Unified Coverage Report :: Module :: edn

Module : edn

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	94.44		83.33	100.00			100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.99	99.02	92.26	96.79	89.47	98.62	99.77

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
edn_csr_assert	100.00						100.00
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_edn_core	91.31	99.92	89.48	70.79	89.47	99.29	98.91
u_edn_cov_if	25.00	50.00	0.00
u_reg	98.63	96.98	98.92	100.00		97.26	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Cond Coverage for Module : edn

	Total	Covered	Percent
Conditions	6	5	83.33
Logical	6	5	83.33
Non-Logical	0	0
Event	0	0

 LINE       99
 EXPRESSION (alert[0] || intg_err_alert[0])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T16,T17,T18

 LINE       99
 EXPRESSION (alert[1] || intg_err_alert[1])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T22,T23,T24
1	0	Covered	T4,T5,T21

---

Toggle Coverage for Module : edn

	Total	Covered	Percent
Totals	69	69	100.00
Total Bits	1168	1168	100.00
Total Bits 0->1	584	584	100.00
Total Bits 1->0	584	584	100.00

Ports	69	69	100.00
Port Bits	1168	1168	100.00
Port Bits 0->1	584	584	100.00
Port Bits 1->0	584	584	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T4,T5,T6	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T16,T6	Yes	T1,T16,T6	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T25,T26,T27	Yes	T25,T26,T27	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T2,*T3,*T4	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i[0].edn_req	Yes	Yes	T3,T4,T16	Yes	T3,T4,T16	INPUT
edn_i[1].edn_req	Yes	Yes	T2,T20,T18	Yes	T2,T20,T18	INPUT
edn_i[2].edn_req	Yes	Yes	T1,T8,T28	Yes	T1,T8,T28	INPUT
edn_i[3].edn_req	Yes	Yes	T7,T29,T30	Yes	T7,T29,T30	INPUT
edn_i[4].edn_req	Yes	Yes	T31,T32,T10	Yes	T31,T32,T10	INPUT
edn_i[5].edn_req	Yes	Yes	T33,T14,T34	Yes	T33,T14,T34	INPUT
edn_i[6].edn_req	Yes	Yes	T30,T35,T36	Yes	T30,T35,T36	INPUT
edn_o[0].edn_bus[31:0]	Yes	Yes	T3,T16,T6	Yes	T3,T16,T6	OUTPUT
edn_o[0].edn_fips	Yes	Yes	T3,T4,T37	Yes	T3,T4,T16	OUTPUT
edn_o[0].edn_ack	Yes	Yes	T3,T4,T16	Yes	T3,T4,T16	OUTPUT
edn_o[1].edn_bus[31:0]	Yes	Yes	T2,T20,T18	Yes	T2,T20,T18	OUTPUT
edn_o[1].edn_fips	Yes	Yes	T2,T30,T38	Yes	T2,T20,T18	OUTPUT
edn_o[1].edn_ack	Yes	Yes	T2,T20,T18	Yes	T2,T20,T18	OUTPUT
edn_o[2].edn_bus[31:0]	Yes	Yes	T1,T8,T28	Yes	T1,T8,T28	OUTPUT
edn_o[2].edn_fips	Yes	Yes	T1,T8,T30	Yes	T1,T8,T30	OUTPUT
edn_o[2].edn_ack	Yes	Yes	T1,T8,T28	Yes	T1,T8,T28	OUTPUT
edn_o[3].edn_bus[31:0]	Yes	Yes	T29,T30,T38	Yes	T29,T30,T38	OUTPUT
edn_o[3].edn_fips	Yes	Yes	T30,T38,T39	Yes	T29,T30,T38	OUTPUT
edn_o[3].edn_ack	Yes	Yes	T29,T30,T38	Yes	T29,T30,T38	OUTPUT
edn_o[4].edn_bus[31:0]	Yes	Yes	T31,T10,T40	Yes	T31,T10,T40	OUTPUT
edn_o[4].edn_fips	Yes	Yes	T32,T30,T38	Yes	T31,T32,T40	OUTPUT
edn_o[4].edn_ack	Yes	Yes	T31,T32,T10	Yes	T31,T32,T10	OUTPUT
edn_o[5].edn_bus[31:0]	Yes	Yes	T33,T14,T34	Yes	T33,T14,T34	OUTPUT
edn_o[5].edn_fips	Yes	Yes	T34,T41,T38	Yes	T14,T34,T41	OUTPUT
edn_o[5].edn_ack	Yes	Yes	T33,T14,T34	Yes	T33,T14,T34	OUTPUT
edn_o[6].edn_bus[31:0]	Yes	Yes	T30,T39,T42	Yes	T30,T39,T42	OUTPUT
edn_o[6].edn_fips	Yes	Yes	T30,T39,T43	Yes	T30,T39,T43	OUTPUT
edn_o[6].edn_ack	Yes	Yes	T30,T39,T42	Yes	T30,T39,T42	OUTPUT
csrng_cmd_o.genbits_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_i.genbits_bus[127:0]	Yes	Yes	T2,T20,T37	Yes	T2,T6,T20	INPUT
csrng_cmd_i.genbits_fips	Yes	Yes	T2,T3,T37	Yes	T2,T6,T37	INPUT
csrng_cmd_i.genbits_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_rsp_sts	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_rsp_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_req_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T16,T17,T18	Yes	T16,T17,T18	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T4,T5,T21	Yes	T4,T5,T21	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T16,T17,T18	Yes	T16,T17,T18	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T4,T5,T21	Yes	T4,T5,T21	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T6,T37,T25	Yes	T6,T37,T25	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T6,T37,T25	Yes	T6,T37,T25	OUTPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Module : edn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	43	43	100.00	43	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	43	43	100.00	43	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnownO_A	188552077	188425938	0	0
CsrngAppIfOut_A	188552077	188425938	0	0
FpvSecCmCntAlertCheck_A	188552077	107	0	0
FpvSecCmMainFsmCheck_A	188552077	70	0	0
FpvSecCmRegWeOnehotCheck_A	188552077	70	0	0
IntrEdnCmdReqDoneKnownO_A	188552077	188425938	0	0
TlAReadyKnownO_A	188552077	188425938	0	0
TlDValidKnownO_A	188552077	188425938	0	0
gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A	188552077	70	0	0
gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A	188552077	70	0	0
gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A	188552077	70	0	0
gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A	188552077	70	0	0
gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A	188552077	70	0	0
gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A	188552077	70	0	0
gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A	188552077	70	0	0
gen_edn_if_asserts[0].EdnDataStableDisable_A	188552077	441510	0	0
gen_edn_if_asserts[0].EdnDataStable_A	188552077	6160	0	159
gen_edn_if_asserts[0].EdnEndPointOut_A	188552077	188425938	0	0
gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A	188552077	128040	0	0
gen_edn_if_asserts[1].EdnDataStableDisable_A	188552077	441510	0	0
gen_edn_if_asserts[1].EdnDataStable_A	188552077	515	0	31
gen_edn_if_asserts[1].EdnEndPointOut_A	188552077	188425938	0	0
gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A	188552077	128040	0	0
gen_edn_if_asserts[2].EdnDataStableDisable_A	188552077	441510	0	0
gen_edn_if_asserts[2].EdnDataStable_A	188552077	627	0	25
gen_edn_if_asserts[2].EdnEndPointOut_A	188552077	188425938	0	0
gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A	188552077	128040	0	0
gen_edn_if_asserts[3].EdnDataStableDisable_A	188552077	441510	0	0
gen_edn_if_asserts[3].EdnDataStable_A	188552077	294	0	16
gen_edn_if_asserts[3].EdnEndPointOut_A	188552077	188425938	0	0
gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A	188552077	128040	0	0
gen_edn_if_asserts[4].EdnDataStableDisable_A	188552077	441510	0	0
gen_edn_if_asserts[4].EdnDataStable_A	188552077	664	0	25
gen_edn_if_asserts[4].EdnEndPointOut_A	188552077	188425938	0	0
gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A	188552077	128040	0	0
gen_edn_if_asserts[5].EdnDataStableDisable_A	188552077	441510	0	0
gen_edn_if_asserts[5].EdnDataStable_A	188552077	262	0	12
gen_edn_if_asserts[5].EdnEndPointOut_A	188552077	188425938	0	0
gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A	188552077	128040	0	0
gen_edn_if_asserts[6].EdnDataStableDisable_A	188552077	441510	0	0
gen_edn_if_asserts[6].EdnDataStable_A	188552077	152	0	7
gen_edn_if_asserts[6].EdnEndPointOut_A	188552077	188425938	0	0
gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A	188552077	128040	0	0

AlertTxKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188552077	188425938	0	0
T1	834	771	0	0
T2	1459	1360	0	0
T3	1106	1034	0	0
T4	575	424	0	0
T5	1096	942	0	0
T6	11106	10673	0	0
T16	1461	1363	0	0
T19	1275	1197	0	0
T20	1080	985	0	0
T21	1752	1635	0	0

CsrngAppIfOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188552077	188425938	0	0
T1	834	771	0	0
T2	1459	1360	0	0
T3	1106	1034	0	0
T4	575	424	0	0
T5	1096	942	0	0
T6	11106	10673	0	0
T16	1461	1363	0	0
T19	1275	1197	0	0
T20	1080	985	0	0
T21	1752	1635	0	0

FpvSecCmCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188552077	107	0	0
T7	1706	1	0	0
T8	1780	1	0	0
T9	0	1	0	0
T15	0	1	0	0
T17	2016	0	0	0
T25	151428	0	0	0
T26	125985	0	0	0
T31	797	0	0	0
T37	12855	0	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	778	0	0	0
T51	814	0	0	0
T52	2350	0	0	0

FpvSecCmMainFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188552077	70	0	0
T22	17531	10	0	0
T23	35708	20	0	0
T24	16254	10	0	0
T53	0	10	0	0
T54	0	20	0	0
T55	1833	0	0	0
T56	1099	0	0	0
T57	1153	0	0	0
T58	1776	0	0	0
T59	956	0	0	0
T60	904	0	0	0
T61	2410	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188552077	70	0	0
T22	17531	10	0	0
T23	35708	20	0	0
T24	16254	10	0	0
T53	0	10	0	0
T54	0	20	0	0
T55	1833	0	0	0
T56	1099	0	0	0
T57	1153	0	0	0
T58	1776	0	0	0
T59	956	0	0	0
T60	904	0	0	0
T61	2410	0	0	0

IntrEdnCmdReqDoneKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188552077	188425938	0	0
T1	834	771	0	0
T2	1459	1360	0	0
T3	1106	1034	0	0
T4	575	424	0	0
T5	1096	942	0	0
T6	11106	10673	0	0
T16	1461	1363	0	0
T19	1275	1197	0	0
T20	1080	985	0	0
T21	1752	1635	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188552077	188425938	0	0
T1	834	771	0	0
T2	1459	1360	0	0
T3	1106	1034	0	0
T4	575	424	0	0
T5	1096	942	0	0
T6	11106	10673	0	0
T16	1461	1363	0	0
T19	1275	1197	0	0
T20	1080	985	0	0
T21	1752	1635	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188552077	188425938	0	0
T1	834	771	0	0
T2	1459	1360	0	0
T3	1106	1034	0	0
T4	575	424	0	0
T5	1096	942	0	0
T6	11106	10673	0	0
T16	1461	1363	0	0
T19	1275	1197	0	0
T20	1080	985	0	0
T21	1752	1635	0	0

gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188552077	70	0	0
T22	17531	10	0	0
T23	35708	20	0	0
T24	16254	10	0	0
T53	0	10	0	0
T54	0	20	0	0
T55	1833	0	0	0
T56	1099	0	0	0
T57	1153	0	0	0
T58	1776	0	0	0
T59	956	0	0	0
T60	904	0	0	0
T61	2410	0	0	0

gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188552077	70	0	0
T22	17531	10	0	0
T23	35708	20	0	0
T24	16254	10	0	0
T53	0	10	0	0
T54	0	20	0	0
T55	1833	0	0	0
T56	1099	0	0	0
T57	1153	0	0	0
T58	1776	0	0	0
T59	956	0	0	0
T60	904	0	0	0
T61	2410	0	0	0

gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188552077	70	0	0
T22	17531	10	0	0
T23	35708	20	0	0
T24	16254	10	0	0
T53	0	10	0	0
T54	0	20	0	0
T55	1833	0	0	0
T56	1099	0	0	0
T57	1153	0	0	0
T58	1776	0	0	0
T59	956	0	0	0
T60	904	0	0	0
T61	2410	0	0	0

gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188552077	70	0	0
T22	17531	10	0	0
T23	35708	20	0	0
T24	16254	10	0	0
T53	0	10	0	0
T54	0	20	0	0
T55	1833	0	0	0
T56	1099	0	0	0
T57	1153	0	0	0
T58	1776	0	0	0
T59	956	0	0	0
T60	904	0	0	0
T61	2410	0	0	0

gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188552077	70	0	0
T22	17531	10	0	0
T23	35708	20	0	0
T24	16254	10	0	0
T53	0	10	0	0
T54	0	20	0	0
T55	1833	0	0	0
T56	1099	0	0	0
T57	1153	0	0	0
T58	1776	0	0	0
T59	956	0	0	0
T60	904	0	0	0
T61	2410	0	0	0

gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188552077	70	0	0
T22	17531	10	0	0
T23	35708	20	0	0
T24	16254	10	0	0
T53	0	10	0	0
T54	0	20	0	0
T55	1833	0	0	0
T56	1099	0	0	0
T57	1153	0	0	0
T58	1776	0	0	0
T59	956	0	0	0
T60	904	0	0	0
T61	2410	0	0	0

gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188552077	70	0	0
T22	17531	10	0	0
T23	35708	20	0	0
T24	16254	10	0	0
T53	0	10	0	0
T54	0	20	0	0
T55	1833	0	0	0
T56	1099	0	0	0
T57	1153	0	0	0
T58	1776	0	0	0
T59	956	0	0	0
T60	904	0	0	0
T61	2410	0	0	0

gen_edn_if_asserts[0].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188552077	441510	0	0
T1	834	68	0	0
T2	1459	77	0	0
T3	1106	14	0	0
T4	575	148	0	0
T5	1096	545	0	0
T6	11106	101	0	0
T16	1461	143	0	0
T19	1275	76	0	0
T20	1080	20	0	0
T21	1752	345	0	0

gen_edn_if_asserts[0].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188552077	6160	0	159
T3	1106	11	0	1
T4	575	0	0	0
T5	1096	0	0	0
T6	11106	9	0	1
T7	1706	0	0	0
T16	1461	4	0	1
T17	2016	4	0	1
T19	1275	3	0	1
T20	1080	0	0	0
T21	1752	0	0	0
T25	0	68	0	0
T26	0	56	0	0
T37	0	18	0	1
T51	0	3	0	1
T62	0	3	0	1
T63	0	0	0	1
T64	0	0	0	1

gen_edn_if_asserts[0].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188552077	188425938	0	0
T1	834	771	0	0
T2	1459	1360	0	0
T3	1106	1034	0	0
T4	575	424	0	0
T5	1096	942	0	0
T6	11106	10673	0	0
T16	1461	1363	0	0
T19	1275	1197	0	0
T20	1080	985	0	0
T21	1752	1635	0	0

gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188552077	128040	0	0
T4	575	255	0	0
T5	1096	660	0	0
T6	11106	0	0	0
T7	1706	964	0	0
T8	0	643	0	0
T16	1461	0	0	0
T17	2016	0	0	0
T19	1275	0	0	0
T20	1080	0	0	0
T21	1752	403	0	0
T32	0	25	0	0
T37	12855	0	0	0
T50	0	432	0	0
T52	0	1112	0	0
T65	0	593	0	0
T66	0	312	0	0

gen_edn_if_asserts[1].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188552077	441510	0	0
T1	834	68	0	0
T2	1459	77	0	0
T3	1106	14	0	0
T4	575	148	0	0
T5	1096	545	0	0
T6	11106	101	0	0
T16	1461	143	0	0
T19	1275	76	0	0
T20	1080	20	0	0
T21	1752	345	0	0

gen_edn_if_asserts[1].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188552077	515	0	31
T2	1459	27	0	1
T3	1106	0	0	0
T4	575	0	0	0
T5	1096	0	0	0
T6	11106	0	0	0
T7	1706	0	0	0
T11	0	37	0	1
T16	1461	0	0	0
T18	0	4	0	1
T19	1275	0	0	0
T20	1080	23	0	1
T21	1752	0	0	0
T30	0	46	0	1
T38	0	26	0	1
T67	0	3	0	0
T68	0	3	0	0
T69	0	33	0	1
T70	0	58	0	1
T71	0	0	0	1
T72	0	0	0	1

gen_edn_if_asserts[1].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188552077	188425938	0	0
T1	834	771	0	0
T2	1459	1360	0	0
T3	1106	1034	0	0
T4	575	424	0	0
T5	1096	942	0	0
T6	11106	10673	0	0
T16	1461	1363	0	0
T19	1275	1197	0	0
T20	1080	985	0	0
T21	1752	1635	0	0

gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188552077	128040	0	0
T4	575	255	0	0
T5	1096	660	0	0
T6	11106	0	0	0
T7	1706	964	0	0
T8	0	643	0	0
T16	1461	0	0	0
T17	2016	0	0	0
T19	1275	0	0	0
T20	1080	0	0	0
T21	1752	403	0	0
T32	0	25	0	0
T37	12855	0	0	0
T50	0	432	0	0
T52	0	1112	0	0
T65	0	593	0	0
T66	0	312	0	0

gen_edn_if_asserts[2].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188552077	441510	0	0
T1	834	68	0	0
T2	1459	77	0	0
T3	1106	14	0	0
T4	575	148	0	0
T5	1096	545	0	0
T6	11106	101	0	0
T16	1461	143	0	0
T19	1275	76	0	0
T20	1080	20	0	0
T21	1752	345	0	0

gen_edn_if_asserts[2].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188552077	627	0	25
T1	834	3	0	0
T2	1459	0	0	0
T3	1106	0	0	0
T4	575	0	0	0
T5	1096	0	0	0
T6	11106	0	0	0
T16	1461	0	0	0
T19	1275	0	0	0
T20	1080	0	0	0
T21	1752	0	0	0
T28	0	3	0	0
T30	0	46	0	1
T38	0	35	0	1
T39	0	54	0	1
T70	0	0	0	1
T73	0	3	0	1
T74	0	4	0	1
T75	0	3	0	1
T76	0	3	0	1
T77	0	3	0	1
T78	0	0	0	1

gen_edn_if_asserts[2].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188552077	188425938	0	0
T1	834	771	0	0
T2	1459	1360	0	0
T3	1106	1034	0	0
T4	575	424	0	0
T5	1096	942	0	0
T6	11106	10673	0	0
T16	1461	1363	0	0
T19	1275	1197	0	0
T20	1080	985	0	0
T21	1752	1635	0	0

gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188552077	128040	0	0
T4	575	255	0	0
T5	1096	660	0	0
T6	11106	0	0	0
T7	1706	964	0	0
T8	0	643	0	0
T16	1461	0	0	0
T17	2016	0	0	0
T19	1275	0	0	0
T20	1080	0	0	0
T21	1752	403	0	0
T32	0	25	0	0
T37	12855	0	0	0
T50	0	432	0	0
T52	0	1112	0	0
T65	0	593	0	0
T66	0	312	0	0

gen_edn_if_asserts[3].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188552077	441510	0	0
T1	834	68	0	0
T2	1459	77	0	0
T3	1106	14	0	0
T4	575	148	0	0
T5	1096	545	0	0
T6	11106	101	0	0
T16	1461	143	0	0
T19	1275	76	0	0
T20	1080	20	0	0
T21	1752	345	0	0

gen_edn_if_asserts[3].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188552077	294	0	16
T11	0	11	0	1
T29	964	3	0	1
T30	2641	12	0	1
T38	1935	11	0	1
T39	0	57	0	1
T43	0	0	0	1
T70	0	14	0	1
T79	0	3	0	0
T80	0	3	0	1
T81	0	4	0	1
T82	0	4	0	1
T83	1066	0	0	0
T84	967	0	0	0
T85	1712	0	0	0
T86	1221	0	0	0
T87	17105	0	0	0
T88	2777	0	0	0
T89	1644	0	0	0

gen_edn_if_asserts[3].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188552077	188425938	0	0
T1	834	771	0	0
T2	1459	1360	0	0
T3	1106	1034	0	0
T4	575	424	0	0
T5	1096	942	0	0
T6	11106	10673	0	0
T16	1461	1363	0	0
T19	1275	1197	0	0
T20	1080	985	0	0
T21	1752	1635	0	0

gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188552077	128040	0	0
T4	575	255	0	0
T5	1096	660	0	0
T6	11106	0	0	0
T7	1706	964	0	0
T8	0	643	0	0
T16	1461	0	0	0
T17	2016	0	0	0
T19	1275	0	0	0
T20	1080	0	0	0
T21	1752	403	0	0
T32	0	25	0	0
T37	12855	0	0	0
T50	0	432	0	0
T52	0	1112	0	0
T65	0	593	0	0
T66	0	312	0	0

gen_edn_if_asserts[4].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188552077	441510	0	0
T1	834	68	0	0
T2	1459	77	0	0
T3	1106	14	0	0
T4	575	148	0	0
T5	1096	545	0	0
T6	11106	101	0	0
T16	1461	143	0	0
T19	1275	76	0	0
T20	1080	20	0	0
T21	1752	345	0	0

gen_edn_if_asserts[4].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188552077	664	0	25
T10	1882	3	0	0
T11	0	27	0	1
T25	151428	0	0	0
T26	125985	0	0	0
T30	0	19	0	1
T31	797	2	0	1
T33	1863	0	0	0
T38	0	46	0	1
T39	0	40	0	1
T40	0	4	0	1
T51	814	0	0	0
T52	2350	0	0	0
T70	0	0	0	1
T89	0	4	0	1
T90	0	45	0	1
T91	0	51	0	1
T92	1015	0	0	0
T93	1865	0	0	0
T94	1641	0	0	0

gen_edn_if_asserts[4].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188552077	188425938	0	0
T1	834	771	0	0
T2	1459	1360	0	0
T3	1106	1034	0	0
T4	575	424	0	0
T5	1096	942	0	0
T6	11106	10673	0	0
T16	1461	1363	0	0
T19	1275	1197	0	0
T20	1080	985	0	0
T21	1752	1635	0	0

gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188552077	128040	0	0
T4	575	255	0	0
T5	1096	660	0	0
T6	11106	0	0	0
T7	1706	964	0	0
T8	0	643	0	0
T16	1461	0	0	0
T17	2016	0	0	0
T19	1275	0	0	0
T20	1080	0	0	0
T21	1752	403	0	0
T32	0	25	0	0
T37	12855	0	0	0
T50	0	432	0	0
T52	0	1112	0	0
T65	0	593	0	0
T66	0	312	0	0

gen_edn_if_asserts[5].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188552077	441510	0	0
T1	834	68	0	0
T2	1459	77	0	0
T3	1106	14	0	0
T4	575	148	0	0
T5	1096	545	0	0
T6	11106	101	0	0
T16	1461	143	0	0
T19	1275	76	0	0
T20	1080	20	0	0
T21	1752	345	0	0

gen_edn_if_asserts[5].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188552077	262	0	12
T9	2243	0	0	0
T13	0	0	0	1
T14	1280	3	0	0
T15	810	0	0	0
T33	1863	4	0	1
T34	0	3	0	0
T38	0	36	0	1
T39	0	57	0	1
T43	0	22	0	1
T59	0	0	0	1
T69	0	5	0	1
T91	0	14	0	1
T94	1641	0	0	0
T95	0	32	0	1
T96	0	3	0	0
T97	832	0	0	0
T98	777	0	0	0
T99	1335	0	0	0
T100	1047	0	0	0
T101	2189	0	0	0
T102	0	0	0	1

gen_edn_if_asserts[5].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188552077	188425938	0	0
T1	834	771	0	0
T2	1459	1360	0	0
T3	1106	1034	0	0
T4	575	424	0	0
T5	1096	942	0	0
T6	11106	10673	0	0
T16	1461	1363	0	0
T19	1275	1197	0	0
T20	1080	985	0	0
T21	1752	1635	0	0

gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188552077	128040	0	0
T4	575	255	0	0
T5	1096	660	0	0
T6	11106	0	0	0
T7	1706	964	0	0
T8	0	643	0	0
T16	1461	0	0	0
T17	2016	0	0	0
T19	1275	0	0	0
T20	1080	0	0	0
T21	1752	403	0	0
T32	0	25	0	0
T37	12855	0	0	0
T50	0	432	0	0
T52	0	1112	0	0
T65	0	593	0	0
T66	0	312	0	0

gen_edn_if_asserts[6].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188552077	441510	0	0
T1	834	68	0	0
T2	1459	77	0	0
T3	1106	14	0	0
T4	575	148	0	0
T5	1096	545	0	0
T6	11106	101	0	0
T16	1461	143	0	0
T19	1275	76	0	0
T20	1080	20	0	0
T21	1752	345	0	0

gen_edn_if_asserts[6].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188552077	152	0	7
T13	0	35	0	1
T30	2641	34	0	1
T39	2177	31	0	1
T42	2042	3	0	0
T43	0	37	0	1
T80	769	0	0	0
T81	1347	0	0	0
T103	0	3	0	1
T104	0	3	0	0
T105	0	3	0	1
T106	0	3	0	1
T107	1481	0	0	0
T108	411184	0	0	0
T109	1046	0	0	0
T110	1528	0	0	0
T111	1290	0	0	0

gen_edn_if_asserts[6].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188552077	188425938	0	0
T1	834	771	0	0
T2	1459	1360	0	0
T3	1106	1034	0	0
T4	575	424	0	0
T5	1096	942	0	0
T6	11106	10673	0	0
T16	1461	1363	0	0
T19	1275	1197	0	0
T20	1080	985	0	0
T21	1752	1635	0	0

gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188552077	128040	0	0
T4	575	255	0	0
T5	1096	660	0	0
T6	11106	0	0	0
T7	1706	964	0	0
T8	0	643	0	0
T16	1461	0	0	0
T17	2016	0	0	0
T19	1275	0	0	0
T20	1080	0	0	0
T21	1752	403	0	0
T32	0	25	0	0
T37	12855	0	0	0
T50	0	432	0	0
T52	0	1112	0	0
T65	0	593	0	0
T66	0	312	0	0