Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44		83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	207313081	9687231	0	0
boot_gen_cmd_rd_A	207313081	47961	0	0
boot_ins_cmd_rd_A	207313081	55138	0	0
ctrl_rd_A	207313081	47762	0	0
err_code_test_rd_A	207313081	48392	0	0
intr_enable_rd_A	207313081	52647	0	0
max_num_reqs_between_reseeds_rd_A	207313081	56078	0	0
regwen_rd_A	207313081	55343	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207313081	9687231	0	0
T5	905	0	0	0
T9	1637	0	0	0
T15	320940	179484	0	0
T16	1614	0	0	0
T17	11173	0	0	0
T20	0	264365	0	0
T21	0	244735	0	0
T22	1923	0	0	0
T23	825	0	0	0
T37	1337	0	0	0
T39	2079	0	0	0
T50	1554	0	0	0
T114	0	258066	0	0
T116	0	157779	0	0
T177	0	357133	0	0
T178	0	83227	0	0
T179	0	261498	0	0
T180	0	230851	0	0
T181	0	142512	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207313081	47961	0	0
T21	680408	6747	0	0
T28	1737	0	0	0
T30	781	0	0	0
T31	1290	0	0	0
T42	938	0	0	0
T98	1328	0	0	0
T113	7875	0	0	0
T116	270500	0	0	0
T181	0	4212	0	0
T182	0	9333	0	0
T183	0	4681	0	0
T184	0	9	0	0
T185	0	15	0	0
T186	0	49	0	0
T187	0	19	0	0
T188	0	37	0	0
T189	0	10	0	0
T190	1237	0	0	0
T191	5132	0	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207313081	55138	0	0
T21	680408	7725	0	0
T28	1737	0	0	0
T30	781	0	0	0
T31	1290	0	0	0
T42	938	0	0	0
T98	1328	0	0	0
T113	7875	0	0	0
T116	270500	0	0	0
T181	0	4561	0	0
T182	0	10268	0	0
T183	0	5759	0	0
T184	0	14	0	0
T185	0	3	0	0
T186	0	55	0	0
T187	0	19	0	0
T188	0	2	0	0
T190	1237	0	0	0
T191	5132	0	0	0
T192	0	48	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207313081	47762	0	0
T21	680408	7176	0	0
T28	1737	0	0	0
T30	781	0	0	0
T31	1290	0	0	0
T35	0	3	0	0
T42	938	0	0	0
T98	1328	0	0	0
T113	7875	0	0	0
T116	270500	0	0	0
T119	0	1	0	0
T181	0	3883	0	0
T182	0	8930	0	0
T183	0	5159	0	0
T184	0	1	0	0
T185	0	9	0	0
T186	0	31	0	0
T187	0	37	0	0
T190	1237	0	0	0
T191	5132	0	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207313081	48392	0	0
T21	680408	7148	0	0
T28	1737	0	0	0
T30	781	0	0	0
T31	1290	0	0	0
T42	938	0	0	0
T98	1328	0	0	0
T113	7875	0	0	0
T116	270500	0	0	0
T181	0	3791	0	0
T182	0	9043	0	0
T183	0	4781	0	0
T184	0	6	0	0
T185	0	22	0	0
T186	0	25	0	0
T187	0	17	0	0
T188	0	35	0	0
T190	1237	0	0	0
T191	5132	0	0	0
T192	0	9	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207313081	52647	0	0
T21	680408	7075	0	0
T28	1737	0	0	0
T30	781	0	0	0
T31	1290	0	0	0
T42	938	0	0	0
T98	1328	0	0	0
T112	0	67	0	0
T113	7875	0	0	0
T116	270500	0	0	0
T181	0	4324	0	0
T182	0	9042	0	0
T183	0	5486	0	0
T184	0	19	0	0
T190	1237	0	0	0
T191	5132	0	0	0
T193	0	80	0	0
T194	0	9	0	0
T195	0	15	0	0
T196	0	133	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207313081	56078	0	0
T21	680408	8260	0	0
T28	1737	0	0	0
T30	781	0	0	0
T31	1290	0	0	0
T42	938	0	0	0
T98	1328	0	0	0
T113	7875	0	0	0
T116	270500	0	0	0
T181	0	4465	0	0
T182	0	10665	0	0
T183	0	5791	0	0
T184	0	11	0	0
T185	0	22	0	0
T186	0	49	0	0
T187	0	18	0	0
T190	1237	0	0	0
T191	5132	0	0	0
T192	0	21	0	0
T196	0	172	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207313081	55343	0	0
T21	680408	7559	0	0
T28	1737	0	0	0
T30	781	0	0	0
T31	1290	0	0	0
T42	938	0	0	0
T98	1328	0	0	0
T113	7875	0	0	0
T116	270500	0	0	0
T181	0	4735	0	0
T182	0	10541	0	0
T183	0	5468	0	0
T184	0	3	0	0
T185	0	7	0	0
T186	0	42	0	0
T187	0	19	0	0
T190	1237	0	0	0
T191	5132	0	0	0
T192	0	19	0	0
T196	0	113	0	0