Unified Coverage Report :: Module :: edn

Module : edn

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	94.44		83.33	100.00			100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.68	99.02	92.39	96.84	93.42	98.62	99.77

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
edn_csr_assert	100.00						100.00
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_edn_core	92.09	99.92	89.68	71.29	93.42	99.29	98.91
u_edn_cov_if	25.00	50.00	0.00
u_reg	98.63	96.98	98.92	100.00		97.26	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Cond Coverage for Module : edn

	Total	Covered	Percent
Conditions	6	5	83.33
Logical	6	5	83.33
Non-Logical	0	0
Event	0	0

 LINE       99
 EXPRESSION (alert[0] || intg_err_alert[0])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T9,T10,T11

 LINE       99
 EXPRESSION (alert[1] || intg_err_alert[1])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T18,T19
1	0	Covered	T1,T2,T4

---

Toggle Coverage for Module : edn

	Total	Covered	Percent
Totals	69	69	100.00
Total Bits	1168	1168	100.00
Total Bits 0->1	584	584	100.00
Total Bits 1->0	584	584	100.00

Ports	69	69	100.00
Port Bits	1168	1168	100.00
Port Bits 0->1	584	584	100.00
Port Bits 1->0	584	584	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T12,T15	Yes	T1,T12,T15	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T12	Yes	T1,T2,T12	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T15,T20,T21	Yes	T15,T20,T21	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i[0].edn_req	Yes	Yes	T1,T13,T14	Yes	T1,T13,T14	INPUT
edn_i[1].edn_req	Yes	Yes	T4,T22,T23	Yes	T4,T22,T23	INPUT
edn_i[2].edn_req	Yes	Yes	T12,T24,T25	Yes	T12,T24,T25	INPUT
edn_i[3].edn_req	Yes	Yes	T2,T26,T25	Yes	T2,T26,T25	INPUT
edn_i[4].edn_req	Yes	Yes	T3,T9,T10	Yes	T3,T9,T10	INPUT
edn_i[5].edn_req	Yes	Yes	T27,T25,T28	Yes	T27,T25,T28	INPUT
edn_i[6].edn_req	Yes	Yes	T5,T6,T25	Yes	T5,T6,T25	INPUT
edn_o[0].edn_bus[31:0]	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
edn_o[0].edn_fips	Yes	Yes	T13,T15,T17	Yes	T13,T15,T17	OUTPUT
edn_o[0].edn_ack	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	OUTPUT
edn_o[1].edn_bus[31:0]	Yes	Yes	T4,T23,T29	Yes	T4,T23,T29	OUTPUT
edn_o[1].edn_fips	Yes	Yes	T25,T8,T30	Yes	T25,T8,T30	OUTPUT
edn_o[1].edn_ack	Yes	Yes	T23,T29,T25	Yes	T23,T29,T25	OUTPUT
edn_o[2].edn_bus[31:0]	Yes	Yes	T24,T25,T8	Yes	T24,T25,T8	OUTPUT
edn_o[2].edn_fips	Yes	Yes	T25,T8,T31	Yes	T24,T25,T8	OUTPUT
edn_o[2].edn_ack	Yes	Yes	T12,T24,T25	Yes	T12,T24,T25	OUTPUT
edn_o[3].edn_bus[31:0]	Yes	Yes	T26,T25,T8	Yes	T26,T25,T8	OUTPUT
edn_o[3].edn_fips	Yes	Yes	T2,T32,T33	Yes	T2,T25,T8	OUTPUT
edn_o[3].edn_ack	Yes	Yes	T2,T26,T25	Yes	T2,T26,T25	OUTPUT
edn_o[4].edn_bus[31:0]	Yes	Yes	T3,T9,T10	Yes	T3,T9,T10	OUTPUT
edn_o[4].edn_fips	Yes	Yes	T3,T25,T8	Yes	T3,T25,T8	OUTPUT
edn_o[4].edn_ack	Yes	Yes	T3,T9,T10	Yes	T3,T9,T10	OUTPUT
edn_o[5].edn_bus[31:0]	Yes	Yes	T27,T25,T28	Yes	T27,T25,T28	OUTPUT
edn_o[5].edn_fips	Yes	Yes	T25,T34,T35	Yes	T27,T25,T28	OUTPUT
edn_o[5].edn_ack	Yes	Yes	T27,T25,T28	Yes	T27,T25,T28	OUTPUT
edn_o[6].edn_bus[31:0]	Yes	Yes	T5,T6,T25	Yes	T5,T6,T25	OUTPUT
edn_o[6].edn_fips	Yes	Yes	T6,T25,T36	Yes	T6,T25,T36	OUTPUT
edn_o[6].edn_ack	Yes	Yes	T5,T6,T25	Yes	T5,T6,T25	OUTPUT
csrng_cmd_o.genbits_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
csrng_cmd_o.csrng_req_valid	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
csrng_cmd_i.genbits_bus[127:0]	Yes	Yes	T3,T14,T15	Yes	T3,T15,T17	INPUT
csrng_cmd_i.genbits_fips	Yes	Yes	T3,T15,T17	Yes	T3,T15,T37	INPUT
csrng_cmd_i.genbits_valid	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
csrng_cmd_i.csrng_rsp_sts	Yes	Yes	T3,T4,T13	Yes	T3,T4,T13	INPUT
csrng_cmd_i.csrng_rsp_ack	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
csrng_cmd_i.csrng_req_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T16,T9,T38	Yes	T16,T9,T38	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T16,T9,T38	Yes	T16,T9,T38	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T14,T15,T17	Yes	T14,T15,T17	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T2,T13,T14	Yes	T2,T13,T14	OUTPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Module : edn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	43	43	100.00	43	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	43	43	100.00	43	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnownO_A	206809062	206676795	0	0
CsrngAppIfOut_A	206809062	206676795	0	0
FpvSecCmCntAlertCheck_A	206809062	132	0	0
FpvSecCmMainFsmCheck_A	206809062	80	0	0
FpvSecCmRegWeOnehotCheck_A	206809062	80	0	0
IntrEdnCmdReqDoneKnownO_A	206809062	206676795	0	0
TlAReadyKnownO_A	206809062	206676795	0	0
TlDValidKnownO_A	206809062	206676795	0	0
gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A	206809062	80	0	0
gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A	206809062	80	0	0
gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A	206809062	80	0	0
gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A	206809062	80	0	0
gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A	206809062	80	0	0
gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A	206809062	80	0	0
gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A	206809062	80	0	0
gen_edn_if_asserts[0].EdnDataStableDisable_A	206809062	471857	0	0
gen_edn_if_asserts[0].EdnDataStable_A	206809062	6591	0	154
gen_edn_if_asserts[0].EdnEndPointOut_A	206809062	206676795	0	0
gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A	206809062	132954	0	0
gen_edn_if_asserts[1].EdnDataStableDisable_A	206809062	471857	0	0
gen_edn_if_asserts[1].EdnDataStable_A	206809062	771	0	26
gen_edn_if_asserts[1].EdnEndPointOut_A	206809062	206676795	0	0
gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A	206809062	132954	0	0
gen_edn_if_asserts[2].EdnDataStableDisable_A	206809062	471857	0	0
gen_edn_if_asserts[2].EdnDataStable_A	206809062	581	0	29
gen_edn_if_asserts[2].EdnEndPointOut_A	206809062	206676795	0	0
gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A	206809062	132954	0	0
gen_edn_if_asserts[3].EdnDataStableDisable_A	206809062	471857	0	0
gen_edn_if_asserts[3].EdnDataStable_A	206809062	661	0	28
gen_edn_if_asserts[3].EdnEndPointOut_A	206809062	206676795	0	0
gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A	206809062	132954	0	0
gen_edn_if_asserts[4].EdnDataStableDisable_A	206809062	471857	0	0
gen_edn_if_asserts[4].EdnDataStable_A	206809062	584	0	25
gen_edn_if_asserts[4].EdnEndPointOut_A	206809062	206676795	0	0
gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A	206809062	132954	0	0
gen_edn_if_asserts[5].EdnDataStableDisable_A	206809062	471857	0	0
gen_edn_if_asserts[5].EdnDataStable_A	206809062	391	0	24
gen_edn_if_asserts[5].EdnEndPointOut_A	206809062	206676795	0	0
gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A	206809062	132954	0	0
gen_edn_if_asserts[6].EdnDataStableDisable_A	206809062	471857	0	0
gen_edn_if_asserts[6].EdnDataStable_A	206809062	376	0	18
gen_edn_if_asserts[6].EdnEndPointOut_A	206809062	206676795	0	0
gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A	206809062	132954	0	0

AlertTxKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206809062	206676795	0	0
T1	15669	8144	0	0
T2	731	612	0	0
T3	1810	1726	0	0
T4	1217	1079	0	0
T12	624	455	0	0
T13	1963	1773	0	0
T14	5214	5003	0	0
T15	320940	320928	0	0
T16	1614	1548	0	0
T17	11173	10536	0	0

CsrngAppIfOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206809062	206676795	0	0
T1	15669	8144	0	0
T2	731	612	0	0
T3	1810	1726	0	0
T4	1217	1079	0	0
T12	624	455	0	0
T13	1963	1773	0	0
T14	5214	5003	0	0
T15	320940	320928	0	0
T16	1614	1548	0	0
T17	11173	10536	0	0

FpvSecCmCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206809062	132	0	0
T1	15669	10	0	0
T2	731	1	0	0
T3	1810	0	0	0
T4	1217	1	0	0
T6	0	1	0	0
T12	624	0	0	0
T13	1963	0	0	0
T14	5214	0	0	0
T15	320940	0	0	0
T16	1614	0	0	0
T17	11173	0	0	0
T18	0	10	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0

FpvSecCmMainFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206809062	80	0	0
T1	15669	10	0	0
T2	731	0	0	0
T3	1810	0	0	0
T4	1217	0	0	0
T12	624	0	0	0
T13	1963	0	0	0
T14	5214	0	0	0
T15	320940	0	0	0
T16	1614	0	0	0
T17	11173	0	0	0
T18	0	10	0	0
T19	0	20	0	0
T44	0	20	0	0
T45	0	20	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206809062	80	0	0
T1	15669	10	0	0
T2	731	0	0	0
T3	1810	0	0	0
T4	1217	0	0	0
T12	624	0	0	0
T13	1963	0	0	0
T14	5214	0	0	0
T15	320940	0	0	0
T16	1614	0	0	0
T17	11173	0	0	0
T18	0	10	0	0
T19	0	20	0	0
T44	0	20	0	0
T45	0	20	0	0

IntrEdnCmdReqDoneKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206809062	206676795	0	0
T1	15669	8144	0	0
T2	731	612	0	0
T3	1810	1726	0	0
T4	1217	1079	0	0
T12	624	455	0	0
T13	1963	1773	0	0
T14	5214	5003	0	0
T15	320940	320928	0	0
T16	1614	1548	0	0
T17	11173	10536	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206809062	206676795	0	0
T1	15669	8144	0	0
T2	731	612	0	0
T3	1810	1726	0	0
T4	1217	1079	0	0
T12	624	455	0	0
T13	1963	1773	0	0
T14	5214	5003	0	0
T15	320940	320928	0	0
T16	1614	1548	0	0
T17	11173	10536	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206809062	206676795	0	0
T1	15669	8144	0	0
T2	731	612	0	0
T3	1810	1726	0	0
T4	1217	1079	0	0
T12	624	455	0	0
T13	1963	1773	0	0
T14	5214	5003	0	0
T15	320940	320928	0	0
T16	1614	1548	0	0
T17	11173	10536	0	0

gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206809062	80	0	0
T1	15669	10	0	0
T2	731	0	0	0
T3	1810	0	0	0
T4	1217	0	0	0
T12	624	0	0	0
T13	1963	0	0	0
T14	5214	0	0	0
T15	320940	0	0	0
T16	1614	0	0	0
T17	11173	0	0	0
T18	0	10	0	0
T19	0	20	0	0
T44	0	20	0	0
T45	0	20	0	0

gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206809062	80	0	0
T1	15669	10	0	0
T2	731	0	0	0
T3	1810	0	0	0
T4	1217	0	0	0
T12	624	0	0	0
T13	1963	0	0	0
T14	5214	0	0	0
T15	320940	0	0	0
T16	1614	0	0	0
T17	11173	0	0	0
T18	0	10	0	0
T19	0	20	0	0
T44	0	20	0	0
T45	0	20	0	0

gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206809062	80	0	0
T1	15669	10	0	0
T2	731	0	0	0
T3	1810	0	0	0
T4	1217	0	0	0
T12	624	0	0	0
T13	1963	0	0	0
T14	5214	0	0	0
T15	320940	0	0	0
T16	1614	0	0	0
T17	11173	0	0	0
T18	0	10	0	0
T19	0	20	0	0
T44	0	20	0	0
T45	0	20	0	0

gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206809062	80	0	0
T1	15669	10	0	0
T2	731	0	0	0
T3	1810	0	0	0
T4	1217	0	0	0
T12	624	0	0	0
T13	1963	0	0	0
T14	5214	0	0	0
T15	320940	0	0	0
T16	1614	0	0	0
T17	11173	0	0	0
T18	0	10	0	0
T19	0	20	0	0
T44	0	20	0	0
T45	0	20	0	0

gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206809062	80	0	0
T1	15669	10	0	0
T2	731	0	0	0
T3	1810	0	0	0
T4	1217	0	0	0
T12	624	0	0	0
T13	1963	0	0	0
T14	5214	0	0	0
T15	320940	0	0	0
T16	1614	0	0	0
T17	11173	0	0	0
T18	0	10	0	0
T19	0	20	0	0
T44	0	20	0	0
T45	0	20	0	0

gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206809062	80	0	0
T1	15669	10	0	0
T2	731	0	0	0
T3	1810	0	0	0
T4	1217	0	0	0
T12	624	0	0	0
T13	1963	0	0	0
T14	5214	0	0	0
T15	320940	0	0	0
T16	1614	0	0	0
T17	11173	0	0	0
T18	0	10	0	0
T19	0	20	0	0
T44	0	20	0	0
T45	0	20	0	0

gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206809062	80	0	0
T1	15669	10	0	0
T2	731	0	0	0
T3	1810	0	0	0
T4	1217	0	0	0
T12	624	0	0	0
T13	1963	0	0	0
T14	5214	0	0	0
T15	320940	0	0	0
T16	1614	0	0	0
T17	11173	0	0	0
T18	0	10	0	0
T19	0	20	0	0
T44	0	20	0	0
T45	0	20	0	0

gen_edn_if_asserts[0].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206809062	471857	0	0
T1	15669	6809	0	0
T2	731	287	0	0
T3	1810	225	0	0
T4	1217	762	0	0
T12	624	181	0	0
T13	1963	1043	0	0
T14	5214	730	0	0
T15	320940	1140	0	0
T16	1614	1547	0	0
T17	11173	2514	0	0

gen_edn_if_asserts[0].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206809062	6591	0	154
T5	905	0	0	0
T7	0	0	0	1
T14	5214	6	0	0
T15	320940	81	0	0
T16	1614	0	0	0
T17	11173	9	0	0
T20	0	144	0	0
T22	1923	0	0	0
T23	825	0	0	0
T24	0	11	0	1
T25	0	0	0	1
T37	1337	27	0	1
T39	2079	0	0	0
T46	0	3	0	1
T47	0	3	0	1
T48	0	3	0	1
T49	0	3	0	1
T50	1554	0	0	0
T51	0	0	0	1
T52	0	0	0	1

gen_edn_if_asserts[0].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206809062	206676795	0	0
T1	15669	8144	0	0
T2	731	612	0	0
T3	1810	1726	0	0
T4	1217	1079	0	0
T12	624	455	0	0
T13	1963	1773	0	0
T14	5214	5003	0	0
T15	320940	320928	0	0
T16	1614	1548	0	0
T17	11173	10536	0	0

gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206809062	132954	0	0
T1	15669	4750	0	0
T2	731	350	0	0
T3	1810	0	0	0
T4	1217	410	0	0
T5	0	362	0	0
T12	624	257	0	0
T13	1963	30	0	0
T14	5214	0	0	0
T15	320940	0	0	0
T16	1614	0	0	0
T17	11173	0	0	0
T22	0	1116	0	0
T39	0	614	0	0
T40	0	372	0	0
T50	0	282	0	0

gen_edn_if_asserts[1].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206809062	471857	0	0
T1	15669	6809	0	0
T2	731	287	0	0
T3	1810	225	0	0
T4	1217	762	0	0
T12	624	181	0	0
T13	1963	1043	0	0
T14	5214	730	0	0
T15	320940	1140	0	0
T16	1614	1547	0	0
T17	11173	2514	0	0

gen_edn_if_asserts[1].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206809062	771	0	26
T8	0	27	0	1
T9	1637	0	0	0
T23	825	3	0	0
T25	2297	31	0	1
T31	0	28	0	1
T32	0	0	0	1
T33	0	0	0	1
T39	2079	0	0	0
T40	783	0	0	0
T46	1092	0	0	0
T47	1600	0	0	0
T53	0	22	0	1
T54	0	4	0	0
T55	0	37	0	1
T56	0	3	0	0
T57	0	53	0	1
T58	0	3	0	0
T59	988	0	0	0
T60	5861	0	0	0
T61	1420	0	0	0
T62	0	0	0	1
T63	0	0	0	1

gen_edn_if_asserts[1].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206809062	206676795	0	0
T1	15669	8144	0	0
T2	731	612	0	0
T3	1810	1726	0	0
T4	1217	1079	0	0
T12	624	455	0	0
T13	1963	1773	0	0
T14	5214	5003	0	0
T15	320940	320928	0	0
T16	1614	1548	0	0
T17	11173	10536	0	0

gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206809062	132954	0	0
T1	15669	4750	0	0
T2	731	350	0	0
T3	1810	0	0	0
T4	1217	410	0	0
T5	0	362	0	0
T12	624	257	0	0
T13	1963	30	0	0
T14	5214	0	0	0
T15	320940	0	0	0
T16	1614	0	0	0
T17	11173	0	0	0
T22	0	1116	0	0
T39	0	614	0	0
T40	0	372	0	0
T50	0	282	0	0

gen_edn_if_asserts[2].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206809062	471857	0	0
T1	15669	6809	0	0
T2	731	287	0	0
T3	1810	225	0	0
T4	1217	762	0	0
T12	624	181	0	0
T13	1963	1043	0	0
T14	5214	730	0	0
T15	320940	1140	0	0
T16	1614	1547	0	0
T17	11173	2514	0	0

gen_edn_if_asserts[2].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206809062	581	0	29
T6	629	0	0	0
T8	0	45	0	1
T10	1493	0	0	0
T20	468250	0	0	0
T24	969	4	0	1
T25	0	31	0	1
T26	2078	0	0	0
T27	2191	0	0	0
T31	0	19	0	1
T38	1136	0	0	0
T48	963	0	0	0
T53	0	36	0	1
T55	0	55	0	1
T64	0	3	0	1
T65	0	4	0	1
T66	0	4	0	1
T67	0	3	0	1
T68	1034	0	0	0
T69	919	0	0	0

gen_edn_if_asserts[2].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206809062	206676795	0	0
T1	15669	8144	0	0
T2	731	612	0	0
T3	1810	1726	0	0
T4	1217	1079	0	0
T12	624	455	0	0
T13	1963	1773	0	0
T14	5214	5003	0	0
T15	320940	320928	0	0
T16	1614	1548	0	0
T17	11173	10536	0	0

gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206809062	132954	0	0
T1	15669	4750	0	0
T2	731	350	0	0
T3	1810	0	0	0
T4	1217	410	0	0
T5	0	362	0	0
T12	624	257	0	0
T13	1963	30	0	0
T14	5214	0	0	0
T15	320940	0	0	0
T16	1614	0	0	0
T17	11173	0	0	0
T22	0	1116	0	0
T39	0	614	0	0
T40	0	372	0	0
T50	0	282	0	0

gen_edn_if_asserts[3].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206809062	471857	0	0
T1	15669	6809	0	0
T2	731	287	0	0
T3	1810	225	0	0
T4	1217	762	0	0
T12	624	181	0	0
T13	1963	1043	0	0
T14	5214	730	0	0
T15	320940	1140	0	0
T16	1614	1547	0	0
T17	11173	2514	0	0

gen_edn_if_asserts[3].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206809062	661	0	28
T8	0	12	0	1
T25	0	15	0	1
T26	2078	3	0	0
T29	1315	0	0	0
T31	0	15	0	1
T32	0	11	0	1
T33	0	43	0	1
T41	1797	0	0	0
T49	1698	0	0	0
T51	1440	0	0	0
T52	1276	0	0	0
T69	919	0	0	0
T70	0	3	0	0
T71	0	3	0	1
T72	0	4	0	1
T73	0	4	0	1
T74	1467	0	0	0
T75	534	0	0	0
T76	4388	0	0	0
T77	0	0	0	1
T78	0	0	0	1

gen_edn_if_asserts[3].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206809062	206676795	0	0
T1	15669	8144	0	0
T2	731	612	0	0
T3	1810	1726	0	0
T4	1217	1079	0	0
T12	624	455	0	0
T13	1963	1773	0	0
T14	5214	5003	0	0
T15	320940	320928	0	0
T16	1614	1548	0	0
T17	11173	10536	0	0

gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206809062	132954	0	0
T1	15669	4750	0	0
T2	731	350	0	0
T3	1810	0	0	0
T4	1217	410	0	0
T5	0	362	0	0
T12	624	257	0	0
T13	1963	30	0	0
T14	5214	0	0	0
T15	320940	0	0	0
T16	1614	0	0	0
T17	11173	0	0	0
T22	0	1116	0	0
T39	0	614	0	0
T40	0	372	0	0
T50	0	282	0	0

gen_edn_if_asserts[4].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206809062	471857	0	0
T1	15669	6809	0	0
T2	731	287	0	0
T3	1810	225	0	0
T4	1217	762	0	0
T12	624	181	0	0
T13	1963	1043	0	0
T14	5214	730	0	0
T15	320940	1140	0	0
T16	1614	1547	0	0
T17	11173	2514	0	0

gen_edn_if_asserts[4].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206809062	584	0	25
T3	1810	57	0	1
T4	1217	0	0	0
T5	905	0	0	0
T8	0	42	0	1
T9	0	4	0	1
T10	0	4	0	1
T12	624	0	0	0
T13	1963	0	0	0
T14	5214	0	0	0
T15	320940	0	0	0
T16	1614	0	0	0
T17	11173	0	0	0
T25	0	24	0	1
T31	0	20	0	1
T33	0	0	0	1
T50	1554	0	0	0
T79	0	3	0	1
T80	0	4	0	1
T81	0	3	0	0
T82	0	3	0	1

gen_edn_if_asserts[4].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206809062	206676795	0	0
T1	15669	8144	0	0
T2	731	612	0	0
T3	1810	1726	0	0
T4	1217	1079	0	0
T12	624	455	0	0
T13	1963	1773	0	0
T14	5214	5003	0	0
T15	320940	320928	0	0
T16	1614	1548	0	0
T17	11173	10536	0	0

gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206809062	132954	0	0
T1	15669	4750	0	0
T2	731	350	0	0
T3	1810	0	0	0
T4	1217	410	0	0
T5	0	362	0	0
T12	624	257	0	0
T13	1963	30	0	0
T14	5214	0	0	0
T15	320940	0	0	0
T16	1614	0	0	0
T17	11173	0	0	0
T22	0	1116	0	0
T39	0	614	0	0
T40	0	372	0	0
T50	0	282	0	0

gen_edn_if_asserts[5].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206809062	471857	0	0
T1	15669	6809	0	0
T2	731	287	0	0
T3	1810	225	0	0
T4	1217	762	0	0
T12	624	181	0	0
T13	1963	1043	0	0
T14	5214	730	0	0
T15	320940	1140	0	0
T16	1614	1547	0	0
T17	11173	2514	0	0

gen_edn_if_asserts[5].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206809062	391	0	24
T6	629	0	0	0
T10	1493	0	0	0
T20	468250	0	0	0
T25	0	62	0	1
T26	2078	0	0	0
T27	2191	3	0	0
T28	0	3	0	0
T31	0	8	0	1
T33	0	6	0	1
T34	0	3	0	1
T38	1136	0	0	0
T68	1034	0	0	0
T69	919	0	0	0
T74	1467	0	0	0
T75	534	0	0	0
T78	0	52	0	1
T83	0	3	0	0
T84	0	3	0	0
T85	0	3	0	1
T86	0	0	0	1
T87	0	0	0	1
T88	0	0	0	1
T89	0	0	0	1

gen_edn_if_asserts[5].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206809062	206676795	0	0
T1	15669	8144	0	0
T2	731	612	0	0
T3	1810	1726	0	0
T4	1217	1079	0	0
T12	624	455	0	0
T13	1963	1773	0	0
T14	5214	5003	0	0
T15	320940	320928	0	0
T16	1614	1548	0	0
T17	11173	10536	0	0

gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206809062	132954	0	0
T1	15669	4750	0	0
T2	731	350	0	0
T3	1810	0	0	0
T4	1217	410	0	0
T5	0	362	0	0
T12	624	257	0	0
T13	1963	30	0	0
T14	5214	0	0	0
T15	320940	0	0	0
T16	1614	0	0	0
T17	11173	0	0	0
T22	0	1116	0	0
T39	0	614	0	0
T40	0	372	0	0
T50	0	282	0	0

gen_edn_if_asserts[6].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206809062	471857	0	0
T1	15669	6809	0	0
T2	731	287	0	0
T3	1810	225	0	0
T4	1217	762	0	0
T12	624	181	0	0
T13	1963	1043	0	0
T14	5214	730	0	0
T15	320940	1140	0	0
T16	1614	1547	0	0
T17	11173	2514	0	0

gen_edn_if_asserts[6].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206809062	376	0	18
T8	2521	0	0	0
T21	680408	0	0	0
T25	2297	56	0	1
T32	0	40	0	1
T33	0	33	0	1
T36	0	3	0	1
T59	988	0	0	0
T60	5861	0	0	0
T61	1420	0	0	0
T89	0	38	0	1
T90	0	3	0	0
T91	0	3	0	1
T92	0	3	0	0
T93	0	3	0	1
T94	0	7	0	1
T95	1281	0	0	0
T96	1896	0	0	0
T97	1650	0	0	0
T98	1328	0	0	0
T99	0	0	0	1
T100	0	0	0	1

gen_edn_if_asserts[6].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206809062	206676795	0	0
T1	15669	8144	0	0
T2	731	612	0	0
T3	1810	1726	0	0
T4	1217	1079	0	0
T12	624	455	0	0
T13	1963	1773	0	0
T14	5214	5003	0	0
T15	320940	320928	0	0
T16	1614	1548	0	0
T17	11173	10536	0	0

gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206809062	132954	0	0
T1	15669	4750	0	0
T2	731	350	0	0
T3	1810	0	0	0
T4	1217	410	0	0
T5	0	362	0	0
T12	624	257	0	0
T13	1963	30	0	0
T14	5214	0	0	0
T15	320940	0	0	0
T16	1614	0	0	0
T17	11173	0	0	0
T22	0	1116	0	0
T39	0	614	0	0
T40	0	372	0	0
T50	0	282	0	0