EDN Simulation Results

Sunday October 01 2023 19:02:47 UTC

GitHub Revision: 7b89440c3

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 3649974514

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	1.060s	30.148us	50	50	100.00
V1	csr_hw_reset	edn_csr_hw_reset	0.940s	28.560us	5	5	100.00
V1	csr_rw	edn_csr_rw	0.920s	15.492us	20	20	100.00
V1	csr_bit_bash	edn_csr_bit_bash	6.140s	256.194us	5	5	100.00
V1	csr_aliasing	edn_csr_aliasing	1.390s	35.595us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	1.840s	33.187us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	0.920s	15.492us	20	20	100.00
		edn_csr_aliasing	1.390s	35.595us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	firmware	edn_genbits	1.600s	68.658us	50	50	100.00
V2	csrng_commands	edn_genbits	1.600s	68.658us	50	50	100.00
V2	genbits	edn_genbits	1.600s	68.658us	50	50	100.00
V2	interrupts	edn_intr	1.160s	23.422us	50	50	100.00
V2	alerts	edn_alert	1.070s	20.205us	50	50	100.00
V2	errs	edn_err	1.430s	18.359us	100	100	100.00
V2	disable	edn_disable	0.930s	12.623us	49	50	98.00
		edn_disable_auto_req_mode	1.160s	69.311us	50	50	100.00
V2	stress_all	edn_stress_all	4.480s	1.028ms	50	50	100.00
V2	intr_test	edn_intr_test	0.910s	16.289us	50	50	100.00
V2	alert_test	edn_alert_test	1.310s	45.743us	50	50	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	4.080s	431.306us	20	20	100.00
V2	tl_d_illegal_access	edn_tl_errors	4.080s	431.306us	20	20	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	0.940s	28.560us	5	5	100.00
		edn_csr_rw	0.920s	15.492us	20	20	100.00
		edn_csr_aliasing	1.390s	35.595us	5	5	100.00
		edn_same_csr_outstanding	1.390s	32.889us	20	20	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	0.940s	28.560us	5	5	100.00
		edn_csr_rw	0.920s	15.492us	20	20	100.00
		edn_csr_aliasing	1.390s	35.595us	5	5	100.00
		edn_same_csr_outstanding	1.390s	32.889us	20	20	100.00
V2		TOTAL			539	540	99.81
V2S	tl_intg_err	edn_sec_cm	6.360s	417.383us	5	5	100.00
		edn_tl_intg_err	2.930s	277.556us	20	20	100.00
V2S	sec_cm_config_regwen	edn_regwen	0.900s	46.221us	10	10	100.00
V2S	sec_cm_config_mubi	edn_alert	1.070s	20.205us	50	50	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	6.360s	417.383us	5	5	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	6.360s	417.383us	5	5	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	6.360s	417.383us	5	5	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.070s	20.205us	50	50	100.00
		edn_sec_cm	6.360s	417.383us	5	5	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.070s	20.205us	50	50	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	2.930s	277.556us	20	20	100.00
V2S		TOTAL			35	35	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	35.985m	98.516ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			729	730	99.86

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	10	90.91
V2S	3	3	3	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.89	99.02	92.39	96.84	93.42	98.62	99.77	98.14

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
  • Test edn_disable has 1 failures.

    • 16.edn_disable.1657592673
      Line 210, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/16.edn_disable/latest/run.log

        UVM_FATAL @ 100000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 100000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 100000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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