Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44		83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	240480752	11237132	0	0
boot_gen_cmd_rd_A	240480752	56207	0	0
boot_ins_cmd_rd_A	240480752	64394	0	0
ctrl_rd_A	240480752	57097	0	0
err_code_test_rd_A	240480752	55818	0	0
intr_enable_rd_A	240480752	62307	0	0
max_num_reqs_between_reseeds_rd_A	240480752	65719	0	0
regwen_rd_A	240480752	65641	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	240480752	11237132	0	0
T20	154232	54655	0	0
T21	341121	121740	0	0
T22	0	212582	0	0
T36	2081	0	0	0
T38	1382	0	0	0
T47	680	0	0	0
T67	2037	0	0	0
T81	1236	0	0	0
T119	1759	0	0	0
T122	1497	0	0	0
T180	0	628472	0	0
T181	0	162857	0	0
T182	0	93231	0	0
T183	0	409731	0	0
T184	0	82265	0	0
T185	0	313631	0	0
T186	0	270860	0	0
T187	1009	0	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	240480752	56207	0	0
T20	154232	1468	0	0
T21	341121	3658	0	0
T36	2081	0	0	0
T38	1382	0	0	0
T47	680	0	0	0
T67	2037	0	0	0
T81	1236	0	0	0
T119	1759	0	0	0
T122	1497	0	0	0
T187	1009	0	0	0
T188	0	8846	0	0
T189	0	14	0	0
T190	0	18	0	0
T191	0	11	0	0
T192	0	19	0	0
T193	0	65	0	0
T194	0	13	0	0
T195	0	9	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	240480752	64394	0	0
T20	154232	1928	0	0
T21	341121	4073	0	0
T36	2081	0	0	0
T38	1382	0	0	0
T47	680	0	0	0
T67	2037	0	0	0
T81	1236	0	0	0
T119	1759	0	0	0
T122	1497	0	0	0
T187	1009	0	0	0
T188	0	10658	0	0
T189	0	2	0	0
T190	0	25	0	0
T191	0	7	0	0
T192	0	10	0	0
T193	0	38	0	0
T194	0	15	0	0
T196	0	1	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	240480752	57097	0	0
T20	154232	1503	0	0
T21	341121	3453	0	0
T36	2081	0	0	0
T38	1382	0	0	0
T47	680	0	0	0
T67	2037	0	0	0
T81	1236	0	0	0
T84	0	2	0	0
T119	1759	0	0	0
T122	1497	0	0	0
T187	1009	0	0	0
T188	0	9486	0	0
T189	0	23	0	0
T190	0	18	0	0
T191	0	5	0	0
T192	0	19	0	0
T193	0	50	0	0
T197	0	1	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	240480752	55818	0	0
T20	154232	1550	0	0
T21	341121	3697	0	0
T36	2081	0	0	0
T38	1382	0	0	0
T47	680	0	0	0
T67	2037	0	0	0
T81	1236	0	0	0
T119	1759	0	0	0
T122	1497	0	0	0
T187	1009	0	0	0
T188	0	9302	0	0
T190	0	30	0	0
T192	0	16	0	0
T193	0	92	0	0
T194	0	12	0	0
T196	0	3	0	0
T198	0	56	0	0
T199	0	78	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	240480752	62307	0	0
T20	154232	1763	0	0
T21	341121	4096	0	0
T36	2081	0	0	0
T38	1382	0	0	0
T47	680	0	0	0
T67	2037	0	0	0
T81	1236	0	0	0
T119	1759	0	0	0
T122	1497	0	0	0
T187	1009	0	0	0
T188	0	9514	0	0
T189	0	26	0	0
T200	0	11	0	0
T201	0	10	0	0
T202	0	410	0	0
T203	0	191	0	0
T204	0	47	0	0
T205	0	14	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	240480752	65719	0	0
T20	154232	1702	0	0
T21	341121	4146	0	0
T36	2081	0	0	0
T38	1382	0	0	0
T47	680	0	0	0
T67	2037	0	0	0
T81	1236	0	0	0
T119	1759	0	0	0
T122	1497	0	0	0
T187	1009	0	0	0
T188	0	10627	0	0
T189	0	56	0	0
T190	0	10	0	0
T201	0	8	0	0
T202	0	448	0	0
T203	0	222	0	0
T204	0	42	0	0
T206	0	32	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	240480752	65641	0	0
T20	154232	1745	0	0
T21	341121	4267	0	0
T36	2081	0	0	0
T38	1382	0	0	0
T47	680	0	0	0
T67	2037	0	0	0
T81	1236	0	0	0
T119	1759	0	0	0
T122	1497	0	0	0
T187	1009	0	0	0
T188	0	10674	0	0
T189	0	3	0	0
T190	0	50	0	0
T201	0	9	0	0
T202	0	451	0	0
T203	0	215	0	0
T204	0	50	0	0
T206	0	35	0	0