Unified Coverage Report :: Module :: edn

Module : edn

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	94.44		83.33	100.00			100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.91	99.02	92.46	96.84	94.74	98.62	99.77

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
edn_csr_assert	100.00						100.00
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_edn_core	92.32	99.92	89.78	71.29	94.74	99.29	98.91
u_edn_cov_if	25.00	50.00	0.00
u_reg	98.63	96.98	98.92	100.00		97.26	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Cond Coverage for Module : edn

	Total	Covered	Percent
Conditions	6	5	83.33
Logical	6	5	83.33
Non-Logical	0	0
Event	0	0

 LINE       99
 EXPRESSION (alert[0] || intg_err_alert[0])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T3,T16,T17

 LINE       99
 EXPRESSION (alert[1] || intg_err_alert[1])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T18,T19
1	0	Covered	T1,T4,T5

---

Toggle Coverage for Module : edn

	Total	Covered	Percent
Totals	69	69	100.00
Total Bits	1168	1168	100.00
Total Bits 0->1	584	584	100.00
Total Bits 1->0	584	584	100.00

Ports	69	69	100.00
Port Bits	1168	1168	100.00
Port Bits 0->1	584	584	100.00
Port Bits 1->0	584	584	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T8	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T2,T5,T14	Yes	T2,T5,T14	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T5	Yes	T1,T2,T5	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T5	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i[0].edn_req	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
edn_i[1].edn_req	Yes	Yes	T8,T16,T9	Yes	T8,T16,T9	INPUT
edn_i[2].edn_req	Yes	Yes	T6,T23,T24	Yes	T6,T23,T24	INPUT
edn_i[3].edn_req	Yes	Yes	T17,T25,T26	Yes	T17,T25,T26	INPUT
edn_i[4].edn_req	Yes	Yes	T27,T28,T23	Yes	T27,T28,T23	INPUT
edn_i[5].edn_req	Yes	Yes	T13,T24,T29	Yes	T13,T24,T29	INPUT
edn_i[6].edn_req	Yes	Yes	T30,T29,T31	Yes	T30,T29,T31	INPUT
edn_o[0].edn_bus[31:0]	Yes	Yes	T3,T32,T33	Yes	T2,T3,T32	OUTPUT
edn_o[0].edn_fips	Yes	Yes	T4,T32,T34	Yes	T4,T32,T33	OUTPUT
edn_o[0].edn_ack	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
edn_o[1].edn_bus[31:0]	Yes	Yes	T16,T9,T35	Yes	T8,T16,T9	OUTPUT
edn_o[1].edn_fips	Yes	Yes	T35,T29,T36	Yes	T16,T35,T29	OUTPUT
edn_o[1].edn_ack	Yes	Yes	T8,T16,T9	Yes	T8,T16,T9	OUTPUT
edn_o[2].edn_bus[31:0]	Yes	Yes	T23,T24,T29	Yes	T23,T24,T29	OUTPUT
edn_o[2].edn_fips	Yes	Yes	T23,T29,T37	Yes	T23,T24,T29	OUTPUT
edn_o[2].edn_ack	Yes	Yes	T23,T24,T29	Yes	T23,T24,T29	OUTPUT
edn_o[3].edn_bus[31:0]	Yes	Yes	T17,T25,T26	Yes	T17,T25,T26	OUTPUT
edn_o[3].edn_fips	Yes	Yes	T26,T29,T10	Yes	T26,T23,T29	OUTPUT
edn_o[3].edn_ack	Yes	Yes	T17,T25,T26	Yes	T17,T25,T26	OUTPUT
edn_o[4].edn_bus[31:0]	Yes	Yes	T27,T28,T23	Yes	T27,T28,T23	OUTPUT
edn_o[4].edn_fips	Yes	Yes	T23,T29,T15	Yes	T27,T23,T29	OUTPUT
edn_o[4].edn_ack	Yes	Yes	T27,T28,T23	Yes	T27,T28,T23	OUTPUT
edn_o[5].edn_bus[31:0]	Yes	Yes	T24,T29,T38	Yes	T13,T24,T29	OUTPUT
edn_o[5].edn_fips	Yes	Yes	T24,T29,T39	Yes	T24,T29,T39	OUTPUT
edn_o[5].edn_ack	Yes	Yes	T13,T24,T29	Yes	T13,T24,T29	OUTPUT
edn_o[6].edn_bus[31:0]	Yes	Yes	T29,T10,T40	Yes	T30,T29,T41	OUTPUT
edn_o[6].edn_fips	Yes	Yes	T29,T10,T42	Yes	T30,T29,T10	OUTPUT
edn_o[6].edn_ack	Yes	Yes	T30,T29,T41	Yes	T30,T29,T41	OUTPUT
csrng_cmd_o.genbits_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	Yes	Yes	T2,T3,T8	Yes	T2,T3,T8	OUTPUT
csrng_cmd_o.csrng_req_valid	Yes	Yes	T2,T3,T8	Yes	T2,T3,T8	OUTPUT
csrng_cmd_i.genbits_bus[127:0]	Yes	Yes	T8,T32,T30	Yes	T13,T30,T23	INPUT
csrng_cmd_i.genbits_fips	Yes	Yes	T8,T13,T32	Yes	T8,T9,T13	INPUT
csrng_cmd_i.genbits_valid	Yes	Yes	T2,T3,T8	Yes	T2,T3,T8	INPUT
csrng_cmd_i.csrng_rsp_sts	Yes	Yes	T2,T3,T8	Yes	T2,T3,T8	INPUT
csrng_cmd_i.csrng_rsp_ack	Yes	Yes	T2,T3,T8	Yes	T2,T3,T8	INPUT
csrng_cmd_i.csrng_req_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T3,T16,T17	Yes	T3,T16,T17	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T3,T16,T17	Yes	T3,T16,T17	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T43,T44,T45	Yes	T43,T44,T45	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T4,T46,T34	Yes	T4,T46,T34	OUTPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Module : edn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	43	43	100.00	43	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	43	43	100.00	43	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnownO_A	239997211	239869471	0	0
CsrngAppIfOut_A	239997211	239869471	0	0
FpvSecCmCntAlertCheck_A	239997211	118	0	0
FpvSecCmMainFsmCheck_A	239997211	70	0	0
FpvSecCmRegWeOnehotCheck_A	239997211	70	0	0
IntrEdnCmdReqDoneKnownO_A	239997211	239869471	0	0
TlAReadyKnownO_A	239997211	239869471	0	0
TlDValidKnownO_A	239997211	239869471	0	0
gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A	239997211	70	0	0
gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A	239997211	70	0	0
gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A	239997211	70	0	0
gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A	239997211	70	0	0
gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A	239997211	70	0	0
gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A	239997211	70	0	0
gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A	239997211	70	0	0
gen_edn_if_asserts[0].EdnDataStableDisable_A	239997211	454061	0	0
gen_edn_if_asserts[0].EdnDataStable_A	239997211	6809	0	160
gen_edn_if_asserts[0].EdnEndPointOut_A	239997211	239869471	0	0
gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A	239997211	126743	0	0
gen_edn_if_asserts[1].EdnDataStableDisable_A	239997211	454061	0	0
gen_edn_if_asserts[1].EdnDataStable_A	239997211	573	0	23
gen_edn_if_asserts[1].EdnEndPointOut_A	239997211	239869471	0	0
gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A	239997211	126743	0	0
gen_edn_if_asserts[2].EdnDataStableDisable_A	239997211	454061	0	0
gen_edn_if_asserts[2].EdnDataStable_A	239997211	407	0	17
gen_edn_if_asserts[2].EdnEndPointOut_A	239997211	239869471	0	0
gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A	239997211	126743	0	0
gen_edn_if_asserts[3].EdnDataStableDisable_A	239997211	454061	0	0
gen_edn_if_asserts[3].EdnDataStable_A	239997211	479	0	21
gen_edn_if_asserts[3].EdnEndPointOut_A	239997211	239869471	0	0
gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A	239997211	126743	0	0
gen_edn_if_asserts[4].EdnDataStableDisable_A	239997211	454061	0	0
gen_edn_if_asserts[4].EdnDataStable_A	239997211	522	0	25
gen_edn_if_asserts[4].EdnEndPointOut_A	239997211	239869471	0	0
gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A	239997211	126743	0	0
gen_edn_if_asserts[5].EdnDataStableDisable_A	239997211	454061	0	0
gen_edn_if_asserts[5].EdnDataStable_A	239997211	558	0	26
gen_edn_if_asserts[5].EdnEndPointOut_A	239997211	239869471	0	0
gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A	239997211	126743	0	0
gen_edn_if_asserts[6].EdnDataStableDisable_A	239997211	454061	0	0
gen_edn_if_asserts[6].EdnDataStable_A	239997211	317	0	15
gen_edn_if_asserts[6].EdnEndPointOut_A	239997211	239869471	0	0
gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A	239997211	126743	0	0

AlertTxKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239997211	239869471	0	0
T1	16037	8715	0	0
T2	1040	953	0	0
T3	1538	1455	0	0
T4	1824	1655	0	0
T5	1938	1753	0	0
T8	2635	2555	0	0
T9	1808	1730	0	0
T13	2103	2052	0	0
T14	735	605	0	0
T16	2002	1940	0	0

CsrngAppIfOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239997211	239869471	0	0
T1	16037	8715	0	0
T2	1040	953	0	0
T3	1538	1455	0	0
T4	1824	1655	0	0
T5	1938	1753	0	0
T8	2635	2555	0	0
T9	1808	1730	0	0
T13	2103	2052	0	0
T14	735	605	0	0
T16	2002	1940	0	0

FpvSecCmCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239997211	118	0	0
T1	16037	10	0	0
T2	1040	0	0	0
T3	1538	0	0	0
T4	1824	0	0	0
T5	1938	0	0	0
T8	2635	0	0	0
T9	1808	0	0	0
T13	2103	0	0	0
T14	735	1	0	0
T15	0	1	0	0
T16	2002	0	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0

FpvSecCmMainFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239997211	70	0	0
T1	16037	10	0	0
T2	1040	0	0	0
T3	1538	0	0	0
T4	1824	0	0	0
T5	1938	0	0	0
T8	2635	0	0	0
T9	1808	0	0	0
T13	2103	0	0	0
T14	735	0	0	0
T16	2002	0	0	0
T18	0	20	0	0
T19	0	20	0	0
T54	0	10	0	0
T55	0	10	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239997211	70	0	0
T1	16037	10	0	0
T2	1040	0	0	0
T3	1538	0	0	0
T4	1824	0	0	0
T5	1938	0	0	0
T8	2635	0	0	0
T9	1808	0	0	0
T13	2103	0	0	0
T14	735	0	0	0
T16	2002	0	0	0
T18	0	20	0	0
T19	0	20	0	0
T54	0	10	0	0
T55	0	10	0	0

IntrEdnCmdReqDoneKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239997211	239869471	0	0
T1	16037	8715	0	0
T2	1040	953	0	0
T3	1538	1455	0	0
T4	1824	1655	0	0
T5	1938	1753	0	0
T8	2635	2555	0	0
T9	1808	1730	0	0
T13	2103	2052	0	0
T14	735	605	0	0
T16	2002	1940	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239997211	239869471	0	0
T1	16037	8715	0	0
T2	1040	953	0	0
T3	1538	1455	0	0
T4	1824	1655	0	0
T5	1938	1753	0	0
T8	2635	2555	0	0
T9	1808	1730	0	0
T13	2103	2052	0	0
T14	735	605	0	0
T16	2002	1940	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239997211	239869471	0	0
T1	16037	8715	0	0
T2	1040	953	0	0
T3	1538	1455	0	0
T4	1824	1655	0	0
T5	1938	1753	0	0
T8	2635	2555	0	0
T9	1808	1730	0	0
T13	2103	2052	0	0
T14	735	605	0	0
T16	2002	1940	0	0

gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239997211	70	0	0
T1	16037	10	0	0
T2	1040	0	0	0
T3	1538	0	0	0
T4	1824	0	0	0
T5	1938	0	0	0
T8	2635	0	0	0
T9	1808	0	0	0
T13	2103	0	0	0
T14	735	0	0	0
T16	2002	0	0	0
T18	0	20	0	0
T19	0	20	0	0
T54	0	10	0	0
T55	0	10	0	0

gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239997211	70	0	0
T1	16037	10	0	0
T2	1040	0	0	0
T3	1538	0	0	0
T4	1824	0	0	0
T5	1938	0	0	0
T8	2635	0	0	0
T9	1808	0	0	0
T13	2103	0	0	0
T14	735	0	0	0
T16	2002	0	0	0
T18	0	20	0	0
T19	0	20	0	0
T54	0	10	0	0
T55	0	10	0	0

gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239997211	70	0	0
T1	16037	10	0	0
T2	1040	0	0	0
T3	1538	0	0	0
T4	1824	0	0	0
T5	1938	0	0	0
T8	2635	0	0	0
T9	1808	0	0	0
T13	2103	0	0	0
T14	735	0	0	0
T16	2002	0	0	0
T18	0	20	0	0
T19	0	20	0	0
T54	0	10	0	0
T55	0	10	0	0

gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239997211	70	0	0
T1	16037	10	0	0
T2	1040	0	0	0
T3	1538	0	0	0
T4	1824	0	0	0
T5	1938	0	0	0
T8	2635	0	0	0
T9	1808	0	0	0
T13	2103	0	0	0
T14	735	0	0	0
T16	2002	0	0	0
T18	0	20	0	0
T19	0	20	0	0
T54	0	10	0	0
T55	0	10	0	0

gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239997211	70	0	0
T1	16037	10	0	0
T2	1040	0	0	0
T3	1538	0	0	0
T4	1824	0	0	0
T5	1938	0	0	0
T8	2635	0	0	0
T9	1808	0	0	0
T13	2103	0	0	0
T14	735	0	0	0
T16	2002	0	0	0
T18	0	20	0	0
T19	0	20	0	0
T54	0	10	0	0
T55	0	10	0	0

gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239997211	70	0	0
T1	16037	10	0	0
T2	1040	0	0	0
T3	1538	0	0	0
T4	1824	0	0	0
T5	1938	0	0	0
T8	2635	0	0	0
T9	1808	0	0	0
T13	2103	0	0	0
T14	735	0	0	0
T16	2002	0	0	0
T18	0	20	0	0
T19	0	20	0	0
T54	0	10	0	0
T55	0	10	0	0

gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239997211	70	0	0
T1	16037	10	0	0
T2	1040	0	0	0
T3	1538	0	0	0
T4	1824	0	0	0
T5	1938	0	0	0
T8	2635	0	0	0
T9	1808	0	0	0
T13	2103	0	0	0
T14	735	0	0	0
T16	2002	0	0	0
T18	0	20	0	0
T19	0	20	0	0
T54	0	10	0	0
T55	0	10	0	0

gen_edn_if_asserts[0].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239997211	454061	0	0
T1	16037	7477	0	0
T2	1040	14	0	0
T3	1538	26	0	0
T4	1824	1064	0	0
T5	1938	1154	0	0
T8	2635	1605	0	0
T9	1808	1127	0	0
T13	2103	1209	0	0
T14	735	325	0	0
T16	2002	26	0	0

gen_edn_if_asserts[0].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239997211	6809	0	160
T2	1040	3	0	1
T3	1538	4	0	1
T4	1824	0	0	0
T5	1938	0	0	0
T8	2635	0	0	0
T9	1808	0	0	0
T13	2103	0	0	0
T14	735	0	0	0
T16	2002	0	0	0
T17	1503	0	0	0
T24	0	0	0	1
T32	0	16	0	1
T33	0	3	0	1
T43	0	13	0	0
T44	0	7	0	1
T45	0	6	0	0
T56	0	3	0	1
T57	0	3	0	1
T58	0	3	0	1
T59	0	0	0	1

gen_edn_if_asserts[0].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239997211	239869471	0	0
T1	16037	8715	0	0
T2	1040	953	0	0
T3	1538	1455	0	0
T4	1824	1655	0	0
T5	1938	1753	0	0
T8	2635	2555	0	0
T9	1808	1730	0	0
T13	2103	2052	0	0
T14	735	605	0	0
T16	2002	1940	0	0

gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239997211	126743	0	0
T1	16037	5380	0	0
T2	1040	0	0	0
T3	1538	0	0	0
T4	1824	7	0	0
T5	1938	1072	0	0
T6	0	412	0	0
T7	0	749	0	0
T8	2635	0	0	0
T9	1808	0	0	0
T13	2103	0	0	0
T14	735	421	0	0
T15	0	787	0	0
T16	2002	0	0	0
T26	0	1110	0	0
T34	0	29	0	0
T46	0	640	0	0

gen_edn_if_asserts[1].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239997211	454061	0	0
T1	16037	7477	0	0
T2	1040	14	0	0
T3	1538	26	0	0
T4	1824	1064	0	0
T5	1938	1154	0	0
T8	2635	1605	0	0
T9	1808	1127	0	0
T13	2103	1209	0	0
T14	735	325	0	0
T16	2002	26	0	0

gen_edn_if_asserts[1].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239997211	573	0	23
T4	1824	0	0	0
T5	1938	0	0	0
T8	2635	3	0	0
T9	1808	3	0	0
T10	0	49	0	1
T13	2103	0	0	0
T14	735	0	0	0
T16	2002	4	0	1
T17	1503	0	0	0
T27	2589	0	0	0
T29	0	56	0	1
T32	1376	0	0	0
T35	0	44	0	1
T42	0	0	0	1
T60	0	3	0	1
T61	0	15	0	1
T62	0	3	0	0
T63	0	3	0	0
T64	0	0	0	1
T65	0	0	0	1
T66	0	0	0	1

gen_edn_if_asserts[1].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239997211	239869471	0	0
T1	16037	8715	0	0
T2	1040	953	0	0
T3	1538	1455	0	0
T4	1824	1655	0	0
T5	1938	1753	0	0
T8	2635	2555	0	0
T9	1808	1730	0	0
T13	2103	2052	0	0
T14	735	605	0	0
T16	2002	1940	0	0

gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239997211	126743	0	0
T1	16037	5380	0	0
T2	1040	0	0	0
T3	1538	0	0	0
T4	1824	7	0	0
T5	1938	1072	0	0
T6	0	412	0	0
T7	0	749	0	0
T8	2635	0	0	0
T9	1808	0	0	0
T13	2103	0	0	0
T14	735	421	0	0
T15	0	787	0	0
T16	2002	0	0	0
T26	0	1110	0	0
T34	0	29	0	0
T46	0	640	0	0

gen_edn_if_asserts[2].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239997211	454061	0	0
T1	16037	7477	0	0
T2	1040	14	0	0
T3	1538	26	0	0
T4	1824	1064	0	0
T5	1938	1154	0	0
T8	2635	1605	0	0
T9	1808	1127	0	0
T13	2103	1209	0	0
T14	735	325	0	0
T16	2002	26	0	0

gen_edn_if_asserts[2].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239997211	407	0	17
T7	2674	0	0	0
T10	0	38	0	1
T23	2188	47	0	1
T24	1845	11	0	1
T29	2680	52	0	1
T35	1417	0	0	0
T39	0	54	0	1
T42	0	0	0	1
T44	4896	0	0	0
T45	6058	0	0	0
T58	1108	0	0	0
T59	803	0	0	0
T67	0	4	0	1
T68	0	3	0	1
T69	0	3	0	1
T70	0	3	0	0
T71	0	16	0	1
T72	1320	0	0	0

gen_edn_if_asserts[2].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239997211	239869471	0	0
T1	16037	8715	0	0
T2	1040	953	0	0
T3	1538	1455	0	0
T4	1824	1655	0	0
T5	1938	1753	0	0
T8	2635	2555	0	0
T9	1808	1730	0	0
T13	2103	2052	0	0
T14	735	605	0	0
T16	2002	1940	0	0

gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239997211	126743	0	0
T1	16037	5380	0	0
T2	1040	0	0	0
T3	1538	0	0	0
T4	1824	7	0	0
T5	1938	1072	0	0
T6	0	412	0	0
T7	0	749	0	0
T8	2635	0	0	0
T9	1808	0	0	0
T13	2103	0	0	0
T14	735	421	0	0
T15	0	787	0	0
T16	2002	0	0	0
T26	0	1110	0	0
T34	0	29	0	0
T46	0	640	0	0

gen_edn_if_asserts[3].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239997211	454061	0	0
T1	16037	7477	0	0
T2	1040	14	0	0
T3	1538	26	0	0
T4	1824	1064	0	0
T5	1938	1154	0	0
T8	2635	1605	0	0
T9	1808	1127	0	0
T13	2103	1209	0	0
T14	735	325	0	0
T16	2002	26	0	0

gen_edn_if_asserts[3].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239997211	479	0	21
T6	1102	0	0	0
T10	0	33	0	1
T17	1503	4	0	1
T23	0	17	0	1
T25	1793	4	0	1
T26	1852	0	0	0
T27	2589	0	0	0
T28	2134	0	0	0
T29	0	51	0	1
T32	1376	0	0	0
T33	981	0	0	0
T34	1035	0	0	0
T46	1337	0	0	0
T71	0	0	0	1
T73	0	4	0	1
T74	0	3	0	0
T75	0	3	0	1
T76	0	3	0	0
T77	0	3	0	0
T78	0	0	0	1
T79	0	0	0	1

gen_edn_if_asserts[3].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239997211	239869471	0	0
T1	16037	8715	0	0
T2	1040	953	0	0
T3	1538	1455	0	0
T4	1824	1655	0	0
T5	1938	1753	0	0
T8	2635	2555	0	0
T9	1808	1730	0	0
T13	2103	2052	0	0
T14	735	605	0	0
T16	2002	1940	0	0

gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239997211	126743	0	0
T1	16037	5380	0	0
T2	1040	0	0	0
T3	1538	0	0	0
T4	1824	7	0	0
T5	1938	1072	0	0
T6	0	412	0	0
T7	0	749	0	0
T8	2635	0	0	0
T9	1808	0	0	0
T13	2103	0	0	0
T14	735	421	0	0
T15	0	787	0	0
T16	2002	0	0	0
T26	0	1110	0	0
T34	0	29	0	0
T46	0	640	0	0

gen_edn_if_asserts[4].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239997211	454061	0	0
T1	16037	7477	0	0
T2	1040	14	0	0
T3	1538	26	0	0
T4	1824	1064	0	0
T5	1938	1154	0	0
T8	2635	1605	0	0
T9	1808	1127	0	0
T13	2103	1209	0	0
T14	735	325	0	0
T16	2002	26	0	0

gen_edn_if_asserts[4].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239997211	522	0	25
T6	1102	0	0	0
T10	0	46	0	1
T23	2188	63	0	1
T25	1793	0	0	0
T26	1852	0	0	0
T27	2589	3	0	0
T28	2134	3	0	0
T29	0	40	0	1
T33	981	0	0	0
T34	1035	0	0	0
T44	4896	0	0	0
T46	1337	0	0	0
T80	0	3	0	0
T81	0	3	0	1
T82	0	3	0	1
T83	0	4	0	1
T84	0	3	0	0
T85	0	0	0	1
T86	0	0	0	1
T87	0	0	0	1
T88	0	0	0	1

gen_edn_if_asserts[4].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239997211	239869471	0	0
T1	16037	8715	0	0
T2	1040	953	0	0
T3	1538	1455	0	0
T4	1824	1655	0	0
T5	1938	1753	0	0
T8	2635	2555	0	0
T9	1808	1730	0	0
T13	2103	2052	0	0
T14	735	605	0	0
T16	2002	1940	0	0

gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239997211	126743	0	0
T1	16037	5380	0	0
T2	1040	0	0	0
T3	1538	0	0	0
T4	1824	7	0	0
T5	1938	1072	0	0
T6	0	412	0	0
T7	0	749	0	0
T8	2635	0	0	0
T9	1808	0	0	0
T13	2103	0	0	0
T14	735	421	0	0
T15	0	787	0	0
T16	2002	0	0	0
T26	0	1110	0	0
T34	0	29	0	0
T46	0	640	0	0

gen_edn_if_asserts[5].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239997211	454061	0	0
T1	16037	7477	0	0
T2	1040	14	0	0
T3	1538	26	0	0
T4	1824	1064	0	0
T5	1938	1154	0	0
T8	2635	1605	0	0
T9	1808	1127	0	0
T13	2103	1209	0	0
T14	735	325	0	0
T16	2002	26	0	0

gen_edn_if_asserts[5].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239997211	558	0	26
T6	1102	0	0	0
T10	0	34	0	1
T13	2103	3	0	0
T17	1503	0	0	0
T24	0	31	0	1
T25	1793	0	0	0
T27	2589	0	0	0
T28	2134	0	0	0
T29	0	55	0	1
T32	1376	0	0	0
T33	981	0	0	0
T34	1035	0	0	0
T38	0	3	0	1
T39	0	62	0	1
T41	0	1	0	0
T46	1337	0	0	0
T89	0	3	0	1
T90	0	3	0	0
T91	0	4	0	1
T92	0	0	0	1
T93	0	0	0	1
T94	0	0	0	1

gen_edn_if_asserts[5].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239997211	239869471	0	0
T1	16037	8715	0	0
T2	1040	953	0	0
T3	1538	1455	0	0
T4	1824	1655	0	0
T5	1938	1753	0	0
T8	2635	2555	0	0
T9	1808	1730	0	0
T13	2103	2052	0	0
T14	735	605	0	0
T16	2002	1940	0	0

gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239997211	126743	0	0
T1	16037	5380	0	0
T2	1040	0	0	0
T3	1538	0	0	0
T4	1824	7	0	0
T5	1938	1072	0	0
T6	0	412	0	0
T7	0	749	0	0
T8	2635	0	0	0
T9	1808	0	0	0
T13	2103	0	0	0
T14	735	421	0	0
T15	0	787	0	0
T16	2002	0	0	0
T26	0	1110	0	0
T34	0	29	0	0
T46	0	640	0	0

gen_edn_if_asserts[6].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239997211	454061	0	0
T1	16037	7477	0	0
T2	1040	14	0	0
T3	1538	26	0	0
T4	1824	1064	0	0
T5	1938	1154	0	0
T8	2635	1605	0	0
T9	1808	1127	0	0
T13	2103	1209	0	0
T14	735	325	0	0
T16	2002	26	0	0

gen_edn_if_asserts[6].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239997211	317	0	15
T10	0	55	0	1
T23	2188	0	0	0
T24	1845	0	0	0
T29	0	32	0	1
T30	1669	3	0	0
T35	1417	0	0	0
T40	0	3	0	0
T41	0	3	0	0
T42	0	42	0	1
T43	18589	0	0	0
T44	4896	0	0	0
T45	6058	0	0	0
T56	1307	0	0	0
T57	742	0	0	0
T58	1108	0	0	0
T79	0	0	0	1
T95	0	3	0	1
T96	0	3	0	1
T97	0	3	0	0
T98	0	4	0	0
T99	0	0	0	1
T100	0	0	0	1
T101	0	0	0	1
T102	0	0	0	1

gen_edn_if_asserts[6].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239997211	239869471	0	0
T1	16037	8715	0	0
T2	1040	953	0	0
T3	1538	1455	0	0
T4	1824	1655	0	0
T5	1938	1753	0	0
T8	2635	2555	0	0
T9	1808	1730	0	0
T13	2103	2052	0	0
T14	735	605	0	0
T16	2002	1940	0	0

gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239997211	126743	0	0
T1	16037	5380	0	0
T2	1040	0	0	0
T3	1538	0	0	0
T4	1824	7	0	0
T5	1938	1072	0	0
T6	0	412	0	0
T7	0	749	0	0
T8	2635	0	0	0
T9	1808	0	0	0
T13	2103	0	0	0
T14	735	421	0	0
T15	0	787	0	0
T16	2002	0	0	0
T26	0	1110	0	0
T34	0	29	0	0
T46	0	640	0	0