Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44		83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	193243751	8744054	0	0
boot_gen_cmd_rd_A	193243751	66756	0	0
boot_ins_cmd_rd_A	193243751	74994	0	0
ctrl_rd_A	193243751	65994	0	0
err_code_test_rd_A	193243751	65616	0	0
intr_enable_rd_A	193243751	73892	0	0
max_num_reqs_between_reseeds_rd_A	193243751	75612	0	0
regwen_rd_A	193243751	75341	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	193243751	8744054	0	0
T3	223211	129716	0	0
T4	1865	0	0	0
T14	3059	0	0	0
T16	1760	0	0	0
T18	2477	0	0	0
T19	1185	0	0	0
T20	914	0	0	0
T21	1665	0	0	0
T22	1140	0	0	0
T25	0	85162	0	0
T26	0	179387	0	0
T45	1231	0	0	0
T115	0	155267	0	0
T116	0	111064	0	0
T122	0	255114	0	0
T139	0	232980	0	0
T140	0	119000	0	0
T141	0	47485	0	0
T142	0	245275	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	193243751	66756	0	0
T5	1275	0	0	0
T10	1971	0	0	0
T26	467246	2495	0	0
T28	1133	0	0	0
T37	1700	0	0	0
T38	1293	0	0	0
T58	1013	0	0	0
T76	1193	0	0	0
T116	0	1777	0	0
T141	0	1320	0	0
T143	0	7148	0	0
T144	0	36	0	0
T145	0	53	0	0
T146	0	107	0	0
T147	0	17	0	0
T148	0	1	0	0
T149	0	4	0	0
T150	1860	0	0	0
T151	1454	0	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	193243751	74994	0	0
T5	1275	0	0	0
T10	1971	0	0	0
T26	467246	2677	0	0
T28	1133	0	0	0
T37	1700	0	0	0
T38	1293	0	0	0
T58	1013	0	0	0
T76	1193	0	0	0
T116	0	1852	0	0
T141	0	1535	0	0
T143	0	8287	0	0
T144	0	18	0	0
T145	0	85	0	0
T146	0	78	0	0
T147	0	20	0	0
T149	0	3	0	0
T150	1860	0	0	0
T151	1454	0	0	0
T152	0	34	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	193243751	65994	0	0
T14	3059	0	0	0
T15	18052	0	0	0
T16	1760	0	0	0
T17	1558	0	0	0
T20	914	6	0	0
T21	1665	0	0	0
T22	1140	0	0	0
T26	0	2340	0	0
T27	0	1	0	0
T34	1585	0	0	0
T45	1231	0	0	0
T46	0	2	0	0
T51	1096	0	0	0
T58	0	5	0	0
T116	0	1690	0	0
T141	0	1362	0	0
T143	0	7466	0	0
T144	0	38	0	0
T153	0	5	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	193243751	65616	0	0
T5	1275	0	0	0
T10	1971	0	0	0
T26	467246	2446	0	0
T28	1133	0	0	0
T37	1700	0	0	0
T38	1293	0	0	0
T58	1013	0	0	0
T76	1193	0	0	0
T116	0	1653	0	0
T141	0	1319	0	0
T143	0	6812	0	0
T145	0	12	0	0
T146	0	81	0	0
T147	0	14	0	0
T149	0	7	0	0
T150	1860	0	0	0
T151	1454	0	0	0
T152	0	27	0	0
T154	0	4	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	193243751	73892	0	0
T5	1275	0	0	0
T10	1971	0	0	0
T26	467246	2878	0	0
T28	1133	0	0	0
T37	1700	0	0	0
T38	1293	0	0	0
T58	1013	0	0	0
T76	1193	0	0	0
T116	0	2123	0	0
T141	0	1624	0	0
T143	0	7825	0	0
T150	1860	0	0	0
T151	1454	0	0	0
T154	0	138	0	0
T155	0	30	0	0
T156	0	66	0	0
T157	0	15	0	0
T158	0	47	0	0
T159	0	58	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	193243751	75612	0	0
T5	1275	0	0	0
T10	1971	0	0	0
T26	467246	2915	0	0
T28	1133	0	0	0
T37	1700	0	0	0
T38	1293	0	0	0
T58	1013	0	0	0
T76	1193	0	0	0
T116	0	1928	0	0
T141	0	1543	0	0
T143	0	8103	0	0
T144	0	21	0	0
T145	0	38	0	0
T146	0	88	0	0
T150	1860	0	0	0
T151	1454	0	0	0
T154	0	61	0	0
T160	0	4	0	0
T161	0	5	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	193243751	75341	0	0
T5	1275	0	0	0
T10	1971	0	0	0
T26	467246	2998	0	0
T28	1133	0	0	0
T37	1700	0	0	0
T38	1293	0	0	0
T58	1013	0	0	0
T76	1193	0	0	0
T116	0	1762	0	0
T141	0	1605	0	0
T143	0	8280	0	0
T144	0	32	0	0
T145	0	50	0	0
T150	1860	0	0	0
T151	1454	0	0	0
T154	0	88	0	0
T160	0	4	0	0
T161	0	6	0	0
T162	0	5	0	0