Unified Coverage Report :: Module :: edn

Module : edn

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	94.44		83.33	100.00			100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.00	99.02	92.39	96.79	95.39	98.62	99.77

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
edn_csr_assert	100.00						100.00
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_edn_core	92.33	99.92	89.68	70.79	95.39	99.29	98.91
u_edn_cov_if	25.00	50.00	0.00
u_reg	98.63	96.98	98.92	100.00		97.26	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Cond Coverage for Module : edn

	Total	Covered	Percent
Conditions	6	5	83.33
Logical	6	5	83.33
Non-Logical	0	0
Event	0	0

 LINE       99
 EXPRESSION (alert[0] || intg_err_alert[0])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T2,T16,T17

 LINE       99
 EXPRESSION (alert[1] || intg_err_alert[1])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T15,T23,T24
1	0	Covered	T1,T4,T22

---

Toggle Coverage for Module : edn

	Total	Covered	Percent
Totals	69	69	100.00
Total Bits	1168	1168	100.00
Total Bits 0->1	584	584	100.00
Total Bits 1->0	584	584	100.00

Ports	69	69	100.00
Port Bits	1168	1168	100.00
Port Bits 0->1	584	584	100.00
Port Bits 1->0	584	584	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T3,T18	Yes	T1,T3,T18	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T3,T18	Yes	T1,T3,T18	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T3,T18	Yes	T1,T3,T18	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T3,T25,T26	Yes	T3,T25,T26	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T3,T18	Yes	T1,T3,T18	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i[0].edn_req	Yes	Yes	T3,T18,T19	Yes	T3,T18,T19	INPUT
edn_i[1].edn_req	Yes	Yes	T18,T27,T9	Yes	T18,T27,T9	INPUT
edn_i[2].edn_req	Yes	Yes	T1,T18,T4	Yes	T1,T18,T4	INPUT
edn_i[3].edn_req	Yes	Yes	T18,T9,T28	Yes	T18,T9,T28	INPUT
edn_i[4].edn_req	Yes	Yes	T2,T9,T29	Yes	T2,T9,T29	INPUT
edn_i[5].edn_req	Yes	Yes	T8,T11,T30	Yes	T8,T11,T30	INPUT
edn_i[6].edn_req	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	INPUT
edn_o[0].edn_bus[31:0]	Yes	Yes	T3,T18,T19	Yes	T3,T18,T19	OUTPUT
edn_o[0].edn_fips	Yes	Yes	T3,T18,T25	Yes	T3,T18,T20	OUTPUT
edn_o[0].edn_ack	Yes	Yes	T3,T18,T19	Yes	T3,T18,T19	OUTPUT
edn_o[1].edn_bus[31:0]	Yes	Yes	T18,T27,T9	Yes	T18,T27,T9	OUTPUT
edn_o[1].edn_fips	Yes	Yes	T18,T27,T9	Yes	T18,T27,T9	OUTPUT
edn_o[1].edn_ack	Yes	Yes	T18,T27,T9	Yes	T18,T27,T9	OUTPUT
edn_o[2].edn_bus[31:0]	Yes	Yes	T18,T34,T5	Yes	T18,T34,T10	OUTPUT
edn_o[2].edn_fips	Yes	Yes	T18,T5,T35	Yes	T18,T5,T36	OUTPUT
edn_o[2].edn_ack	Yes	Yes	T1,T18,T34	Yes	T1,T18,T34	OUTPUT
edn_o[3].edn_bus[31:0]	Yes	Yes	T18,T9,T37	Yes	T18,T9,T37	OUTPUT
edn_o[3].edn_fips	Yes	Yes	T18,T9,T37	Yes	T18,T9,T37	OUTPUT
edn_o[3].edn_ack	Yes	Yes	T18,T9,T28	Yes	T18,T9,T28	OUTPUT
edn_o[4].edn_bus[31:0]	Yes	Yes	T2,T9,T29	Yes	T2,T9,T29	OUTPUT
edn_o[4].edn_fips	Yes	Yes	T9,T37,T38	Yes	T9,T37,T38	OUTPUT
edn_o[4].edn_ack	Yes	Yes	T2,T9,T29	Yes	T2,T9,T29	OUTPUT
edn_o[5].edn_bus[31:0]	Yes	Yes	T8,T11,T30	Yes	T8,T11,T30	OUTPUT
edn_o[5].edn_fips	Yes	Yes	T11,T39,T40	Yes	T11,T30,T41	OUTPUT
edn_o[5].edn_ack	Yes	Yes	T8,T11,T30	Yes	T8,T11,T30	OUTPUT
edn_o[6].edn_bus[31:0]	Yes	Yes	T31,T42,T43	Yes	T31,T33,T42	OUTPUT
edn_o[6].edn_fips	Yes	Yes	T32,T43,T44	Yes	T31,T32,T33	OUTPUT
edn_o[6].edn_ack	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
csrng_cmd_o.genbits_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_i.genbits_bus[127:0]	Yes	Yes	T3,T18,T8	Yes	T3,T18,T25	INPUT
csrng_cmd_i.genbits_fips	Yes	Yes	T3,T18,T25	Yes	T3,T18,T8	INPUT
csrng_cmd_i.genbits_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_rsp_sts	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_rsp_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_req_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T2,T16,T45	Yes	T2,T16,T45	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T1,T4,T22	Yes	T1,T4,T22	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T2,T16,T45	Yes	T2,T16,T45	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T1,T4,T22	Yes	T1,T4,T22	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T3,T25,T26	Yes	T3,T25,T26	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T1,T3,T22	Yes	T1,T3,T22	OUTPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Module : edn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	43	43	100.00	43	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	43	43	100.00	43	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnownO_A	192773565	192655048	0	0
CsrngAppIfOut_A	192773565	192655048	0	0
FpvSecCmCntAlertCheck_A	192773565	104	0	0
FpvSecCmMainFsmCheck_A	192773565	60	0	0
FpvSecCmRegWeOnehotCheck_A	192773565	60	0	0
IntrEdnCmdReqDoneKnownO_A	192773565	192655048	0	0
TlAReadyKnownO_A	192773565	192655048	0	0
TlDValidKnownO_A	192773565	192655048	0	0
gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A	192773565	60	0	0
gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A	192773565	60	0	0
gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A	192773565	60	0	0
gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A	192773565	60	0	0
gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A	192773565	60	0	0
gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A	192773565	60	0	0
gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A	192773565	60	0	0
gen_edn_if_asserts[0].EdnDataStableDisable_A	192773565	479509	0	0
gen_edn_if_asserts[0].EdnDataStable_A	192773565	6263	0	151
gen_edn_if_asserts[0].EdnEndPointOut_A	192773565	192655048	0	0
gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A	192773565	125096	0	0
gen_edn_if_asserts[1].EdnDataStableDisable_A	192773565	479509	0	0
gen_edn_if_asserts[1].EdnDataStable_A	192773565	573	0	28
gen_edn_if_asserts[1].EdnEndPointOut_A	192773565	192655048	0	0
gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A	192773565	125096	0	0
gen_edn_if_asserts[2].EdnDataStableDisable_A	192773565	479509	0	0
gen_edn_if_asserts[2].EdnDataStable_A	192773565	584	0	25
gen_edn_if_asserts[2].EdnEndPointOut_A	192773565	192655048	0	0
gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A	192773565	125096	0	0
gen_edn_if_asserts[3].EdnDataStableDisable_A	192773565	479509	0	0
gen_edn_if_asserts[3].EdnDataStable_A	192773565	574	0	25
gen_edn_if_asserts[3].EdnEndPointOut_A	192773565	192655048	0	0
gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A	192773565	125096	0	0
gen_edn_if_asserts[4].EdnDataStableDisable_A	192773565	479509	0	0
gen_edn_if_asserts[4].EdnDataStable_A	192773565	646	0	30
gen_edn_if_asserts[4].EdnEndPointOut_A	192773565	192655048	0	0
gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A	192773565	125096	0	0
gen_edn_if_asserts[5].EdnDataStableDisable_A	192773565	479509	0	0
gen_edn_if_asserts[5].EdnDataStable_A	192773565	502	0	20
gen_edn_if_asserts[5].EdnEndPointOut_A	192773565	192655048	0	0
gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A	192773565	125096	0	0
gen_edn_if_asserts[6].EdnDataStableDisable_A	192773565	479509	0	0
gen_edn_if_asserts[6].EdnDataStable_A	192773565	356	0	16
gen_edn_if_asserts[6].EdnEndPointOut_A	192773565	192655048	0	0
gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A	192773565	125096	0	0

AlertTxKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	192773565	192655048	0	0
T1	1950	1784	0	0
T2	1739	1661	0	0
T3	223211	223199	0	0
T4	1865	1690	0	0
T16	1760	1699	0	0
T18	2477	2384	0	0
T19	1185	1108	0	0
T20	914	864	0	0
T21	1665	1611	0	0
T22	1140	976	0	0

CsrngAppIfOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	192773565	192655048	0	0
T1	1950	1784	0	0
T2	1739	1661	0	0
T3	223211	223199	0	0
T4	1865	1690	0	0
T16	1760	1699	0	0
T18	2477	2384	0	0
T19	1185	1108	0	0
T20	914	864	0	0
T21	1665	1611	0	0
T22	1140	976	0	0

FpvSecCmCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	192773565	104	0	0
T4	1865	1	0	0
T6	0	1	0	0
T7	0	1	0	0
T14	3059	1	0	0
T15	18052	10	0	0
T16	1760	0	0	0
T17	1558	0	0	0
T20	914	0	0	0
T21	1665	0	0	0
T22	1140	0	0	0
T45	1231	0	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	1096	0	0	0

FpvSecCmMainFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	192773565	60	0	0
T8	2226	0	0	0
T15	18052	10	0	0
T23	25478	10	0	0
T24	0	10	0	0
T25	146641	0	0	0
T34	1585	0	0	0
T51	1096	0	0	0
T52	0	10	0	0
T53	0	20	0	0
T54	1448	0	0	0
T55	1165	0	0	0
T56	1000	0	0	0
T57	1396	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	192773565	60	0	0
T8	2226	0	0	0
T15	18052	10	0	0
T23	25478	10	0	0
T24	0	10	0	0
T25	146641	0	0	0
T34	1585	0	0	0
T51	1096	0	0	0
T52	0	10	0	0
T53	0	20	0	0
T54	1448	0	0	0
T55	1165	0	0	0
T56	1000	0	0	0
T57	1396	0	0	0

IntrEdnCmdReqDoneKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	192773565	192655048	0	0
T1	1950	1784	0	0
T2	1739	1661	0	0
T3	223211	223199	0	0
T4	1865	1690	0	0
T16	1760	1699	0	0
T18	2477	2384	0	0
T19	1185	1108	0	0
T20	914	864	0	0
T21	1665	1611	0	0
T22	1140	976	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	192773565	192655048	0	0
T1	1950	1784	0	0
T2	1739	1661	0	0
T3	223211	223199	0	0
T4	1865	1690	0	0
T16	1760	1699	0	0
T18	2477	2384	0	0
T19	1185	1108	0	0
T20	914	864	0	0
T21	1665	1611	0	0
T22	1140	976	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	192773565	192655048	0	0
T1	1950	1784	0	0
T2	1739	1661	0	0
T3	223211	223199	0	0
T4	1865	1690	0	0
T16	1760	1699	0	0
T18	2477	2384	0	0
T19	1185	1108	0	0
T20	914	864	0	0
T21	1665	1611	0	0
T22	1140	976	0	0

gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	192773565	60	0	0
T8	2226	0	0	0
T15	18052	10	0	0
T23	25478	10	0	0
T24	0	10	0	0
T25	146641	0	0	0
T34	1585	0	0	0
T51	1096	0	0	0
T52	0	10	0	0
T53	0	20	0	0
T54	1448	0	0	0
T55	1165	0	0	0
T56	1000	0	0	0
T57	1396	0	0	0

gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	192773565	60	0	0
T8	2226	0	0	0
T15	18052	10	0	0
T23	25478	10	0	0
T24	0	10	0	0
T25	146641	0	0	0
T34	1585	0	0	0
T51	1096	0	0	0
T52	0	10	0	0
T53	0	20	0	0
T54	1448	0	0	0
T55	1165	0	0	0
T56	1000	0	0	0
T57	1396	0	0	0

gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	192773565	60	0	0
T8	2226	0	0	0
T15	18052	10	0	0
T23	25478	10	0	0
T24	0	10	0	0
T25	146641	0	0	0
T34	1585	0	0	0
T51	1096	0	0	0
T52	0	10	0	0
T53	0	20	0	0
T54	1448	0	0	0
T55	1165	0	0	0
T56	1000	0	0	0
T57	1396	0	0	0

gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	192773565	60	0	0
T8	2226	0	0	0
T15	18052	10	0	0
T23	25478	10	0	0
T24	0	10	0	0
T25	146641	0	0	0
T34	1585	0	0	0
T51	1096	0	0	0
T52	0	10	0	0
T53	0	20	0	0
T54	1448	0	0	0
T55	1165	0	0	0
T56	1000	0	0	0
T57	1396	0	0	0

gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	192773565	60	0	0
T8	2226	0	0	0
T15	18052	10	0	0
T23	25478	10	0	0
T24	0	10	0	0
T25	146641	0	0	0
T34	1585	0	0	0
T51	1096	0	0	0
T52	0	10	0	0
T53	0	20	0	0
T54	1448	0	0	0
T55	1165	0	0	0
T56	1000	0	0	0
T57	1396	0	0	0

gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	192773565	60	0	0
T8	2226	0	0	0
T15	18052	10	0	0
T23	25478	10	0	0
T24	0	10	0	0
T25	146641	0	0	0
T34	1585	0	0	0
T51	1096	0	0	0
T52	0	10	0	0
T53	0	20	0	0
T54	1448	0	0	0
T55	1165	0	0	0
T56	1000	0	0	0
T57	1396	0	0	0

gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	192773565	60	0	0
T8	2226	0	0	0
T15	18052	10	0	0
T23	25478	10	0	0
T24	0	10	0	0
T25	146641	0	0	0
T34	1585	0	0	0
T51	1096	0	0	0
T52	0	10	0	0
T53	0	20	0	0
T54	1448	0	0	0
T55	1165	0	0	0
T56	1000	0	0	0
T57	1396	0	0	0

gen_edn_if_asserts[0].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	192773565	479509	0	0
T1	1950	1032	0	0
T2	1739	17	0	0
T3	223211	783	0	0
T4	1865	1060	0	0
T16	1760	178	0	0
T18	2477	59	0	0
T19	1185	14	0	0
T20	914	23	0	0
T21	1665	30	0	0
T22	1140	525	0	0

gen_edn_if_asserts[0].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	192773565	6263	0	151
T3	223211	59	0	0
T4	1865	0	0	0
T9	0	0	0	1
T14	3059	0	0	0
T16	1760	4	0	1
T17	0	4	0	1
T18	2477	61	0	1
T19	1185	3	0	1
T20	914	3	0	1
T21	1665	3	0	1
T22	1140	0	0	0
T25	0	44	0	0
T45	1231	0	0	0
T54	0	4	0	1
T55	0	3	0	1
T58	0	0	0	1

gen_edn_if_asserts[0].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	192773565	192655048	0	0
T1	1950	1784	0	0
T2	1739	1661	0	0
T3	223211	223199	0	0
T4	1865	1690	0	0
T16	1760	1699	0	0
T18	2477	2384	0	0
T19	1185	1108	0	0
T20	914	864	0	0
T21	1665	1611	0	0
T22	1140	976	0	0

gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	192773565	125096	0	0
T1	1950	1110	0	0
T2	1739	0	0	0
T3	223211	0	0	0
T4	1865	1129	0	0
T5	0	602	0	0
T14	0	1172	0	0
T15	0	7061	0	0
T16	1760	0	0	0
T18	2477	0	0	0
T19	1185	0	0	0
T20	914	0	0	0
T21	1665	0	0	0
T22	1140	600	0	0
T27	0	1104	0	0
T28	0	18	0	0
T59	0	285	0	0
T60	0	1134	0	0

gen_edn_if_asserts[1].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	192773565	479509	0	0
T1	1950	1032	0	0
T2	1739	17	0	0
T3	223211	783	0	0
T4	1865	1060	0	0
T16	1760	178	0	0
T18	2477	59	0	0
T19	1185	14	0	0
T20	914	23	0	0
T21	1665	30	0	0
T22	1140	525	0	0

gen_edn_if_asserts[1].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	192773565	573	0	28
T4	1865	0	0	0
T9	0	49	0	1
T14	3059	0	0	0
T16	1760	0	0	0
T17	1558	0	0	0
T18	2477	28	0	1
T19	1185	0	0	0
T20	914	0	0	0
T21	1665	0	0	0
T22	1140	0	0	0
T37	0	27	0	1
T40	0	10	0	1
T43	0	0	0	1
T44	0	0	0	1
T45	1231	0	0	0
T61	0	3	0	0
T62	0	3	0	1
T63	0	4	0	1
T64	0	4	0	0
T65	0	28	0	1
T66	0	3	0	0
T67	0	0	0	1

gen_edn_if_asserts[1].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	192773565	192655048	0	0
T1	1950	1784	0	0
T2	1739	1661	0	0
T3	223211	223199	0	0
T4	1865	1690	0	0
T16	1760	1699	0	0
T18	2477	2384	0	0
T19	1185	1108	0	0
T20	914	864	0	0
T21	1665	1611	0	0
T22	1140	976	0	0

gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	192773565	125096	0	0
T1	1950	1110	0	0
T2	1739	0	0	0
T3	223211	0	0	0
T4	1865	1129	0	0
T5	0	602	0	0
T14	0	1172	0	0
T15	0	7061	0	0
T16	1760	0	0	0
T18	2477	0	0	0
T19	1185	0	0	0
T20	914	0	0	0
T21	1665	0	0	0
T22	1140	600	0	0
T27	0	1104	0	0
T28	0	18	0	0
T59	0	285	0	0
T60	0	1134	0	0

gen_edn_if_asserts[2].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	192773565	479509	0	0
T1	1950	1032	0	0
T2	1739	17	0	0
T3	223211	783	0	0
T4	1865	1060	0	0
T16	1760	178	0	0
T18	2477	59	0	0
T19	1185	14	0	0
T20	914	23	0	0
T21	1665	30	0	0
T22	1140	525	0	0

gen_edn_if_asserts[2].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	192773565	584	0	25
T4	1865	0	0	0
T10	0	3	0	0
T12	0	0	0	1
T14	3059	0	0	0
T16	1760	0	0	0
T17	1558	0	0	0
T18	2477	31	0	1
T19	1185	0	0	0
T20	914	0	0	0
T21	1665	0	0	0
T22	1140	0	0	0
T34	0	4	0	1
T35	0	3	0	0
T36	0	3	0	0
T43	0	38	0	1
T44	0	37	0	1
T45	1231	0	0	0
T68	0	4	0	1
T69	0	3	0	1
T70	0	61	0	1
T71	0	0	0	1
T72	0	0	0	1

gen_edn_if_asserts[2].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	192773565	192655048	0	0
T1	1950	1784	0	0
T2	1739	1661	0	0
T3	223211	223199	0	0
T4	1865	1690	0	0
T16	1760	1699	0	0
T18	2477	2384	0	0
T19	1185	1108	0	0
T20	914	864	0	0
T21	1665	1611	0	0
T22	1140	976	0	0

gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	192773565	125096	0	0
T1	1950	1110	0	0
T2	1739	0	0	0
T3	223211	0	0	0
T4	1865	1129	0	0
T5	0	602	0	0
T14	0	1172	0	0
T15	0	7061	0	0
T16	1760	0	0	0
T18	2477	0	0	0
T19	1185	0	0	0
T20	914	0	0	0
T21	1665	0	0	0
T22	1140	600	0	0
T27	0	1104	0	0
T28	0	18	0	0
T59	0	285	0	0
T60	0	1134	0	0

gen_edn_if_asserts[3].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	192773565	479509	0	0
T1	1950	1032	0	0
T2	1739	17	0	0
T3	223211	783	0	0
T4	1865	1060	0	0
T16	1760	178	0	0
T18	2477	59	0	0
T19	1185	14	0	0
T20	914	23	0	0
T21	1665	30	0	0
T22	1140	525	0	0

gen_edn_if_asserts[3].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	192773565	574	0	25
T4	1865	0	0	0
T9	0	43	0	1
T12	0	39	0	1
T14	3059	0	0	0
T16	1760	0	0	0
T17	1558	0	0	0
T18	2477	61	0	1
T19	1185	0	0	0
T20	914	0	0	0
T21	1665	0	0	0
T22	1140	0	0	0
T37	0	55	0	1
T40	0	41	0	1
T44	0	16	0	1
T45	1231	0	0	0
T65	0	22	0	1
T72	0	13	0	1
T73	0	3	0	0
T74	0	3	0	1
T75	0	0	0	1

gen_edn_if_asserts[3].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	192773565	192655048	0	0
T1	1950	1784	0	0
T2	1739	1661	0	0
T3	223211	223199	0	0
T4	1865	1690	0	0
T16	1760	1699	0	0
T18	2477	2384	0	0
T19	1185	1108	0	0
T20	914	864	0	0
T21	1665	1611	0	0
T22	1140	976	0	0

gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	192773565	125096	0	0
T1	1950	1110	0	0
T2	1739	0	0	0
T3	223211	0	0	0
T4	1865	1129	0	0
T5	0	602	0	0
T14	0	1172	0	0
T15	0	7061	0	0
T16	1760	0	0	0
T18	2477	0	0	0
T19	1185	0	0	0
T20	914	0	0	0
T21	1665	0	0	0
T22	1140	600	0	0
T27	0	1104	0	0
T28	0	18	0	0
T59	0	285	0	0
T60	0	1134	0	0

gen_edn_if_asserts[4].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	192773565	479509	0	0
T1	1950	1032	0	0
T2	1739	17	0	0
T3	223211	783	0	0
T4	1865	1060	0	0
T16	1760	178	0	0
T18	2477	59	0	0
T19	1185	14	0	0
T20	914	23	0	0
T21	1665	30	0	0
T22	1140	525	0	0

gen_edn_if_asserts[4].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	192773565	646	0	30
T2	1739	4	0	1
T3	223211	0	0	0
T4	1865	0	0	0
T9	0	51	0	1
T16	1760	0	0	0
T18	2477	0	0	0
T19	1185	0	0	0
T20	914	0	0	0
T21	1665	0	0	0
T22	1140	0	0	0
T29	0	4	0	1
T37	0	39	0	1
T38	0	33	0	1
T40	0	35	0	1
T43	0	0	0	1
T45	1231	0	0	0
T76	0	3	0	0
T77	0	4	0	1
T78	0	3	0	0
T79	0	3	0	1
T80	0	0	0	1

gen_edn_if_asserts[4].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	192773565	192655048	0	0
T1	1950	1784	0	0
T2	1739	1661	0	0
T3	223211	223199	0	0
T4	1865	1690	0	0
T16	1760	1699	0	0
T18	2477	2384	0	0
T19	1185	1108	0	0
T20	914	864	0	0
T21	1665	1611	0	0
T22	1140	976	0	0

gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	192773565	125096	0	0
T1	1950	1110	0	0
T2	1739	0	0	0
T3	223211	0	0	0
T4	1865	1129	0	0
T5	0	602	0	0
T14	0	1172	0	0
T15	0	7061	0	0
T16	1760	0	0	0
T18	2477	0	0	0
T19	1185	0	0	0
T20	914	0	0	0
T21	1665	0	0	0
T22	1140	600	0	0
T27	0	1104	0	0
T28	0	18	0	0
T59	0	285	0	0
T60	0	1134	0	0

gen_edn_if_asserts[5].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	192773565	479509	0	0
T1	1950	1032	0	0
T2	1739	17	0	0
T3	223211	783	0	0
T4	1865	1060	0	0
T16	1760	178	0	0
T18	2477	59	0	0
T19	1185	14	0	0
T20	914	23	0	0
T21	1665	30	0	0
T22	1140	525	0	0

gen_edn_if_asserts[5].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	192773565	502	0	20
T6	2294	0	0	0
T8	2226	3	0	0
T11	2678	52	0	1
T25	146641	0	0	0
T30	0	3	0	0
T39	0	3	0	1
T40	0	58	0	1
T41	0	3	0	0
T44	0	0	0	1
T55	1165	0	0	0
T57	0	0	0	1
T65	0	41	0	1
T72	0	0	0	1
T81	0	3	0	0
T82	0	3	0	0
T83	0	3	0	0
T84	745	0	0	0
T85	1709	0	0	0
T86	1799	0	0	0
T87	1105	0	0	0
T88	10824	0	0	0
T89	0	0	0	1
T90	0	0	0	1
T91	0	0	0	1

gen_edn_if_asserts[5].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	192773565	192655048	0	0
T1	1950	1784	0	0
T2	1739	1661	0	0
T3	223211	223199	0	0
T4	1865	1690	0	0
T16	1760	1699	0	0
T18	2477	2384	0	0
T19	1185	1108	0	0
T20	914	864	0	0
T21	1665	1611	0	0
T22	1140	976	0	0

gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	192773565	125096	0	0
T1	1950	1110	0	0
T2	1739	0	0	0
T3	223211	0	0	0
T4	1865	1129	0	0
T5	0	602	0	0
T14	0	1172	0	0
T15	0	7061	0	0
T16	1760	0	0	0
T18	2477	0	0	0
T19	1185	0	0	0
T20	914	0	0	0
T21	1665	0	0	0
T22	1140	600	0	0
T27	0	1104	0	0
T28	0	18	0	0
T59	0	285	0	0
T60	0	1134	0	0

gen_edn_if_asserts[6].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	192773565	479509	0	0
T1	1950	1032	0	0
T2	1739	17	0	0
T3	223211	783	0	0
T4	1865	1060	0	0
T16	1760	178	0	0
T18	2477	59	0	0
T19	1185	14	0	0
T20	914	23	0	0
T21	1665	30	0	0
T22	1140	525	0	0

gen_edn_if_asserts[6].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	192773565	356	0	16
T31	1686	3	0	0
T33	1389	3	0	1
T42	0	3	0	0
T43	0	63	0	1
T44	0	38	0	1
T64	2120	0	0	0
T65	2263	0	0	0
T69	849	0	0	0
T79	863	0	0	0
T83	1345	0	0	0
T91	0	48	0	1
T92	0	3	0	0
T93	0	3	0	0
T94	0	44	0	1
T95	0	3	0	1
T96	1206	0	0	0
T97	1551	0	0	0
T98	1410	0	0	0
T99	0	0	0	1
T100	0	0	0	1
T101	0	0	0	1
T102	0	0	0	1

gen_edn_if_asserts[6].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	192773565	192655048	0	0
T1	1950	1784	0	0
T2	1739	1661	0	0
T3	223211	223199	0	0
T4	1865	1690	0	0
T16	1760	1699	0	0
T18	2477	2384	0	0
T19	1185	1108	0	0
T20	914	864	0	0
T21	1665	1611	0	0
T22	1140	976	0	0

gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	192773565	125096	0	0
T1	1950	1110	0	0
T2	1739	0	0	0
T3	223211	0	0	0
T4	1865	1129	0	0
T5	0	602	0	0
T14	0	1172	0	0
T15	0	7061	0	0
T16	1760	0	0	0
T18	2477	0	0	0
T19	1185	0	0	0
T20	914	0	0	0
T21	1665	0	0	0
T22	1140	600	0	0
T27	0	1104	0	0
T28	0	18	0	0
T59	0	285	0	0
T60	0	1134	0	0