Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44		83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	238637208	11081398	0	0
boot_gen_cmd_rd_A	238637208	68811	0	0
boot_ins_cmd_rd_A	238637208	79365	0	0
ctrl_rd_A	238637208	70389	0	0
err_code_test_rd_A	238637208	69165	0	0
intr_enable_rd_A	238637208	76395	0	0
max_num_reqs_between_reseeds_rd_A	238637208	81101	0	0
regwen_rd_A	238637208	80511	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238637208	11081398	0	0
T2	220160	128112	0	0
T3	762	0	0	0
T4	2270	0	0	0
T6	1699	0	0	0
T16	1392	0	0	0
T17	636233	269000	0	0
T18	988	0	0	0
T19	1023	0	0	0
T20	111164	638711	0	0
T21	13513	0	0	0
T53	0	124333	0	0
T77	0	230868	0	0
T85	0	104177	0	0
T92	0	82974	0	0
T139	0	86673	0	0
T140	0	68934	0	0
T141	0	298266	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238637208	68811	0	0
T7	2346	0	0	0
T13	1136	0	0	0
T43	979	0	0	0
T48	774	0	0	0
T53	341629	3513	0	0
T139	249876	2409	0	0
T142	2494	44	0	0
T143	3450	43	0	0
T144	2230	6	0	0
T145	0	6	0	0
T146	0	7	0	0
T147	0	21	0	0
T148	0	6	0	0
T149	0	10	0	0
T150	8042	0	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238637208	79365	0	0
T7	2346	0	0	0
T13	1136	0	0	0
T43	979	0	0	0
T48	774	0	0	0
T53	341629	4016	0	0
T139	249876	2811	0	0
T142	2494	32	0	0
T143	3450	43	0	0
T144	2230	11	0	0
T145	0	11	0	0
T146	0	2	0	0
T147	0	26	0	0
T151	4475	6	0	0
T152	0	23	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238637208	70389	0	0
T7	2346	0	0	0
T13	1136	0	0	0
T43	979	0	0	0
T48	774	0	0	0
T53	341629	3642	0	0
T64	0	7	0	0
T102	1317	0	0	0
T139	249876	2393	0	0
T142	0	46	0	0
T143	0	48	0	0
T144	0	10	0	0
T145	0	4	0	0
T146	0	8	0	0
T147	0	23	0	0
T153	19415	2	0	0
T154	1097	0	0	0
T155	974	0	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238637208	69165	0	0
T7	2346	0	0	0
T13	1136	0	0	0
T43	979	0	0	0
T48	774	0	0	0
T53	341629	3739	0	0
T139	249876	2575	0	0
T142	2494	41	0	0
T143	3450	31	0	0
T144	2230	18	0	0
T145	0	22	0	0
T146	0	7	0	0
T147	0	27	0	0
T148	0	4	0	0
T149	0	6	0	0
T150	8042	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238637208	76395	0	0
T7	2346	0	0	0
T13	1136	0	0	0
T43	979	0	0	0
T48	774	0	0	0
T53	341629	3917	0	0
T139	249876	2615	0	0
T142	0	53	0	0
T143	0	27	0	0
T151	0	60	0	0
T153	0	140	0	0
T156	12387	29	0	0
T157	0	90	0	0
T158	0	34	0	0
T159	0	7	0	0
T160	1755	0	0	0
T161	1899	0	0	0
T162	966	0	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238637208	81101	0	0
T7	2346	0	0	0
T13	1136	0	0	0
T43	979	0	0	0
T48	774	0	0	0
T53	341629	4189	0	0
T139	249876	2888	0	0
T142	2494	37	0	0
T143	3450	38	0	0
T144	0	11	0	0
T145	0	6	0	0
T146	0	7	0	0
T151	4475	42	0	0
T158	4448	51	0	0
T163	0	229	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238637208	80511	0	0
T7	2346	0	0	0
T13	1136	0	0	0
T43	979	0	0	0
T48	774	0	0	0
T53	341629	3958	0	0
T139	249876	2976	0	0
T142	2494	15	0	0
T143	3450	50	0	0
T144	0	13	0	0
T145	0	8	0	0
T146	0	4	0	0
T151	4475	41	0	0
T158	4448	26	0	0
T163	0	217	0	0