Unified Coverage Report :: Module :: edn

Module : edn

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	94.44		83.33	100.00			100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.76	99.02	92.26	96.79	94.08	98.62	99.77

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
edn_csr_assert	100.00						100.00
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_edn_core	92.08	99.92	89.48	70.79	94.08	99.29	98.91
u_edn_cov_if	25.00	50.00	0.00
u_reg	98.63	96.98	98.92	100.00		97.26	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Cond Coverage for Module : edn

	Total	Covered	Percent
Conditions	6	5	83.33
Logical	6	5	83.33
Non-Logical	0	0
Event	0	0

 LINE       99
 EXPRESSION (alert[0] || intg_err_alert[0])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T13,T14,T15

 LINE       99
 EXPRESSION (alert[1] || intg_err_alert[1])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T22,T23,T24
1	0	Covered	T1,T3,T4

---

Toggle Coverage for Module : edn

	Total	Covered	Percent
Totals	69	69	100.00
Total Bits	1168	1168	100.00
Total Bits 0->1	584	584	100.00
Total Bits 1->0	584	584	100.00

Ports	69	69	100.00
Port Bits	1168	1168	100.00
Port Bits 0->1	584	584	100.00
Port Bits 1->0	584	584	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T17	Yes	T1,T2,T17	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T17	Yes	T1,T2,T17	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T16	Yes	T1,T2,T16	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T2,T17,T20	Yes	T2,T17,T20	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T16	Yes	T1,T2,T16	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i[0].edn_req	Yes	Yes	T2,T17,T19	Yes	T2,T17,T19	INPUT
edn_i[1].edn_req	Yes	Yes	T1,T3,T5	Yes	T1,T3,T5	INPUT
edn_i[2].edn_req	Yes	Yes	T25,T26,T14	Yes	T25,T26,T14	INPUT
edn_i[3].edn_req	Yes	Yes	T6,T27,T28	Yes	T6,T27,T28	INPUT
edn_i[4].edn_req	Yes	Yes	T29,T9,T30	Yes	T29,T9,T30	INPUT
edn_i[5].edn_req	Yes	Yes	T7,T31,T32	Yes	T7,T31,T32	INPUT
edn_i[6].edn_req	Yes	Yes	T6,T10,T33	Yes	T6,T10,T33	INPUT
edn_o[0].edn_bus[31:0]	Yes	Yes	T2,T17,T20	Yes	T2,T17,T19	OUTPUT
edn_o[0].edn_fips	Yes	Yes	T2,T17,T20	Yes	T2,T17,T20	OUTPUT
edn_o[0].edn_ack	Yes	Yes	T2,T17,T19	Yes	T2,T17,T19	OUTPUT
edn_o[1].edn_bus[31:0]	Yes	Yes	T1,T34,T35	Yes	T1,T34,T35	OUTPUT
edn_o[1].edn_fips	Yes	Yes	T1,T30,T36	Yes	T1,T34,T37	OUTPUT
edn_o[1].edn_ack	Yes	Yes	T1,T5,T34	Yes	T1,T5,T34	OUTPUT
edn_o[2].edn_bus[31:0]	Yes	Yes	T25,T26,T9	Yes	T25,T26,T9	OUTPUT
edn_o[2].edn_fips	Yes	Yes	T30,T38,T39	Yes	T26,T14,T9	OUTPUT
edn_o[2].edn_ack	Yes	Yes	T25,T26,T14	Yes	T25,T26,T14	OUTPUT
edn_o[3].edn_bus[31:0]	Yes	Yes	T27,T28,T31	Yes	T27,T28,T31	OUTPUT
edn_o[3].edn_fips	Yes	Yes	T30,T40,T41	Yes	T30,T40,T38	OUTPUT
edn_o[3].edn_ack	Yes	Yes	T6,T27,T28	Yes	T6,T27,T28	OUTPUT
edn_o[4].edn_bus[31:0]	Yes	Yes	T29,T9,T30	Yes	T29,T9,T30	OUTPUT
edn_o[4].edn_fips	Yes	Yes	T30,T40,T36	Yes	T29,T9,T30	OUTPUT
edn_o[4].edn_ack	Yes	Yes	T29,T9,T30	Yes	T29,T9,T30	OUTPUT
edn_o[5].edn_bus[31:0]	Yes	Yes	T7,T31,T30	Yes	T7,T31,T30	OUTPUT
edn_o[5].edn_fips	Yes	Yes	T7,T30,T42	Yes	T7,T32,T30	OUTPUT
edn_o[5].edn_ack	Yes	Yes	T7,T31,T32	Yes	T7,T31,T32	OUTPUT
edn_o[6].edn_bus[31:0]	Yes	Yes	T10,T13,T37	Yes	T6,T10,T33	OUTPUT
edn_o[6].edn_fips	Yes	Yes	T36,T38,T39	Yes	T10,T13,T43	OUTPUT
edn_o[6].edn_ack	Yes	Yes	T6,T10,T33	Yes	T6,T10,T33	OUTPUT
csrng_cmd_o.genbits_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_i.genbits_bus[127:0]	Yes	Yes	T2,T17,T20	Yes	T2,T17,T20	INPUT
csrng_cmd_i.genbits_fips	Yes	Yes	T2,T17,T20	Yes	T2,T17,T20	INPUT
csrng_cmd_i.genbits_valid	Yes	Yes	T1,T2,T17	Yes	T1,T2,T17	INPUT
csrng_cmd_i.csrng_rsp_sts	Yes	Yes	T1,T2,T17	Yes	T1,T2,T17	INPUT
csrng_cmd_i.csrng_rsp_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_req_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T16,T18,T13	Yes	T16,T18,T13	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T1,T3,T16	Yes	T1,T3,T16	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T16,T18,T13	Yes	T16,T18,T13	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T1,T3,T16	Yes	T1,T3,T16	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T2,T17,T20	Yes	T2,T17,T20	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T1,T2,T17	Yes	T1,T2,T17	OUTPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Module : edn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	43	43	100.00	43	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	43	43	100.00	43	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnownO_A	238132407	237997184	0	0
CsrngAppIfOut_A	238132407	237997184	0	0
FpvSecCmCntAlertCheck_A	238132407	122	0	0
FpvSecCmMainFsmCheck_A	238132407	80	0	0
FpvSecCmRegWeOnehotCheck_A	238132407	80	0	0
IntrEdnCmdReqDoneKnownO_A	238132407	237997184	0	0
TlAReadyKnownO_A	238132407	237997184	0	0
TlDValidKnownO_A	238132407	237997184	0	0
gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A	238132407	80	0	0
gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A	238132407	80	0	0
gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A	238132407	80	0	0
gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A	238132407	80	0	0
gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A	238132407	80	0	0
gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A	238132407	80	0	0
gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A	238132407	80	0	0
gen_edn_if_asserts[0].EdnDataStableDisable_A	238132407	502005	0	0
gen_edn_if_asserts[0].EdnDataStable_A	238132407	6742	0	157
gen_edn_if_asserts[0].EdnEndPointOut_A	238132407	237997184	0	0
gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A	238132407	130359	0	0
gen_edn_if_asserts[1].EdnDataStableDisable_A	238132407	502005	0	0
gen_edn_if_asserts[1].EdnDataStable_A	238132407	654	0	33
gen_edn_if_asserts[1].EdnEndPointOut_A	238132407	237997184	0	0
gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A	238132407	130359	0	0
gen_edn_if_asserts[2].EdnDataStableDisable_A	238132407	502005	0	0
gen_edn_if_asserts[2].EdnDataStable_A	238132407	569	0	32
gen_edn_if_asserts[2].EdnEndPointOut_A	238132407	237997184	0	0
gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A	238132407	130359	0	0
gen_edn_if_asserts[3].EdnDataStableDisable_A	238132407	502005	0	0
gen_edn_if_asserts[3].EdnDataStable_A	238132407	570	0	19
gen_edn_if_asserts[3].EdnEndPointOut_A	238132407	237997184	0	0
gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A	238132407	130359	0	0
gen_edn_if_asserts[4].EdnDataStableDisable_A	238132407	502005	0	0
gen_edn_if_asserts[4].EdnDataStable_A	238132407	641	0	24
gen_edn_if_asserts[4].EdnEndPointOut_A	238132407	237997184	0	0
gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A	238132407	130359	0	0
gen_edn_if_asserts[5].EdnDataStableDisable_A	238132407	502005	0	0
gen_edn_if_asserts[5].EdnDataStable_A	238132407	689	0	25
gen_edn_if_asserts[5].EdnEndPointOut_A	238132407	237997184	0	0
gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A	238132407	130359	0	0
gen_edn_if_asserts[6].EdnDataStableDisable_A	238132407	502005	0	0
gen_edn_if_asserts[6].EdnDataStable_A	238132407	512	0	28
gen_edn_if_asserts[6].EdnEndPointOut_A	238132407	237997184	0	0
gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A	238132407	130359	0	0

AlertTxKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238132407	237997184	0	0
T1	355	208	0	0
T2	220160	220150	0	0
T3	762	628	0	0
T6	1699	1648	0	0
T16	1392	1297	0	0
T17	636233	636222	0	0
T18	988	902	0	0
T19	1023	924	0	0
T20	111164	111163	0	0
T21	13513	12809	0	0

CsrngAppIfOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238132407	237997184	0	0
T1	355	208	0	0
T2	220160	220150	0	0
T3	762	628	0	0
T6	1699	1648	0	0
T16	1392	1297	0	0
T17	636233	636222	0	0
T18	988	902	0	0
T19	1023	924	0	0
T20	111164	111163	0	0
T21	13513	12809	0	0

FpvSecCmCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238132407	122	0	0
T4	2270	1	0	0
T7	2346	0	0	0
T10	2816	0	0	0
T11	0	1	0	0
T12	0	1	0	0
T13	1136	0	0	0
T29	1890	0	0	0
T33	1188	0	0	0
T43	979	0	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	12086	0	0	0
T52	12077	0	0	0
T53	341629	0	0	0

FpvSecCmMainFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238132407	80	0	0
T22	39962	20	0	0
T23	0	10	0	0
T24	0	20	0	0
T54	0	20	0	0
T55	0	10	0	0
T56	1156	0	0	0
T57	1677	0	0	0
T58	833	0	0	0
T59	372240	0	0	0
T60	1022	0	0	0
T61	1178	0	0	0
T62	1833	0	0	0
T63	1909	0	0	0
T64	1184	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238132407	80	0	0
T22	39962	20	0	0
T23	0	10	0	0
T24	0	20	0	0
T54	0	20	0	0
T55	0	10	0	0
T56	1156	0	0	0
T57	1677	0	0	0
T58	833	0	0	0
T59	372240	0	0	0
T60	1022	0	0	0
T61	1178	0	0	0
T62	1833	0	0	0
T63	1909	0	0	0
T64	1184	0	0	0

IntrEdnCmdReqDoneKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238132407	237997184	0	0
T1	355	208	0	0
T2	220160	220150	0	0
T3	762	628	0	0
T6	1699	1648	0	0
T16	1392	1297	0	0
T17	636233	636222	0	0
T18	988	902	0	0
T19	1023	924	0	0
T20	111164	111163	0	0
T21	13513	12809	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238132407	237997184	0	0
T1	355	208	0	0
T2	220160	220150	0	0
T3	762	628	0	0
T6	1699	1648	0	0
T16	1392	1297	0	0
T17	636233	636222	0	0
T18	988	902	0	0
T19	1023	924	0	0
T20	111164	111163	0	0
T21	13513	12809	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238132407	237997184	0	0
T1	355	208	0	0
T2	220160	220150	0	0
T3	762	628	0	0
T6	1699	1648	0	0
T16	1392	1297	0	0
T17	636233	636222	0	0
T18	988	902	0	0
T19	1023	924	0	0
T20	111164	111163	0	0
T21	13513	12809	0	0

gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238132407	80	0	0
T22	39962	20	0	0
T23	0	10	0	0
T24	0	20	0	0
T54	0	20	0	0
T55	0	10	0	0
T56	1156	0	0	0
T57	1677	0	0	0
T58	833	0	0	0
T59	372240	0	0	0
T60	1022	0	0	0
T61	1178	0	0	0
T62	1833	0	0	0
T63	1909	0	0	0
T64	1184	0	0	0

gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238132407	80	0	0
T22	39962	20	0	0
T23	0	10	0	0
T24	0	20	0	0
T54	0	20	0	0
T55	0	10	0	0
T56	1156	0	0	0
T57	1677	0	0	0
T58	833	0	0	0
T59	372240	0	0	0
T60	1022	0	0	0
T61	1178	0	0	0
T62	1833	0	0	0
T63	1909	0	0	0
T64	1184	0	0	0

gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238132407	80	0	0
T22	39962	20	0	0
T23	0	10	0	0
T24	0	20	0	0
T54	0	20	0	0
T55	0	10	0	0
T56	1156	0	0	0
T57	1677	0	0	0
T58	833	0	0	0
T59	372240	0	0	0
T60	1022	0	0	0
T61	1178	0	0	0
T62	1833	0	0	0
T63	1909	0	0	0
T64	1184	0	0	0

gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238132407	80	0	0
T22	39962	20	0	0
T23	0	10	0	0
T24	0	20	0	0
T54	0	20	0	0
T55	0	10	0	0
T56	1156	0	0	0
T57	1677	0	0	0
T58	833	0	0	0
T59	372240	0	0	0
T60	1022	0	0	0
T61	1178	0	0	0
T62	1833	0	0	0
T63	1909	0	0	0
T64	1184	0	0	0

gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238132407	80	0	0
T22	39962	20	0	0
T23	0	10	0	0
T24	0	20	0	0
T54	0	20	0	0
T55	0	10	0	0
T56	1156	0	0	0
T57	1677	0	0	0
T58	833	0	0	0
T59	372240	0	0	0
T60	1022	0	0	0
T61	1178	0	0	0
T62	1833	0	0	0
T63	1909	0	0	0
T64	1184	0	0	0

gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238132407	80	0	0
T22	39962	20	0	0
T23	0	10	0	0
T24	0	20	0	0
T54	0	20	0	0
T55	0	10	0	0
T56	1156	0	0	0
T57	1677	0	0	0
T58	833	0	0	0
T59	372240	0	0	0
T60	1022	0	0	0
T61	1178	0	0	0
T62	1833	0	0	0
T63	1909	0	0	0
T64	1184	0	0	0

gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238132407	80	0	0
T22	39962	20	0	0
T23	0	10	0	0
T24	0	20	0	0
T54	0	20	0	0
T55	0	10	0	0
T56	1156	0	0	0
T57	1677	0	0	0
T58	833	0	0	0
T59	372240	0	0	0
T60	1022	0	0	0
T61	1178	0	0	0
T62	1833	0	0	0
T63	1909	0	0	0
T64	1184	0	0	0

gen_edn_if_asserts[0].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238132407	502005	0	0
T1	355	91	0	0
T2	220160	1166	0	0
T3	762	384	0	0
T6	1699	626	0	0
T16	1392	1296	0	0
T17	636233	2459	0	0
T18	988	901	0	0
T19	1023	14	0	0
T20	111164	1182	0	0
T21	13513	3950	0	0

gen_edn_if_asserts[0].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238132407	6742	0	157
T2	220160	44	0	0
T3	762	0	0	0
T4	2270	0	0	0
T6	1699	0	0	0
T7	0	60	0	1
T8	0	47	0	1
T16	1392	0	0	0
T17	636233	87	0	0
T18	988	0	0	0
T19	1023	3	0	1
T20	111164	134	0	0
T21	13513	9	0	0
T51	0	3	0	0
T52	0	16	0	0
T53	0	59	0	0
T65	0	0	0	1
T66	0	0	0	1
T67	0	0	0	1
T68	0	0	0	1
T69	0	0	0	1
T70	0	0	0	1
T71	0	0	0	1

gen_edn_if_asserts[0].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238132407	237997184	0	0
T1	355	208	0	0
T2	220160	220150	0	0
T3	762	628	0	0
T6	1699	1648	0	0
T16	1392	1297	0	0
T17	636233	636222	0	0
T18	988	902	0	0
T19	1023	924	0	0
T20	111164	111163	0	0
T21	13513	12809	0	0

gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238132407	130359	0	0
T1	355	7	0	0
T2	220160	0	0	0
T3	762	352	0	0
T4	0	1075	0	0
T5	0	1072	0	0
T6	1699	0	0	0
T11	0	1084	0	0
T12	0	360	0	0
T16	1392	0	0	0
T17	636233	0	0	0
T18	988	0	0	0
T19	1023	0	0	0
T20	111164	0	0	0
T21	13513	0	0	0
T44	0	924	0	0
T72	0	375	0	0
T73	0	17	0	0
T74	0	235	0	0

gen_edn_if_asserts[1].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238132407	502005	0	0
T1	355	91	0	0
T2	220160	1166	0	0
T3	762	384	0	0
T6	1699	626	0	0
T16	1392	1296	0	0
T17	636233	2459	0	0
T18	988	901	0	0
T19	1023	14	0	0
T20	111164	1182	0	0
T21	13513	3950	0	0

gen_edn_if_asserts[1].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238132407	654	0	33
T11	2019	0	0	0
T15	0	4	0	1
T30	0	14	0	1
T34	1771	3	0	0
T35	887	3	0	1
T36	0	44	0	1
T38	0	62	0	1
T39	0	4	0	1
T41	0	57	0	1
T58	0	3	0	1
T68	1262	0	0	0
T69	1111	0	0	0
T70	11266	0	0	0
T73	762	0	0	0
T74	443	0	0	0
T75	0	3	0	0
T76	1858	0	0	0
T77	386503	0	0	0
T78	0	0	0	1
T79	0	0	0	1

gen_edn_if_asserts[1].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238132407	237997184	0	0
T1	355	208	0	0
T2	220160	220150	0	0
T3	762	628	0	0
T6	1699	1648	0	0
T16	1392	1297	0	0
T17	636233	636222	0	0
T18	988	902	0	0
T19	1023	924	0	0
T20	111164	111163	0	0
T21	13513	12809	0	0

gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238132407	130359	0	0
T1	355	7	0	0
T2	220160	0	0	0
T3	762	352	0	0
T4	0	1075	0	0
T5	0	1072	0	0
T6	1699	0	0	0
T11	0	1084	0	0
T12	0	360	0	0
T16	1392	0	0	0
T17	636233	0	0	0
T18	988	0	0	0
T19	1023	0	0	0
T20	111164	0	0	0
T21	13513	0	0	0
T44	0	924	0	0
T72	0	375	0	0
T73	0	17	0	0
T74	0	235	0	0

gen_edn_if_asserts[2].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238132407	502005	0	0
T1	355	91	0	0
T2	220160	1166	0	0
T3	762	384	0	0
T6	1699	626	0	0
T16	1392	1296	0	0
T17	636233	2459	0	0
T18	988	901	0	0
T19	1023	14	0	0
T20	111164	1182	0	0
T21	13513	3950	0	0

gen_edn_if_asserts[2].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238132407	569	0	32
T9	0	10	0	1
T14	1461	4	0	1
T25	1095	3	0	1
T26	1630	3	0	0
T30	0	7	0	1
T38	0	13	0	1
T39	0	0	0	1
T40	0	22	0	1
T41	0	0	0	1
T57	0	0	0	1
T65	1263	0	0	0
T66	7602	0	0	0
T67	2077	0	0	0
T80	0	3	0	0
T81	0	4	0	1
T82	0	3	0	0
T83	1350	0	0	0
T84	2613	0	0	0
T85	244770	0	0	0
T86	1416	0	0	0

gen_edn_if_asserts[2].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238132407	237997184	0	0
T1	355	208	0	0
T2	220160	220150	0	0
T3	762	628	0	0
T6	1699	1648	0	0
T16	1392	1297	0	0
T17	636233	636222	0	0
T18	988	902	0	0
T19	1023	924	0	0
T20	111164	111163	0	0
T21	13513	12809	0	0

gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238132407	130359	0	0
T1	355	7	0	0
T2	220160	0	0	0
T3	762	352	0	0
T4	0	1075	0	0
T5	0	1072	0	0
T6	1699	0	0	0
T11	0	1084	0	0
T12	0	360	0	0
T16	1392	0	0	0
T17	636233	0	0	0
T18	988	0	0	0
T19	1023	0	0	0
T20	111164	0	0	0
T21	13513	0	0	0
T44	0	924	0	0
T72	0	375	0	0
T73	0	17	0	0
T74	0	235	0	0

gen_edn_if_asserts[3].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238132407	502005	0	0
T1	355	91	0	0
T2	220160	1166	0	0
T3	762	384	0	0
T6	1699	626	0	0
T16	1392	1296	0	0
T17	636233	2459	0	0
T18	988	901	0	0
T19	1023	14	0	0
T20	111164	1182	0	0
T21	13513	3950	0	0

gen_edn_if_asserts[3].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238132407	570	0	19
T5	1971	0	0	0
T8	1879	0	0	0
T25	1095	0	0	0
T27	2154	3	0	0
T28	1257	3	0	0
T30	0	31	0	1
T31	0	3	0	0
T38	0	7	0	1
T40	0	53	0	1
T41	0	17	0	1
T72	678	0	0	0
T87	0	4	0	1
T88	0	3	0	0
T89	0	3	0	0
T90	646	0	0	0
T91	1476	0	0	0
T92	139952	0	0	0
T93	704	0	0	0
T94	0	0	0	1
T95	0	0	0	1
T96	0	0	0	1
T97	0	0	0	1
T98	0	0	0	1

gen_edn_if_asserts[3].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238132407	237997184	0	0
T1	355	208	0	0
T2	220160	220150	0	0
T3	762	628	0	0
T6	1699	1648	0	0
T16	1392	1297	0	0
T17	636233	636222	0	0
T18	988	902	0	0
T19	1023	924	0	0
T20	111164	111163	0	0
T21	13513	12809	0	0

gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238132407	130359	0	0
T1	355	7	0	0
T2	220160	0	0	0
T3	762	352	0	0
T4	0	1075	0	0
T5	0	1072	0	0
T6	1699	0	0	0
T11	0	1084	0	0
T12	0	360	0	0
T16	1392	0	0	0
T17	636233	0	0	0
T18	988	0	0	0
T19	1023	0	0	0
T20	111164	0	0	0
T21	13513	0	0	0
T44	0	924	0	0
T72	0	375	0	0
T73	0	17	0	0
T74	0	235	0	0

gen_edn_if_asserts[4].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238132407	502005	0	0
T1	355	91	0	0
T2	220160	1166	0	0
T3	762	384	0	0
T6	1699	626	0	0
T16	1392	1296	0	0
T17	636233	2459	0	0
T18	988	901	0	0
T19	1023	14	0	0
T20	111164	1182	0	0
T21	13513	3950	0	0

gen_edn_if_asserts[4].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238132407	641	0	24
T7	2346	0	0	0
T9	1970	13	0	1
T12	670	0	0	0
T13	1136	0	0	0
T29	1890	3	0	0
T30	0	45	0	1
T36	0	10	0	1
T38	0	55	0	1
T39	0	42	0	1
T40	0	41	0	1
T41	0	45	0	1
T43	979	0	0	0
T44	2620	0	0	0
T52	12077	0	0	0
T53	341629	0	0	0
T78	0	45	0	1
T95	0	0	0	1
T99	0	3	0	0
T100	2105	0	0	0
T101	0	0	0	1

gen_edn_if_asserts[4].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238132407	237997184	0	0
T1	355	208	0	0
T2	220160	220150	0	0
T3	762	628	0	0
T6	1699	1648	0	0
T16	1392	1297	0	0
T17	636233	636222	0	0
T18	988	902	0	0
T19	1023	924	0	0
T20	111164	111163	0	0
T21	13513	12809	0	0

gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238132407	130359	0	0
T1	355	7	0	0
T2	220160	0	0	0
T3	762	352	0	0
T4	0	1075	0	0
T5	0	1072	0	0
T6	1699	0	0	0
T11	0	1084	0	0
T12	0	360	0	0
T16	1392	0	0	0
T17	636233	0	0	0
T18	988	0	0	0
T19	1023	0	0	0
T20	111164	0	0	0
T21	13513	0	0	0
T44	0	924	0	0
T72	0	375	0	0
T73	0	17	0	0
T74	0	235	0	0

gen_edn_if_asserts[5].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238132407	502005	0	0
T1	355	91	0	0
T2	220160	1166	0	0
T3	762	384	0	0
T6	1699	626	0	0
T16	1392	1296	0	0
T17	636233	2459	0	0
T18	988	901	0	0
T19	1023	14	0	0
T20	111164	1182	0	0
T21	13513	3950	0	0

gen_edn_if_asserts[5].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238132407	689	0	25
T7	2346	44	0	1
T13	1136	0	0	0
T30	0	27	0	1
T31	1618	3	0	0
T32	1560	3	0	0
T36	0	29	0	1
T37	2362	0	0	0
T38	0	46	0	1
T39	0	44	0	1
T40	0	23	0	1
T41	0	19	0	1
T43	979	0	0	0
T45	684	0	0	0
T78	0	0	0	1
T102	0	4	0	1
T103	2220	0	0	0
T104	959	0	0	0
T105	2426	0	0	0
T106	0	0	0	1

gen_edn_if_asserts[5].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238132407	237997184	0	0
T1	355	208	0	0
T2	220160	220150	0	0
T3	762	628	0	0
T6	1699	1648	0	0
T16	1392	1297	0	0
T17	636233	636222	0	0
T18	988	902	0	0
T19	1023	924	0	0
T20	111164	111163	0	0
T21	13513	12809	0	0

gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238132407	130359	0	0
T1	355	7	0	0
T2	220160	0	0	0
T3	762	352	0	0
T4	0	1075	0	0
T5	0	1072	0	0
T6	1699	0	0	0
T11	0	1084	0	0
T12	0	360	0	0
T16	1392	0	0	0
T17	636233	0	0	0
T18	988	0	0	0
T19	1023	0	0	0
T20	111164	0	0	0
T21	13513	0	0	0
T44	0	924	0	0
T72	0	375	0	0
T73	0	17	0	0
T74	0	235	0	0

gen_edn_if_asserts[6].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238132407	502005	0	0
T1	355	91	0	0
T2	220160	1166	0	0
T3	762	384	0	0
T6	1699	626	0	0
T16	1392	1296	0	0
T17	636233	2459	0	0
T18	988	901	0	0
T19	1023	14	0	0
T20	111164	1182	0	0
T21	13513	3950	0	0

gen_edn_if_asserts[6].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238132407	512	0	28
T4	2270	0	0	0
T6	1699	3	0	0
T7	2346	0	0	0
T10	2816	3	0	0
T13	0	4	0	1
T21	13513	0	0	0
T29	1890	0	0	0
T30	0	0	0	1
T33	1188	3	0	1
T36	0	0	0	1
T37	0	3	0	0
T38	0	0	0	1
T39	0	0	0	1
T43	0	3	0	1
T51	12086	0	0	0
T52	12077	0	0	0
T53	341629	0	0	0
T93	0	3	0	1
T100	0	3	0	0
T105	0	3	0	0
T107	0	3	0	0
T108	0	0	0	1
T109	0	0	0	1

gen_edn_if_asserts[6].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238132407	237997184	0	0
T1	355	208	0	0
T2	220160	220150	0	0
T3	762	628	0	0
T6	1699	1648	0	0
T16	1392	1297	0	0
T17	636233	636222	0	0
T18	988	902	0	0
T19	1023	924	0	0
T20	111164	111163	0	0
T21	13513	12809	0	0

gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	238132407	130359	0	0
T1	355	7	0	0
T2	220160	0	0	0
T3	762	352	0	0
T4	0	1075	0	0
T5	0	1072	0	0
T6	1699	0	0	0
T11	0	1084	0	0
T12	0	360	0	0
T16	1392	0	0	0
T17	636233	0	0	0
T18	988	0	0	0
T19	1023	0	0	0
T20	111164	0	0	0
T21	13513	0	0	0
T44	0	924	0	0
T72	0	375	0	0
T73	0	17	0	0
T74	0	235	0	0