Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44		83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	217897388	9983982	0	0
boot_gen_cmd_rd_A	217897388	44179	0	0
boot_ins_cmd_rd_A	217897388	50033	0	0
ctrl_rd_A	217897388	44463	0	0
err_code_test_rd_A	217897388	43677	0	0
intr_enable_rd_A	217897388	50703	0	0
max_num_reqs_between_reseeds_rd_A	217897388	51257	0	0
regwen_rd_A	217897388	51326	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217897388	9983982	0	0
T6	756	0	0	0
T13	1950	0	0	0
T17	1476	0	0	0
T24	227829	132671	0	0
T25	134427	55701	0	0
T26	0	305199	0	0
T36	808	0	0	0
T65	1455	0	0	0
T66	10451	0	0	0
T67	1633	0	0	0
T78	840	0	0	0
T93	0	58567	0	0
T102	0	335406	0	0
T136	0	244661	0	0
T189	0	114394	0	0
T190	0	64986	0	0
T191	0	191659	0	0
T192	0	532088	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217897388	44179	0	0
T38	1632	0	0	0
T40	1389	0	0	0
T43	1903	0	0	0
T93	158055	1041	0	0
T94	986	0	0	0
T136	703565	6840	0	0
T182	743	0	0	0
T189	315722	3298	0	0
T193	0	1390	0	0
T194	0	4745	0	0
T195	0	3319	0	0
T196	0	3783	0	0
T197	0	22	0	0
T198	0	6	0	0
T199	0	11	0	0
T200	1663	0	0	0
T201	991	0	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217897388	50033	0	0
T38	1632	0	0	0
T40	1389	0	0	0
T43	1903	0	0	0
T93	158055	991	0	0
T94	986	0	0	0
T136	703565	7567	0	0
T182	743	0	0	0
T189	315722	3817	0	0
T193	0	1761	0	0
T194	0	5452	0	0
T195	0	3902	0	0
T196	0	4539	0	0
T197	0	8	0	0
T198	0	9	0	0
T200	1663	0	0	0
T201	991	0	0	0
T202	0	13	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217897388	44463	0	0
T31	2306	0	0	0
T32	767	0	0	0
T33	2402	0	0	0
T37	2319	0	0	0
T70	19945	4	0	0
T71	1012	0	0	0
T72	10914	0	0	0
T93	0	820	0	0
T98	0	4	0	0
T100	9284	0	0	0
T101	0	4	0	0
T136	0	6531	0	0
T137	10017	0	0	0
T144	2352	0	0	0
T162	0	6	0	0
T189	0	3300	0	0
T193	0	1266	0	0
T194	0	4948	0	0
T195	0	3480	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217897388	43677	0	0
T38	1632	0	0	0
T40	1389	0	0	0
T43	1903	0	0	0
T93	158055	921	0	0
T94	986	0	0	0
T136	703565	6824	0	0
T182	743	0	0	0
T189	315722	3221	0	0
T193	0	1352	0	0
T194	0	4656	0	0
T195	0	3543	0	0
T196	0	3907	0	0
T197	0	21	0	0
T198	0	12	0	0
T199	0	11	0	0
T200	1663	0	0	0
T201	991	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217897388	50703	0	0
T31	2306	0	0	0
T37	2319	0	0	0
T53	1887	0	0	0
T70	19945	135	0	0
T71	1012	0	0	0
T72	10914	0	0	0
T79	19420	65	0	0
T93	0	1086	0	0
T101	0	64	0	0
T107	1198	0	0	0
T136	0	7149	0	0
T137	10017	0	0	0
T144	2352	0	0	0
T189	0	3544	0	0
T193	0	1496	0	0
T194	0	5454	0	0
T195	0	3583	0	0
T196	0	4327	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217897388	51257	0	0
T38	1632	0	0	0
T40	1389	0	0	0
T43	1903	0	0	0
T93	158055	969	0	0
T94	986	0	0	0
T136	703565	7867	0	0
T182	743	0	0	0
T189	315722	3682	0	0
T193	0	1384	0	0
T194	0	5624	0	0
T195	0	3798	0	0
T196	0	4395	0	0
T197	0	35	0	0
T200	1663	0	0	0
T201	991	0	0	0
T202	0	1	0	0
T203	0	47	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217897388	51326	0	0
T38	1632	0	0	0
T40	1389	0	0	0
T43	1903	0	0	0
T93	158055	1029	0	0
T94	986	0	0	0
T136	703565	7924	0	0
T182	743	0	0	0
T189	315722	3759	0	0
T193	0	1343	0	0
T194	0	5553	0	0
T195	0	4098	0	0
T196	0	4389	0	0
T197	0	12	0	0
T200	1663	0	0	0
T201	991	0	0	0
T202	0	7	0	0
T203	0	43	0	0