Unified Coverage Report :: Module :: edn

Module : edn

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	94.44		83.33	100.00			100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.68	99.02	92.39	96.84	93.42	98.62	99.77

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
edn_csr_assert	100.00						100.00
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_edn_core	92.09	99.92	89.68	71.29	93.42	99.29	98.91
u_edn_cov_if	25.00	50.00	0.00
u_reg	98.63	96.98	98.92	100.00		97.26	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Cond Coverage for Module : edn

	Total	Covered	Percent
Conditions	6	5	83.33
Logical	6	5	83.33
Non-Logical	0	0
Event	0	0

 LINE       99
 EXPRESSION (alert[0] || intg_err_alert[0])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T16,T17,T18

 LINE       99
 EXPRESSION (alert[1] || intg_err_alert[1])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T15,T22,T23
1	0	Covered	T1,T3,T4

---

Toggle Coverage for Module : edn

	Total	Covered	Percent
Totals	69	69	100.00
Total Bits	1168	1168	100.00
Total Bits 0->1	584	584	100.00
Total Bits 1->0	584	584	100.00

Ports	69	69	100.00
Port Bits	1168	1168	100.00
Port Bits 0->1	584	584	100.00
Port Bits 1->0	584	584	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T2,T3,T14	Yes	T2,T3,T14	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T24,T25,T26	Yes	T24,T25,T26	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i[0].edn_req	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
edn_i[1].edn_req	Yes	Yes	T4,T5,T27	Yes	T4,T5,T27	INPUT
edn_i[2].edn_req	Yes	Yes	T28,T29,T30	Yes	T28,T29,T30	INPUT
edn_i[3].edn_req	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	INPUT
edn_i[4].edn_req	Yes	Yes	T34,T7,T35	Yes	T34,T7,T35	INPUT
edn_i[5].edn_req	Yes	Yes	T36,T37,T38	Yes	T36,T37,T38	INPUT
edn_i[6].edn_req	Yes	Yes	T21,T8,T39	Yes	T21,T8,T39	INPUT
edn_o[0].edn_bus[31:0]	Yes	Yes	T2,T3,T16	Yes	T2,T3,T16	OUTPUT
edn_o[0].edn_fips	Yes	Yes	T2,T20,T24	Yes	T2,T16,T20	OUTPUT
edn_o[0].edn_ack	Yes	Yes	T2,T3,T16	Yes	T2,T3,T16	OUTPUT
edn_o[1].edn_bus[31:0]	Yes	Yes	T27,T18,T40	Yes	T27,T13,T33	OUTPUT
edn_o[1].edn_fips	Yes	Yes	T41,T38,T42	Yes	T41,T40,T38	OUTPUT
edn_o[1].edn_ack	Yes	Yes	T27,T41,T13	Yes	T27,T41,T13	OUTPUT
edn_o[2].edn_bus[31:0]	Yes	Yes	T29,T38,T43	Yes	T29,T44,T38	OUTPUT
edn_o[2].edn_fips	Yes	Yes	T29,T30,T38	Yes	T29,T30,T44	OUTPUT
edn_o[2].edn_ack	Yes	Yes	T29,T30,T44	Yes	T29,T30,T44	OUTPUT
edn_o[3].edn_bus[31:0]	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
edn_o[3].edn_fips	Yes	Yes	T43,T45,T46	Yes	T31,T32,T38	OUTPUT
edn_o[3].edn_ack	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
edn_o[4].edn_bus[31:0]	Yes	Yes	T34,T35,T47	Yes	T34,T35,T47	OUTPUT
edn_o[4].edn_fips	Yes	Yes	T35,T48,T42	Yes	T34,T35,T40	OUTPUT
edn_o[4].edn_ack	Yes	Yes	T34,T7,T35	Yes	T34,T7,T35	OUTPUT
edn_o[5].edn_bus[31:0]	Yes	Yes	T37,T38,T43	Yes	T37,T38,T43	OUTPUT
edn_o[5].edn_fips	Yes	Yes	T38,T43,T46	Yes	T38,T43,T49	OUTPUT
edn_o[5].edn_ack	Yes	Yes	T37,T38,T43	Yes	T37,T38,T43	OUTPUT
edn_o[6].edn_bus[31:0]	Yes	Yes	T21,T8,T50	Yes	T21,T8,T39	OUTPUT
edn_o[6].edn_fips	Yes	Yes	T21,T50,T43	Yes	T21,T8,T39	OUTPUT
edn_o[6].edn_ack	Yes	Yes	T21,T8,T39	Yes	T21,T8,T39	OUTPUT
csrng_cmd_o.genbits_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
csrng_cmd_o.csrng_req_valid	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
csrng_cmd_i.genbits_bus[127:0]	Yes	Yes	T2,T20,T24	Yes	T2,T20,T9	INPUT
csrng_cmd_i.genbits_fips	Yes	Yes	T2,T20,T21	Yes	T2,T20,T8	INPUT
csrng_cmd_i.genbits_valid	Yes	Yes	T2,T3,T16	Yes	T2,T3,T16	INPUT
csrng_cmd_i.csrng_rsp_sts	Yes	Yes	T2,T3,T14	Yes	T2,T3,T14	INPUT
csrng_cmd_i.csrng_rsp_ack	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
csrng_cmd_i.csrng_req_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T16,T19,T51	Yes	T16,T19,T51	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T16,T19,T51	Yes	T16,T19,T51	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T20,T24,T25	Yes	T20,T24,T25	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T3,T20,T52	Yes	T3,T20,T52	OUTPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Module : edn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	43	43	100.00	43	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	43	43	100.00	43	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnownO_A	217412720	217290855	0	0
CsrngAppIfOut_A	217412720	217290855	0	0
FpvSecCmCntAlertCheck_A	217412720	99	0	0
FpvSecCmMainFsmCheck_A	217412720	60	0	0
FpvSecCmRegWeOnehotCheck_A	217412720	60	0	0
IntrEdnCmdReqDoneKnownO_A	217412720	217290855	0	0
TlAReadyKnownO_A	217412720	217290855	0	0
TlDValidKnownO_A	217412720	217290855	0	0
gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A	217412720	60	0	0
gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A	217412720	60	0	0
gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A	217412720	60	0	0
gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A	217412720	60	0	0
gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A	217412720	60	0	0
gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A	217412720	60	0	0
gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A	217412720	60	0	0
gen_edn_if_asserts[0].EdnDataStableDisable_A	217412720	494179	0	0
gen_edn_if_asserts[0].EdnDataStable_A	217412720	6169	0	147
gen_edn_if_asserts[0].EdnEndPointOut_A	217412720	217290855	0	0
gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A	217412720	127540	0	0
gen_edn_if_asserts[1].EdnDataStableDisable_A	217412720	494179	0	0
gen_edn_if_asserts[1].EdnDataStable_A	217412720	838	0	31
gen_edn_if_asserts[1].EdnEndPointOut_A	217412720	217290855	0	0
gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A	217412720	127540	0	0
gen_edn_if_asserts[2].EdnDataStableDisable_A	217412720	494179	0	0
gen_edn_if_asserts[2].EdnDataStable_A	217412720	629	0	27
gen_edn_if_asserts[2].EdnEndPointOut_A	217412720	217290855	0	0
gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A	217412720	127540	0	0
gen_edn_if_asserts[3].EdnDataStableDisable_A	217412720	494179	0	0
gen_edn_if_asserts[3].EdnDataStable_A	217412720	611	0	23
gen_edn_if_asserts[3].EdnEndPointOut_A	217412720	217290855	0	0
gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A	217412720	127540	0	0
gen_edn_if_asserts[4].EdnDataStableDisable_A	217412720	494179	0	0
gen_edn_if_asserts[4].EdnDataStable_A	217412720	495	0	24
gen_edn_if_asserts[4].EdnEndPointOut_A	217412720	217290855	0	0
gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A	217412720	127540	0	0
gen_edn_if_asserts[5].EdnDataStableDisable_A	217412720	494179	0	0
gen_edn_if_asserts[5].EdnDataStable_A	217412720	672	0	26
gen_edn_if_asserts[5].EdnEndPointOut_A	217412720	217290855	0	0
gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A	217412720	127540	0	0
gen_edn_if_asserts[6].EdnDataStableDisable_A	217412720	494179	0	0
gen_edn_if_asserts[6].EdnDataStable_A	217412720	441	0	15
gen_edn_if_asserts[6].EdnEndPointOut_A	217412720	217290855	0	0
gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A	217412720	127540	0	0

AlertTxKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217412720	217290855	0	0
T1	730	588	0	0
T2	1474	1413	0	0
T3	755	638	0	0
T4	1853	1729	0	0
T5	1568	1396	0	0
T14	2013	1838	0	0
T16	1342	1287	0	0
T19	1676	1581	0	0
T20	12915	12305	0	0
T21	1123	1057	0	0

CsrngAppIfOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217412720	217290855	0	0
T1	730	588	0	0
T2	1474	1413	0	0
T3	755	638	0	0
T4	1853	1729	0	0
T5	1568	1396	0	0
T14	2013	1838	0	0
T16	1342	1287	0	0
T19	1676	1581	0	0
T20	12915	12305	0	0
T21	1123	1057	0	0

FpvSecCmCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217412720	99	0	0
T5	1568	1	0	0
T14	2013	1	0	0
T15	0	10	0	0
T16	1342	0	0	0
T19	1676	0	0	0
T20	12915	0	0	0
T21	1123	0	0	0
T28	1407	0	0	0
T45	0	1	0	0
T52	711	0	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	1908	0	0	0
T60	1026	0	0	0

FpvSecCmMainFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217412720	60	0	0
T13	1950	0	0	0
T15	19930	10	0	0
T22	0	10	0	0
T23	0	10	0	0
T24	227829	0	0	0
T36	808	0	0	0
T41	1433	0	0	0
T61	0	20	0	0
T62	0	10	0	0
T63	2813	0	0	0
T64	1126	0	0	0
T65	1455	0	0	0
T66	10451	0	0	0
T67	1633	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217412720	60	0	0
T13	1950	0	0	0
T15	19930	10	0	0
T22	0	10	0	0
T23	0	10	0	0
T24	227829	0	0	0
T36	808	0	0	0
T41	1433	0	0	0
T61	0	20	0	0
T62	0	10	0	0
T63	2813	0	0	0
T64	1126	0	0	0
T65	1455	0	0	0
T66	10451	0	0	0
T67	1633	0	0	0

IntrEdnCmdReqDoneKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217412720	217290855	0	0
T1	730	588	0	0
T2	1474	1413	0	0
T3	755	638	0	0
T4	1853	1729	0	0
T5	1568	1396	0	0
T14	2013	1838	0	0
T16	1342	1287	0	0
T19	1676	1581	0	0
T20	12915	12305	0	0
T21	1123	1057	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217412720	217290855	0	0
T1	730	588	0	0
T2	1474	1413	0	0
T3	755	638	0	0
T4	1853	1729	0	0
T5	1568	1396	0	0
T14	2013	1838	0	0
T16	1342	1287	0	0
T19	1676	1581	0	0
T20	12915	12305	0	0
T21	1123	1057	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217412720	217290855	0	0
T1	730	588	0	0
T2	1474	1413	0	0
T3	755	638	0	0
T4	1853	1729	0	0
T5	1568	1396	0	0
T14	2013	1838	0	0
T16	1342	1287	0	0
T19	1676	1581	0	0
T20	12915	12305	0	0
T21	1123	1057	0	0

gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217412720	60	0	0
T13	1950	0	0	0
T15	19930	10	0	0
T22	0	10	0	0
T23	0	10	0	0
T24	227829	0	0	0
T36	808	0	0	0
T41	1433	0	0	0
T61	0	20	0	0
T62	0	10	0	0
T63	2813	0	0	0
T64	1126	0	0	0
T65	1455	0	0	0
T66	10451	0	0	0
T67	1633	0	0	0

gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217412720	60	0	0
T13	1950	0	0	0
T15	19930	10	0	0
T22	0	10	0	0
T23	0	10	0	0
T24	227829	0	0	0
T36	808	0	0	0
T41	1433	0	0	0
T61	0	20	0	0
T62	0	10	0	0
T63	2813	0	0	0
T64	1126	0	0	0
T65	1455	0	0	0
T66	10451	0	0	0
T67	1633	0	0	0

gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217412720	60	0	0
T13	1950	0	0	0
T15	19930	10	0	0
T22	0	10	0	0
T23	0	10	0	0
T24	227829	0	0	0
T36	808	0	0	0
T41	1433	0	0	0
T61	0	20	0	0
T62	0	10	0	0
T63	2813	0	0	0
T64	1126	0	0	0
T65	1455	0	0	0
T66	10451	0	0	0
T67	1633	0	0	0

gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217412720	60	0	0
T13	1950	0	0	0
T15	19930	10	0	0
T22	0	10	0	0
T23	0	10	0	0
T24	227829	0	0	0
T36	808	0	0	0
T41	1433	0	0	0
T61	0	20	0	0
T62	0	10	0	0
T63	2813	0	0	0
T64	1126	0	0	0
T65	1455	0	0	0
T66	10451	0	0	0
T67	1633	0	0	0

gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217412720	60	0	0
T13	1950	0	0	0
T15	19930	10	0	0
T22	0	10	0	0
T23	0	10	0	0
T24	227829	0	0	0
T36	808	0	0	0
T41	1433	0	0	0
T61	0	20	0	0
T62	0	10	0	0
T63	2813	0	0	0
T64	1126	0	0	0
T65	1455	0	0	0
T66	10451	0	0	0
T67	1633	0	0	0

gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217412720	60	0	0
T13	1950	0	0	0
T15	19930	10	0	0
T22	0	10	0	0
T23	0	10	0	0
T24	227829	0	0	0
T36	808	0	0	0
T41	1433	0	0	0
T61	0	20	0	0
T62	0	10	0	0
T63	2813	0	0	0
T64	1126	0	0	0
T65	1455	0	0	0
T66	10451	0	0	0
T67	1633	0	0	0

gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217412720	60	0	0
T13	1950	0	0	0
T15	19930	10	0	0
T22	0	10	0	0
T23	0	10	0	0
T24	227829	0	0	0
T36	808	0	0	0
T41	1433	0	0	0
T61	0	20	0	0
T62	0	10	0	0
T63	2813	0	0	0
T64	1126	0	0	0
T65	1455	0	0	0
T66	10451	0	0	0
T67	1633	0	0	0

gen_edn_if_asserts[0].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217412720	494179	0	0
T1	730	319	0	0
T2	1474	65	0	0
T3	755	235	0	0
T4	1853	1078	0	0
T5	1568	996	0	0
T14	2013	1184	0	0
T16	1342	20	0	0
T19	1676	1580	0	0
T20	12915	1929	0	0
T21	1123	85	0	0

gen_edn_if_asserts[0].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217412720	6169	0	147
T2	1474	25	0	1
T3	755	0	0	0
T4	1853	0	0	0
T5	1568	0	0	0
T9	0	3	0	0
T14	2013	0	0	0
T16	1342	4	0	1
T17	0	0	0	1
T19	1676	0	0	0
T20	12915	12	0	1
T21	1123	0	0	0
T24	0	59	0	0
T28	1407	0	0	0
T60	0	3	0	1
T64	0	3	0	1
T66	0	14	0	0
T68	0	3	0	1
T69	0	3	0	0
T70	0	0	0	1
T71	0	0	0	1
T72	0	0	0	1

gen_edn_if_asserts[0].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217412720	217290855	0	0
T1	730	588	0	0
T2	1474	1413	0	0
T3	755	638	0	0
T4	1853	1729	0	0
T5	1568	1396	0	0
T14	2013	1838	0	0
T16	1342	1287	0	0
T19	1676	1581	0	0
T20	12915	12305	0	0
T21	1123	1057	0	0

gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217412720	127540	0	0
T1	730	421	0	0
T2	1474	0	0	0
T3	755	316	0	0
T4	1853	1174	0	0
T5	1568	699	0	0
T14	2013	1125	0	0
T15	0	6281	0	0
T16	1342	0	0	0
T19	1676	0	0	0
T20	12915	0	0	0
T21	1123	0	0	0
T27	0	15	0	0
T28	0	842	0	0
T52	0	290	0	0
T59	0	1110	0	0

gen_edn_if_asserts[1].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217412720	494179	0	0
T1	730	319	0	0
T2	1474	65	0	0
T3	755	235	0	0
T4	1853	1078	0	0
T5	1568	996	0	0
T14	2013	1184	0	0
T16	1342	20	0	0
T19	1676	1580	0	0
T20	12915	1929	0	0
T21	1123	85	0	0

gen_edn_if_asserts[1].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217412720	838	0	31
T6	756	0	0	0
T13	1950	3	0	0
T17	1476	0	0	0
T18	0	4	0	1
T25	134427	0	0	0
T30	708	0	0	0
T34	776	0	0	0
T36	808	0	0	0
T38	0	44	0	1
T40	0	3	0	0
T42	0	45	0	1
T67	1633	0	0	0
T73	0	3	0	0
T74	0	18	0	1
T75	0	33	0	1
T76	0	4	0	1
T77	0	3	0	0
T78	840	0	0	0
T79	19420	0	0	0
T80	0	0	0	1
T81	0	0	0	1
T82	0	0	0	1
T83	0	0	0	1

gen_edn_if_asserts[1].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217412720	217290855	0	0
T1	730	588	0	0
T2	1474	1413	0	0
T3	755	638	0	0
T4	1853	1729	0	0
T5	1568	1396	0	0
T14	2013	1838	0	0
T16	1342	1287	0	0
T19	1676	1581	0	0
T20	12915	12305	0	0
T21	1123	1057	0	0

gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217412720	127540	0	0
T1	730	421	0	0
T2	1474	0	0	0
T3	755	316	0	0
T4	1853	1174	0	0
T5	1568	699	0	0
T14	2013	1125	0	0
T15	0	6281	0	0
T16	1342	0	0	0
T19	1676	0	0	0
T20	12915	0	0	0
T21	1123	0	0	0
T27	0	15	0	0
T28	0	842	0	0
T52	0	290	0	0
T59	0	1110	0	0

gen_edn_if_asserts[2].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217412720	494179	0	0
T1	730	319	0	0
T2	1474	65	0	0
T3	755	235	0	0
T4	1853	1078	0	0
T5	1568	996	0	0
T14	2013	1184	0	0
T16	1342	20	0	0
T19	1676	1580	0	0
T20	12915	1929	0	0
T21	1123	85	0	0

gen_edn_if_asserts[2].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217412720	629	0	27
T18	1776	0	0	0
T29	872	3	0	0
T38	0	49	0	1
T40	1389	0	0	0
T42	0	54	0	1
T43	0	32	0	1
T44	1825	3	0	0
T83	0	0	0	1
T84	0	4	0	1
T85	0	3	0	0
T86	0	3	0	1
T87	0	3	0	1
T88	0	6	0	1
T89	13522	0	0	0
T90	1065	0	0	0
T91	1410	0	0	0
T92	1906	0	0	0
T93	158055	0	0	0
T94	986	0	0	0
T95	0	0	0	1
T96	0	0	0	1

gen_edn_if_asserts[2].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217412720	217290855	0	0
T1	730	588	0	0
T2	1474	1413	0	0
T3	755	638	0	0
T4	1853	1729	0	0
T5	1568	1396	0	0
T14	2013	1838	0	0
T16	1342	1287	0	0
T19	1676	1581	0	0
T20	12915	12305	0	0
T21	1123	1057	0	0

gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217412720	127540	0	0
T1	730	421	0	0
T2	1474	0	0	0
T3	755	316	0	0
T4	1853	1174	0	0
T5	1568	699	0	0
T14	2013	1125	0	0
T15	0	6281	0	0
T16	1342	0	0	0
T19	1676	0	0	0
T20	12915	0	0	0
T21	1123	0	0	0
T27	0	15	0	0
T28	0	842	0	0
T52	0	290	0	0
T59	0	1110	0	0

gen_edn_if_asserts[3].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217412720	494179	0	0
T1	730	319	0	0
T2	1474	65	0	0
T3	755	235	0	0
T4	1853	1078	0	0
T5	1568	996	0	0
T14	2013	1184	0	0
T16	1342	20	0	0
T19	1676	1580	0	0
T20	12915	1929	0	0
T21	1123	85	0	0

gen_edn_if_asserts[3].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217412720	611	0	23
T7	2785	0	0	0
T26	728064	0	0	0
T31	2306	3	0	0
T32	767	3	0	1
T33	2402	3	0	0
T37	2319	0	0	0
T38	0	23	0	1
T42	0	30	0	1
T43	0	13	0	1
T46	0	40	0	1
T50	689	0	0	0
T75	0	0	0	1
T80	0	0	0	1
T81	0	0	0	1
T83	0	0	0	1
T97	0	3	0	0
T98	0	3	0	0
T99	0	3	0	0
T100	9284	0	0	0
T101	19502	0	0	0
T102	580552	0	0	0
T103	0	0	0	1

gen_edn_if_asserts[3].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217412720	217290855	0	0
T1	730	588	0	0
T2	1474	1413	0	0
T3	755	638	0	0
T4	1853	1729	0	0
T5	1568	1396	0	0
T14	2013	1838	0	0
T16	1342	1287	0	0
T19	1676	1581	0	0
T20	12915	12305	0	0
T21	1123	1057	0	0

gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217412720	127540	0	0
T1	730	421	0	0
T2	1474	0	0	0
T3	755	316	0	0
T4	1853	1174	0	0
T5	1568	699	0	0
T14	2013	1125	0	0
T15	0	6281	0	0
T16	1342	0	0	0
T19	1676	0	0	0
T20	12915	0	0	0
T21	1123	0	0	0
T27	0	15	0	0
T28	0	842	0	0
T52	0	290	0	0
T59	0	1110	0	0

gen_edn_if_asserts[4].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217412720	494179	0	0
T1	730	319	0	0
T2	1474	65	0	0
T3	755	235	0	0
T4	1853	1078	0	0
T5	1568	996	0	0
T14	2013	1184	0	0
T16	1342	20	0	0
T19	1676	1580	0	0
T20	12915	1929	0	0
T21	1123	85	0	0

gen_edn_if_asserts[4].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217412720	495	0	24
T30	708	0	0	0
T34	776	3	0	1
T35	699	3	0	0
T42	0	29	0	1
T44	1825	0	0	0
T47	0	4	0	1
T53	1887	0	0	0
T54	1872	0	0	0
T75	0	62	0	1
T79	19420	0	0	0
T81	0	3	0	1
T83	0	0	0	1
T88	0	15	0	1
T104	0	3	0	0
T105	0	3	0	0
T106	0	3	0	0
T107	1198	0	0	0
T108	1151	0	0	0
T109	1285	0	0	0
T110	0	0	0	1
T111	0	0	0	1
T112	0	0	0	1

gen_edn_if_asserts[4].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217412720	217290855	0	0
T1	730	588	0	0
T2	1474	1413	0	0
T3	755	638	0	0
T4	1853	1729	0	0
T5	1568	1396	0	0
T14	2013	1838	0	0
T16	1342	1287	0	0
T19	1676	1581	0	0
T20	12915	12305	0	0
T21	1123	1057	0	0

gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217412720	127540	0	0
T1	730	421	0	0
T2	1474	0	0	0
T3	755	316	0	0
T4	1853	1174	0	0
T5	1568	699	0	0
T14	2013	1125	0	0
T15	0	6281	0	0
T16	1342	0	0	0
T19	1676	0	0	0
T20	12915	0	0	0
T21	1123	0	0	0
T27	0	15	0	0
T28	0	842	0	0
T52	0	290	0	0
T59	0	1110	0	0

gen_edn_if_asserts[5].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217412720	494179	0	0
T1	730	319	0	0
T2	1474	65	0	0
T3	755	235	0	0
T4	1853	1078	0	0
T5	1568	996	0	0
T14	2013	1184	0	0
T16	1342	20	0	0
T19	1676	1580	0	0
T20	12915	1929	0	0
T21	1123	85	0	0

gen_edn_if_asserts[5].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217412720	672	0	26
T7	2785	0	0	0
T26	728064	0	0	0
T32	767	0	0	0
T33	2402	0	0	0
T37	2319	3	0	0
T38	0	52	0	1
T42	0	59	0	1
T43	0	17	0	1
T46	0	37	0	1
T49	0	3	0	0
T50	689	0	0	0
T80	0	29	0	1
T83	0	0	0	1
T88	0	61	0	1
T100	9284	0	0	0
T101	19502	0	0	0
T102	580552	0	0	0
T111	0	0	0	1
T113	0	3	0	0
T114	0	3	0	0
T115	1219	0	0	0
T116	0	0	0	1
T117	0	0	0	1

gen_edn_if_asserts[5].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217412720	217290855	0	0
T1	730	588	0	0
T2	1474	1413	0	0
T3	755	638	0	0
T4	1853	1729	0	0
T5	1568	1396	0	0
T14	2013	1838	0	0
T16	1342	1287	0	0
T19	1676	1581	0	0
T20	12915	12305	0	0
T21	1123	1057	0	0

gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217412720	127540	0	0
T1	730	421	0	0
T2	1474	0	0	0
T3	755	316	0	0
T4	1853	1174	0	0
T5	1568	699	0	0
T14	2013	1125	0	0
T15	0	6281	0	0
T16	1342	0	0	0
T19	1676	0	0	0
T20	12915	0	0	0
T21	1123	0	0	0
T27	0	15	0	0
T28	0	842	0	0
T52	0	290	0	0
T59	0	1110	0	0

gen_edn_if_asserts[6].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217412720	494179	0	0
T1	730	319	0	0
T2	1474	65	0	0
T3	755	235	0	0
T4	1853	1078	0	0
T5	1568	996	0	0
T14	2013	1184	0	0
T16	1342	20	0	0
T19	1676	1580	0	0
T20	12915	1929	0	0
T21	1123	85	0	0

gen_edn_if_asserts[6].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217412720	441	0	15
T8	2409	3	0	0
T9	2288	0	0	0
T21	1123	3	0	0
T27	538	0	0	0
T28	1407	0	0	0
T39	0	3	0	0
T43	0	40	0	1
T46	0	11	0	1
T50	0	3	0	1
T51	1023	0	0	0
T52	711	0	0	0
T59	1908	0	0	0
T60	1026	0	0	0
T68	940	0	0	0
T83	0	0	0	1
T88	0	37	0	1
T111	0	0	0	1
T112	0	0	0	1
T118	0	3	0	0
T119	0	3	0	0
T120	0	3	0	0
T121	0	0	0	1
T122	0	0	0	1
T123	0	0	0	1

gen_edn_if_asserts[6].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217412720	217290855	0	0
T1	730	588	0	0
T2	1474	1413	0	0
T3	755	638	0	0
T4	1853	1729	0	0
T5	1568	1396	0	0
T14	2013	1838	0	0
T16	1342	1287	0	0
T19	1676	1581	0	0
T20	12915	12305	0	0
T21	1123	1057	0	0

gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	217412720	127540	0	0
T1	730	421	0	0
T2	1474	0	0	0
T3	755	316	0	0
T4	1853	1174	0	0
T5	1568	699	0	0
T14	2013	1125	0	0
T15	0	6281	0	0
T16	1342	0	0	0
T19	1676	0	0	0
T20	12915	0	0	0
T21	1123	0	0	0
T27	0	15	0	0
T28	0	842	0	0
T52	0	290	0	0
T59	0	1110	0	0