Unified Coverage Report :: Group :: tb.dut.u_edn_cov_if::edn_cs_cmds_cg

Group : tb.dut.u_edn_cov_if::edn_cs_cmds_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
51.47	51.47	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_edn_cov_0/edn_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
edn_cs_cmds_cg	51.47	1	100	1	64	64

---

Group Instance : edn_cs_cmds_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
51.47	1	100	1	64	64

---

Summary for Group Instance edn_cs_cmds_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	1	18	94.74
Crosses	49	32	17	34.69

Variables for Group Instance edn_cs_cmds_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_acmd	5	1	4	80.00	100	1	1	0
cp_clen	2	0	2	100.00	100	1	1	0
cp_cmd_src	5	0	5	100.00	100	1	1	0
cp_flags	2	0	2	100.00	100	1	1	0
cp_glen	2	0	2	100.00	100	1	1	0
cp_mode	3	0	3	100.00	100	1	1	0

Crosses for Group Instance edn_cs_cmds_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_generate_intended	13	9	4	30.77	100	1	1	0
cr_instantiate_intended	13	7	6	46.15	100	1	1	0
cr_reseed_intended	12	8	4	33.33	100	1	1	0
cr_update_intended	4	4	0	0.00	100	1	1	0
cr_uninstantiate_intended	2	1	1	50.00	100	1	1	0
cr_acmd_mode_cmd_src_unintended	5	3	2	40.00	100	1	1	0

Summary for Variable cp_acmd

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	1	4	80.00

Automatically Generated Bins for cp_acmd

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[UPD]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[INV]	0	Excluded
auto[GENB]	0	Excluded
auto[GENU]	0	Excluded
unused	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[INS]	4609	1			T19	1		T20	1		T21	1
auto[RES]	400	1			T19	3		T13	3		T14	3
auto[GEN]	4859	1			T19	3		T20	1		T21	1
auto[UNI]	4260	1			T20	1		T1	68		T2	68

---

Summary for Variable cp_clen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_clen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

some_cmd_data

4400

1

T19

3

T1

60

T2

60

no_cmd_data

9728

1

T19

4

T20

3

T21

2

---

Summary for Variable cp_cmd_src

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_cmd_src

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sw_cmd_req	13230	1			T19	1		T20	3		T21	2
reseed_cmd	400	1			T19	3		T13	3		T14	3
generate_cmd	400	1			T19	3		T13	3		T14	3
boot_gen_cmd	49	1			T12	1		T65	1		T62	1
boot_ins_cmd	49	1			T12	1		T65	1		T62	1

---

Summary for Variable cp_flags

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_flags

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

true

3849

1

T19

3

T20

1

T1

48

false

10279

1

T19

4

T20

2

T21

2

---

Summary for Variable cp_glen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_glen

Excluded/Illegal bins

NAME	COUNT	STATUS
zero	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

multiple

1949

1

T19

2

T1

24

T12

1

one

2609

1

T19

3

T20

1

T21

1

---

Summary for Variable cp_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sw_mode	12880	1			T20	3		T21	2		T1	204
boot_mode	98	1			T12	2		T65	2		T62	2
auto_mode	1050	1			T19	7		T13	7		T14	7

---

Summary for Cross cr_generate_intended

Samples crossed: cp_acmd cp_clen cp_glen cp_mode cp_cmd_src

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	13	9	4	30.77	9
Automatically Generated Cross Bins	13	9	4	30.77	9
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_generate_intended

Uncovered bins

cp_acmd	cp_clen	cp_glen	cp_mode	cp_cmd_src	COUNT	AT LEAST	NUMBER	STATUS
[auto[GEN]]	[some_cmd_data]	[multiple]	[sw_mode , boot_mode]	[sw_cmd_req]	--	--	2
[auto[GEN]]	[some_cmd_data]	[multiple]	[auto_mode]	[generate_cmd]	0	1	1
[auto[GEN]]	[some_cmd_data]	[one]	[sw_mode , boot_mode]	[sw_cmd_req]	--	--	2
[auto[GEN]]	[no_cmd_data]	[multiple]	[boot_mode]	[sw_cmd_req]	0	1	1
[auto[GEN]]	[no_cmd_data]	[multiple]	[boot_mode]	[boot_gen_cmd]	0	1	1
[auto[GEN]]	[no_cmd_data]	[multiple]	[auto_mode]	[generate_cmd]	0	1	1
[auto[GEN]]	[no_cmd_data]	[one]	[boot_mode]	[sw_cmd_req]	0	1	1

Excluded/Illegal bins

cp_acmd	cp_clen	cp_glen	cp_mode	cp_cmd_src	COUNT	STATUS
[auto[INV]]	[some_cmd_data , no_cmd_data]	[multiple , one]	[sw_mode , boot_mode , auto_mode]	[sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd]	--	Excluded	(60 bins)
[auto[GENB] , auto[GENU]]	[some_cmd_data , no_cmd_data]	[multiple , one]	[sw_mode , boot_mode , auto_mode]	[sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd]	--	Excluded	(120 bins)

Covered bins

cp_acmd

cp_clen

cp_glen

cp_mode

cp_cmd_src

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[GEN]

some_cmd_data

one

auto_mode

generate_cmd

300

1

T19

2

T13

2

T14

2

auto[GEN]

no_cmd_data

multiple

sw_mode

sw_cmd_req

50

1

T49

1

T51

1

T104

1

auto[GEN]

no_cmd_data

one

sw_mode

sw_cmd_req

2010

1

T20

1

T21

1

T1

32

auto[GEN]

no_cmd_data

one

auto_mode

generate_cmd

100

1

T19

1

T13

1

T14

1

User Defined Cross Bins for cr_generate_intended

Excluded/Illegal bins

NAME	COUNT	STATUS
not_gen	0	Excluded
gen_auto_wrong_src	0	Excluded
gen_boot_wrong_src	0	Excluded
gen_boot_seq_wrong_clen	0	Excluded
gen_boot_seq_wrong_glen	0	Excluded
gen_sw_wrong_src	0	Excluded

---

Summary for Cross cr_instantiate_intended

Samples crossed: cp_acmd cp_clen cp_flags cp_mode cp_cmd_src

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	13	7	6	46.15	7
Automatically Generated Cross Bins	13	7	6	46.15	7
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_instantiate_intended

Element holes

cp_acmd	cp_clen	cp_flags	cp_mode	cp_cmd_src	COUNT	AT LEAST	NUMBER	STATUS
[auto[INS]]	[some_cmd_data]	*	[boot_mode , auto_mode]	[sw_cmd_req]	--	--	4

Uncovered bins

cp_acmd	cp_clen	cp_flags	cp_mode	cp_cmd_src	COUNT	AT LEAST	NUMBER	STATUS
[auto[INS]]	[no_cmd_data]	[true]	[boot_mode]	[sw_cmd_req]	0	1	1
[auto[INS]]	[no_cmd_data]	[false]	[boot_mode]	[sw_cmd_req]	0	1	1
[auto[INS]]	[no_cmd_data]	[false]	[boot_mode]	[boot_ins_cmd]	0	1	1

Excluded/Illegal bins

cp_acmd	cp_clen	cp_flags	cp_mode	cp_cmd_src	COUNT	STATUS
[auto[INV]]	[some_cmd_data , no_cmd_data]	[true , false]	[sw_mode , boot_mode , auto_mode]	[sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd]	--	Excluded	(60 bins)
[auto[GENB] , auto[GENU]]	[some_cmd_data , no_cmd_data]	[true , false]	[sw_mode , boot_mode , auto_mode]	[sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd]	--	Excluded	(120 bins)

Covered bins

cp_acmd

cp_clen

cp_flags

cp_mode

cp_cmd_src

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[INS]

some_cmd_data

true

sw_mode

sw_cmd_req

1050

1

T1

15

T2

15

T3

15

auto[INS]

some_cmd_data

false

sw_mode

sw_cmd_req

950

1

T1

16

T2

16

T3

16

auto[INS]

no_cmd_data

true

sw_mode

sw_cmd_req

100

1

T1

2

T2

2

T3

2

auto[INS]

no_cmd_data

true

auto_mode

sw_cmd_req

50

1

T22

1

T23

1

T24

1

auto[INS]

no_cmd_data

false

sw_mode

sw_cmd_req

2210

1

T20

1

T21

1

T1

35

auto[INS]

no_cmd_data

false

auto_mode

sw_cmd_req

100

1

T19

1

T13

1

T14

1

User Defined Cross Bins for cr_instantiate_intended

Excluded/Illegal bins

NAME	COUNT	STATUS
not_ins	0	Excluded
ins_auto_wrong_src	0	Excluded
ins_boot_wrong_src	0	Excluded
ins_boot_seq_wrong_clen	0	Excluded
ins_boot_seq_wrong_flag0	0	Excluded
ins_sw_wrong_src	0	Excluded

---

Summary for Cross cr_reseed_intended

Samples crossed: cp_acmd cp_clen cp_flags cp_mode cp_cmd_src

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	12	8	4	33.33	8
Automatically Generated Cross Bins	12	8	4	33.33	8
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_reseed_intended

Element holes

cp_acmd	cp_clen	cp_flags	cp_mode	cp_cmd_src	COUNT	AT LEAST	NUMBER	STATUS
[auto[RES]]	*	*	[sw_mode , boot_mode]	[sw_cmd_req]	--	--	8

Excluded/Illegal bins

cp_acmd	cp_clen	cp_flags	cp_mode	cp_cmd_src	COUNT	STATUS
[auto[INV]]	[some_cmd_data , no_cmd_data]	[true , false]	[sw_mode , boot_mode , auto_mode]	[sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd]	--	Excluded	(60 bins)
[auto[GENB] , auto[GENU]]	[some_cmd_data , no_cmd_data]	[true , false]	[sw_mode , boot_mode , auto_mode]	[sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd]	--	Excluded	(120 bins)

Covered bins

cp_acmd

cp_clen

cp_flags

cp_mode

cp_cmd_src

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[RES]

some_cmd_data

true

auto_mode

reseed_cmd

50

1

T29

1

T30

1

T31

1

auto[RES]

some_cmd_data

false

auto_mode

reseed_cmd

150

1

T19

1

T13

1

T14

1

auto[RES]

no_cmd_data

true

auto_mode

reseed_cmd

100

1

T19

1

T13

1

T14

1

auto[RES]

no_cmd_data

false

auto_mode

reseed_cmd

100

1

T19

1

T13

1

T14

1

User Defined Cross Bins for cr_reseed_intended

Excluded/Illegal bins

NAME	COUNT	STATUS
not_res	0	Excluded
res_auto_wrong_src	0	Excluded
res_boot_wrong_src	0	Excluded
res_sw_wrong_src	0	Excluded

---

Summary for Cross cr_update_intended

Samples crossed: cp_acmd cp_clen cp_mode cp_cmd_src

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	4	0	0.00	4
Automatically Generated Cross Bins	4	4	0	0.00	4
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_update_intended

Element holes

cp_acmd	cp_clen	cp_mode	cp_cmd_src	COUNT	AT LEAST	NUMBER	STATUS
[auto[UPD]]	*	[sw_mode , boot_mode]	[sw_cmd_req]	--	--	4

Excluded/Illegal bins

cp_acmd	cp_clen	cp_mode	cp_cmd_src	COUNT	STATUS
[auto[INV]]	[some_cmd_data , no_cmd_data]	[sw_mode , boot_mode , auto_mode]	[sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd]	--	Excluded	(30 bins)
[auto[GENB] , auto[GENU]]	[some_cmd_data , no_cmd_data]	[sw_mode , boot_mode , auto_mode]	[sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd]	--	Excluded	(60 bins)

User Defined Cross Bins for cr_update_intended

Excluded/Illegal bins

NAME	COUNT	STATUS
not_upd	0	Excluded
upd_auto_wrong_src	0	Excluded
upd_boot_wrong_src	0	Excluded
upd_sw_wrong_src	0	Excluded

---

Summary for Cross cr_uninstantiate_intended

Samples crossed: cp_acmd cp_mode cp_cmd_src

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	2	1	1	50.00	1
Automatically Generated Cross Bins	2	1	1	50.00	1
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_uninstantiate_intended

Uncovered bins

cp_acmd	cp_mode	cp_cmd_src	COUNT	AT LEAST	NUMBER	STATUS
[auto[UNI]]	[boot_mode]	[sw_cmd_req]	0	1	1

Excluded/Illegal bins

cp_acmd	cp_mode	cp_cmd_src	COUNT	STATUS
[auto[INV]]	[sw_mode , boot_mode , auto_mode]	[sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd]	--	Excluded	(15 bins)
[auto[GENB] , auto[GENU]]	[sw_mode , boot_mode , auto_mode]	[sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd]	--	Excluded	(30 bins)

Covered bins

cp_acmd

cp_mode

cp_cmd_src

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[UNI]

sw_mode

sw_cmd_req

4260

1

T20

1

T1

68

T2

68

User Defined Cross Bins for cr_uninstantiate_intended

Excluded/Illegal bins

NAME	COUNT	STATUS
not_uni	0	Excluded
uni_auto_wrong_src	0	Excluded
uni_boot_wrong_src	0	Excluded
uni_sw_wrong_src	0	Excluded

---

Summary for Cross cr_acmd_mode_cmd_src_unintended

Samples crossed: cp_acmd cp_mode cp_cmd_src

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	5	3	2	40.00	3
Automatically Generated Cross Bins	5	3	2	40.00	3
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_acmd_mode_cmd_src_unintended

Uncovered bins

cp_acmd	cp_mode	cp_cmd_src	COUNT	AT LEAST	NUMBER	STATUS
[auto[RES]]	[auto_mode]	[sw_cmd_req]	0	1	1
[auto[UPD] , auto[UNI]]	[auto_mode]	[sw_cmd_req]	--	--	2

Excluded/Illegal bins

cp_acmd	cp_mode	cp_cmd_src	COUNT	STATUS
[auto[INV]]	[sw_mode , boot_mode , auto_mode]	[sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd]	--	Excluded	(15 bins)
[auto[GENB] , auto[GENU]]	[sw_mode , boot_mode , auto_mode]	[sw_cmd_req , reseed_cmd , generate_cmd , boot_gen_cmd , boot_ins_cmd]	--	Excluded	(30 bins)

Covered bins

cp_acmd

cp_mode

cp_cmd_src

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[INS]

auto_mode

sw_cmd_req

150

1

T19

1

T13

1

T14

1

auto[GEN]

auto_mode

sw_cmd_req

100

1

T22

2

T23

2

T24

2

User Defined Cross Bins for cr_acmd_mode_cmd_src_unintended

Excluded/Illegal bins

NAME	COUNT	STATUS
not_sw_cmd	0	Excluded
not_auto_mode	0	Excluded