Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd_cg

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
80.39	80.39	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	80.39	1	100	1	64	64

---

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
80.39	1	100	1	64	64

---

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	40	10	30	75.00

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	4	0	4	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	0	2	100.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	40	10	30	75.00	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
non_zero_bins[0]	2400	1			T1	33		T2	33		T3	33
non_zero_bins[1]	1850	1			T19	1		T1	27		T2	27
zero	9476	1			T19	1		T20	3		T21	2

---

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
uni	4260	1			T20	1		T1	68		T2	68
gen	4708	1			T19	1		T20	1		T21	1
res	150	1			T29	3		T30	3		T31	3
ins	4608	1			T19	1		T20	1		T21	1

---

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

9978

1

T19

1

T20

2

T21

2

mubi_true

3748

1

T19

1

T20

1

T1

48

---

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fail

7926

1

T19

2

T20

3

T21

2

pass

5800

1

T1

96

T2

96

T3

96

---

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	40	10	30	75.00	10
Automatically Generated Cross Bins	40	10	30	75.00	10
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Element holes

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[res]	[non_zero_bins[0]]	*	*	--	--	4
[res]	[non_zero_bins[1]]	*	[mubi_false]	--	--	2
[res]	[zero]	*	*	--	--	4

Covered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
uni	zero	fail	mubi_false	1760	1			T1	28		T2	28		T46	1
uni	zero	fail	mubi_true	550	1			T20	1		T1	8		T2	8
uni	zero	pass	mubi_false	1450	1			T1	23		T2	23		T3	23
uni	zero	pass	mubi_true	500	1			T1	9		T2	9		T3	9
gen	non_zero_bins[0]	fail	mubi_false	500	1			T1	7		T2	7		T3	7
gen	non_zero_bins[0]	fail	mubi_true	100	1			T1	2		T2	2		T3	2
gen	non_zero_bins[0]	pass	mubi_false	200	1			T1	4		T2	4		T3	4
gen	non_zero_bins[0]	pass	mubi_true	350	1			T1	4		T2	4		T3	4
gen	non_zero_bins[1]	fail	mubi_false	350	1			T1	5		T2	5		T3	5
gen	non_zero_bins[1]	fail	mubi_true	300	1			T19	1		T1	3		T2	3
gen	non_zero_bins[1]	pass	mubi_false	200	1			T1	4		T2	4		T3	4
gen	non_zero_bins[1]	pass	mubi_true	50	1			T29	1		T30	1		T31	1
gen	zero	fail	mubi_false	1308	1			T20	1		T21	1		T1	17
gen	zero	fail	mubi_true	350	1			T1	4		T2	4		T3	4
gen	zero	pass	mubi_false	950	1			T1	17		T2	17		T3	17
gen	zero	pass	mubi_true	50	1			T1	1		T2	1		T3	1
res	non_zero_bins[1]	fail	mubi_true	100	1			T29	2		T30	2		T31	2
res	non_zero_bins[1]	pass	mubi_true	50	1			T29	1		T30	1		T31	1
ins	non_zero_bins[0]	fail	mubi_false	200	1			T1	2		T2	2		T3	2
ins	non_zero_bins[0]	fail	mubi_true	550	1			T1	6		T2	6		T3	6
ins	non_zero_bins[0]	pass	mubi_false	300	1			T1	5		T2	5		T3	5
ins	non_zero_bins[0]	pass	mubi_true	200	1			T1	3		T2	3		T3	3
ins	non_zero_bins[1]	fail	mubi_false	150	1			T1	3		T2	3		T3	3
ins	non_zero_bins[1]	fail	mubi_true	250	1			T1	4		T2	4		T3	4
ins	non_zero_bins[1]	pass	mubi_false	300	1			T1	6		T2	6		T3	6
ins	non_zero_bins[1]	pass	mubi_true	100	1			T1	2		T2	2		T3	2
ins	zero	fail	mubi_false	1260	1			T19	1		T20	1		T21	1
ins	zero	fail	mubi_true	198	1			T1	1		T12	2		T2	1
ins	zero	pass	mubi_false	1050	1			T1	17		T2	17		T3	17
ins	zero	pass	mubi_true	50	1			T1	1		T2	1		T3	1

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded