Summary for Variable csrng_glen
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
2 |
2 |
50.00 |
User Defined Bins for csrng_glen
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
glens[1] |
0 |
1 |
1 |
|
glens[2] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
glens[0] |
2408 |
1 |
|
|
T19 |
1 |
|
T20 |
1 |
|
T21 |
1 |
glens[3] |
50 |
1 |
|
|
T49 |
1 |
|
T51 |
1 |
|
T104 |
1 |
Summary for Variable csrng_sts
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for csrng_sts
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
fail |
2908 |
1 |
|
|
T19 |
1 |
|
T20 |
1 |
|
T21 |
1 |
pass |
1800 |
1 |
|
|
T1 |
30 |
|
T2 |
30 |
|
T3 |
30 |
Summary for Cross csrng_genbits_cross
Samples crossed: csrng_glen csrng_sts
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
5 |
3 |
37.50 |
5 |
Automatically Generated Cross Bins for csrng_genbits_cross
Element holes
csrng_glen | csrng_sts | COUNT | AT LEAST | NUMBER | STATUS |
[glens[1] , glens[2]] |
* |
-- |
-- |
4 |
|
Uncovered bins
csrng_glen | csrng_sts | COUNT | AT LEAST | NUMBER | STATUS |
[glens[3]] |
[pass] |
0 |
1 |
1 |
|
Covered bins
csrng_glen | csrng_sts | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
glens[0] |
fail |
1458 |
1 |
|
|
T19 |
1 |
|
T20 |
1 |
|
T21 |
1 |
glens[0] |
pass |
950 |
1 |
|
|
T1 |
16 |
|
T2 |
16 |
|
T3 |
16 |
glens[3] |
fail |
50 |
1 |
|
|
T49 |
1 |
|
T51 |
1 |
|
T104 |
1 |