Unified Coverage Report :: Module :: edn_main_sm

Module : edn_main_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.21	98.18	100.00		48.15	94.74	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_edn_main_sm	88.21	98.18	100.00		48.15	94.74	100.00

---

Module Instance : tb.dut.u_edn_core.u_edn_main_sm

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.21	98.18	100.00		48.15	94.74	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.29	98.32	100.00		48.15	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
90.02	100.00	75.70			94.37		u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
TOTAL		110	108	98.18
ALWAYS	62	3	3	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	66	1	1	100.00
ALWAYS	70	105	103	98.10

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
62	3	3
64	1	1
66	1	1
70	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
77	1	1
78	1	1
79	1	1
80	1	1
81	1	1
82	1	1
83	1	1
84	1	1
85	1	1
87	1	1
88	1	1
89	1	1
90	1	1
91	1	1
92	1	1
93	1	1
			MISSING_ELSE
97	1	1
98	1	1
101	1	1
102	1	1
105	1	1
106	1	1
			MISSING_ELSE
110	1	1
111	1	1
114	1	1
115	1	1
116	1	1
			==> MISSING_ELSE
120	1	1
121	1	1
			MISSING_ELSE
125	1	1
126	1	1
132	1	1
133	1	1
134	1	1
135	1	1
			MISSING_ELSE
139	1	1
140	1	1
141	1	1
142	1	1
			MISSING_ELSE
146	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
153	1	1
154	1	1
155	1	1
156	0	1
157	0	1
159	1	1
160	1	1
162	1	1
167	1	1
168	1	1
169	1	1
170	1	1
173	1	1
174	1	1
175	1	1
176	1	1
177	1	1
			MISSING_ELSE
181	1	1
182	1	1
183	1	1
184	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
			MISSING_ELSE
197	1	1
205	1	1
206	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
229	1	1
231	1	1
232	1	1
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_main_sm

	Total	Covered	Percent
Conditions	22	22	100.00
Logical	22	22	100.00
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION ((state_q != Idle) && (state_q != BootPulse) && (state_q != BootDone) && (state_q != SWPortMode))
             --------1--------    -----------2----------    ----------3----------    -----------4-----------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T19,T20,T21
1	0	1	1	Covered	T12,T65,T62
1	1	0	1	Covered	T12,T65,T62
1	1	1	0	Covered	T20,T21,T1
1	1	1	1	Covered	T19,T21,T11

 LINE       66
 SUB-EXPRESSION (state_q != Idle)
                --------1--------

-1-	Status	Tests
0	Covered	T19,T20,T21
1	Covered	T19,T20,T21

 LINE       66
 SUB-EXPRESSION (state_q != BootPulse)
                -----------1----------

-1-	Status	Tests
0	Covered	T19,T20,T21
1	Covered	T19,T20,T21

 LINE       66
 SUB-EXPRESSION (state_q != BootDone)
                ----------1----------

-1-	Status	Tests
0	Covered	T19,T20,T21
1	Covered	T19,T20,T21

 LINE       66
 SUB-EXPRESSION (state_q != SWPortMode)
                -----------1-----------

-1-	Status	Tests
0	Covered	T19,T20,T21
1	Covered	T19,T20,T21

 LINE       87
 EXPRESSION (boot_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T19,T20,T21
1	0	Covered	T12,T65,T62
1	1	Covered	T12,T65,T62

 LINE       89
 EXPRESSION (auto_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T20,T21,T1
1	0	Covered	T29,T30,T31
1	1	Covered	T19,T13,T14

 LINE       220
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_i)) && 
      2  (state_q inside {BootLoadIns, BootLoadGen, BootInsAckWait, BootCaptGenCnt, BootSendGenCmd, BootGenAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode}))

-1-	-2-	Status	Tests
0	1	Covered	T19,T20,T21
1	0	Covered	T19,T20,T21
1	1	Covered	T12,T65,T29

---

FSM Coverage for Module : edn_main_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	19	19	100.00	(Not included in score)
Transitions	54	26	48.15
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AutoAckWait	177	Covered	T19,T13,T14
AutoCaptGenCnt	162	Covered	T19,T13,T14
AutoCaptReseedCnt	160	Covered	T19,T13,T14
AutoDispatch	142	Covered	T19,T13,T14
AutoFirstAckWait	135	Covered	T19,T13,T14
AutoLoadIns	90	Covered	T19,T13,T14
AutoSendGenCmd	170	Covered	T19,T13,T14
AutoSendReseedCmd	184	Covered	T29,T30,T31
BootCaptGenCnt	106	Covered	T12,T65,T62
BootDone	126	Covered	T12,T65,T62
BootGenAckWait	116	Covered	T12,T65,T62
BootInsAckWait	102	Covered	T12,T65,T62
BootLoadGen	98	Covered	T12,T65,T62
BootLoadIns	88	Covered	T12,T65,T62
BootPulse	121	Covered	T12,T65,T62
BootSendGenCmd	111	Covered	T12,T65,T62
Error	206	Covered	T19,T21,T11
Idle	157	Covered	T19,T20,T21
SWPortMode	93	Covered	T20,T21,T1

transitions	Line No.	Covered	Tests
AutoAckWait->AutoDispatch	149	Covered	T19,T13,T14
AutoAckWait->Error	206	Not Covered
AutoAckWait->Idle	229	Covered	T29,T30,T31
AutoCaptGenCnt->AutoSendGenCmd	170	Covered	T19,T13,T14
AutoCaptGenCnt->Error	206	Not Covered
AutoCaptGenCnt->Idle	229	Not Covered
AutoCaptReseedCnt->AutoSendReseedCmd	184	Covered	T29,T30,T31
AutoCaptReseedCnt->Error	206	Covered	T19,T13,T14
AutoCaptReseedCnt->Idle	229	Not Covered
AutoDispatch->AutoCaptGenCnt	162	Covered	T19,T13,T14
AutoDispatch->AutoCaptReseedCnt	160	Covered	T19,T13,T14
AutoDispatch->Error	206	Not Covered
AutoDispatch->Idle	157	Not Covered
AutoFirstAckWait->AutoDispatch	142	Covered	T19,T13,T14
AutoFirstAckWait->Error	206	Not Covered
AutoFirstAckWait->Idle	229	Covered	T29,T30,T31
AutoLoadIns->AutoFirstAckWait	135	Covered	T19,T13,T14
AutoLoadIns->Error	206	Not Covered
AutoLoadIns->Idle	229	Not Covered
AutoSendGenCmd->AutoAckWait	177	Covered	T19,T13,T14
AutoSendGenCmd->Error	206	Not Covered
AutoSendGenCmd->Idle	229	Not Covered
AutoSendReseedCmd->AutoAckWait	191	Covered	T29,T30,T31
AutoSendReseedCmd->Error	206	Not Covered
AutoSendReseedCmd->Idle	229	Not Covered
BootCaptGenCnt->BootSendGenCmd	111	Covered	T12,T65,T62
BootCaptGenCnt->Error	206	Not Covered
BootCaptGenCnt->Idle	229	Not Covered
BootDone->Error	206	Not Covered
BootDone->Idle	229	Not Covered
BootGenAckWait->BootPulse	121	Covered	T12,T65,T62
BootGenAckWait->Error	206	Not Covered
BootGenAckWait->Idle	229	Not Covered
BootInsAckWait->BootCaptGenCnt	106	Covered	T12,T65,T62
BootInsAckWait->Error	206	Not Covered
BootInsAckWait->Idle	229	Not Covered
BootLoadGen->BootInsAckWait	102	Covered	T12,T65,T62
BootLoadGen->Error	206	Not Covered
BootLoadGen->Idle	229	Not Covered
BootLoadIns->BootLoadGen	98	Covered	T12,T65,T62
BootLoadIns->Error	206	Not Covered
BootLoadIns->Idle	229	Not Covered
BootPulse->BootDone	126	Covered	T12,T65,T62
BootPulse->Error	206	Not Covered
BootPulse->Idle	229	Covered	T12,T65,T62
BootSendGenCmd->BootGenAckWait	116	Covered	T12,T65,T62
BootSendGenCmd->Error	206	Not Covered
BootSendGenCmd->Idle	229	Not Covered
Idle->AutoLoadIns	90	Covered	T19,T13,T14
Idle->BootLoadIns	88	Covered	T12,T65,T62
Idle->Error	206	Covered	T25,T26,T27
Idle->SWPortMode	93	Covered	T20,T21,T1
SWPortMode->Error	206	Covered	T21,T11,T15
SWPortMode->Idle	229	Covered	T1,T2,T3

---

Branch Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
Branches		38	36	94.74
IF	62	2	2	100.00
CASE	85	33	31	93.94
IF	205	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	62	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T19,T20,T21
0	Covered	T19,T20,T21

	LineNo.	Expression
-1-:	85	case (state_q)
-2-:	87	if ((boot_req_mode_i && edn_enable_i))
-3-:	89	if ((auto_req_mode_i && edn_enable_i))
-4-:	91	if (edn_enable_i)
-5-:	105	if (csrng_cmd_ack_i)
-6-:	115	if (cmd_sent_i)
-7-:	120	if (csrng_cmd_ack_i)
-8-:	134	if (sw_cmd_req_load_i)
-9-:	140	if (csrng_cmd_ack_i)
-10-:	148	if (csrng_cmd_ack_i)
-11-:	155	if ((!auto_req_mode_i))
-12-:	159	if (max_reqs_cnt_zero_i)
-13-:	176	if (cmd_sent_i)
-14-:	190	if (cmd_sent_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
Idle	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T65,T62
Idle	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T19,T13,T14
Idle	0	0	1	-	-	-	-	-	-	-	-	-	-	Covered	T20,T21,T1
Idle	0	0	0	-	-	-	-	-	-	-	-	-	-	Covered	T19,T20,T21
BootLoadIns	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T65,T62
BootLoadGen	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T65,T62
BootInsAckWait	-	-	-	1	-	-	-	-	-	-	-	-	-	Covered	T12,T65,T62
BootInsAckWait	-	-	-	0	-	-	-	-	-	-	-	-	-	Covered	T12,T65,T62
BootCaptGenCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T65,T62
BootSendGenCmd	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T12,T65,T62
BootSendGenCmd	-	-	-	-	0	-	-	-	-	-	-	-	-	Not Covered
BootGenAckWait	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T12,T65,T62
BootGenAckWait	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T12,T65,T62
BootPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T65,T62
BootDone	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T65,T62
AutoLoadIns	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T19,T13,T14
AutoLoadIns	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T19,T13,T14
AutoFirstAckWait	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T19,T13,T14
AutoFirstAckWait	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T19,T13,T14
AutoAckWait	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T19,T13,T14
AutoAckWait	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T19,T13,T14
AutoDispatch	-	-	-	-	-	-	-	-	-	1	-	-	-	Not Covered
AutoDispatch	-	-	-	-	-	-	-	-	-	0	1	-	-	Covered	T19,T13,T14
AutoDispatch	-	-	-	-	-	-	-	-	-	0	0	-	-	Covered	T19,T13,T14
AutoCaptGenCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T19,T13,T14
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T19,T13,T14
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T19,T13,T14
AutoCaptReseedCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T19,T13,T14
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T29,T30,T31
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T29,T30,T31
SWPortMode	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T20,T21,T1
Error	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T19,T21,T11
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T25,T26,T27

	LineNo.	Expression
-1-:	205	if (local_escalate_i)
-2-:	220	if (((!edn_enable_i) && (state_q inside {BootLoadIns, BootLoadGen, BootInsAckWait, BootCaptGenCnt, BootSendGenCmd, BootGenAckWait, BootPulse, BootDone, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T19,T21,T11
0	1	Covered	T12,T65,T29
0	0	Covered	T19,T20,T21

---

Assert Coverage for Module : edn_main_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ErrorStStable_A	209958707	136825	0	0
FpvSecCmErrorStEscalate_A	209958707	137875	0	0
u_state_regs_A	209934507	209771407	0	0

ErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209958707	136825	0	0
T1	417033	0	0	0
T2	417033	0	0	0
T11	1073	588	0	0
T12	958	0	0	0
T13	985	440	0	0
T14	985	440	0	0
T15	0	588	0	0
T16	0	588	0	0
T19	985	440	0	0
T20	1044	0	0	0
T21	1073	588	0	0
T28	1593	0	0	0
T32	0	588	0	0
T52	0	440	0	0
T53	0	440	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209958707	137875	0	0
T1	417033	0	0	0
T2	417033	0	0	0
T11	1073	589	0	0
T12	958	0	0	0
T13	985	441	0	0
T14	985	441	0	0
T15	0	589	0	0
T16	0	589	0	0
T19	985	441	0	0
T20	1044	0	0	0
T21	1073	589	0	0
T28	1593	0	0	0
T32	0	589	0	0
T52	0	441	0	0
T53	0	441	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209934507	209771407	0	0
T1	417033	417022	0	0
T2	417033	417022	0	0
T11	961	818	0	0
T12	958	898	0	0
T13	799	644	0	0
T14	799	644	0	0
T19	799	644	0	0
T20	1044	982	0	0
T21	961	818	0	0
T28	1593	1531	0	0