Unified Coverage Report :: Module :: edn_ack_sm

Module : edn_ack_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.86	100.00	100.00		64.29	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep	77.95	78.12	100.00		42.86	68.75	100.00
tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep	77.95	78.12	100.00		42.86	68.75	100.00
tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep	77.95	78.12	100.00		42.86	68.75	100.00
tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep	77.95	78.12	100.00		42.86	68.75	100.00
tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep	92.86	100.00	100.00		64.29	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep	92.86	100.00	100.00		64.29	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep	92.86	100.00	100.00		64.29	100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
77.95	78.12	100.00		42.86	68.75	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.60	82.93	100.00		42.86	72.22	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
90.02	100.00	75.70			94.37		u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
77.95	78.12	100.00		42.86	68.75	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.60	82.93	100.00		42.86	72.22	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
90.02	100.00	75.70			94.37		u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
77.95	78.12	100.00		42.86	68.75	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.60	82.93	100.00		42.86	72.22	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
90.02	100.00	75.70			94.37		u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
77.95	78.12	100.00		42.86	68.75	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
79.60	82.93	100.00		42.86	72.22	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
90.02	100.00	75.70			94.37		u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.86	100.00	100.00		64.29	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.86	100.00	100.00		64.29	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
90.02	100.00	75.70			94.37		u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.86	100.00	100.00		64.29	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.86	100.00	100.00		64.29	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
90.02	100.00	75.70			94.37		u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.86	100.00	100.00		64.29	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.86	100.00	100.00		64.29	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
90.02	100.00	75.70			94.37		u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_ack_sm

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T19,T20,T21
1	0	Covered	T19,T20,T21
1	1	Covered	T12,T65,T29

---

FSM Coverage for Module : edn_ack_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	9	64.29
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T19,T20,T21
DataWait	75	Covered	T19,T20,T21
Disabled	107	Covered	T19,T20,T21
EndPointClear	63	Covered	T19,T20,T21
Error	99	Covered	T19,T21,T11
Idle	68	Covered	T19,T20,T21

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T19,T20,T21
DataWait->AckPls	80	Covered	T19,T20,T21
DataWait->Disabled	107	Not Covered
DataWait->Error	99	Not Covered
Disabled->EndPointClear	63	Covered	T19,T20,T21
Disabled->Error	99	Covered	T25,T26,T27
EndPointClear->Disabled	107	Not Covered
EndPointClear->Error	99	Covered	T25,T26,T27
EndPointClear->Idle	68	Covered	T19,T20,T21
Idle->DataWait	75	Covered	T19,T20,T21
Idle->Disabled	107	Covered	T1,T12,T2
Idle->Error	99	Covered	T19,T21,T11

---

Branch Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T19,T20,T21
0	Covered	T19,T20,T21

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T19,T20,T21
Disabled	0	-	-	-	Covered	T19,T20,T21
EndPointClear	-	-	-	-	Covered	T19,T20,T21
Idle	-	1	1	-	Covered	T19,T20,T21
Idle	-	1	0	-	Covered	T19,T20,T21
Idle	-	0	-	-	Covered	T19,T20,T21
DataWait	-	-	-	1	Covered	T19,T20,T21
DataWait	-	-	-	0	Covered	T19,T20,T1
AckPls	-	-	-	-	Covered	T19,T20,T21
Error	-	-	-	-	Covered	T19,T21,T11
default	-	-	-	-	Covered	T19,T13,T14

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T19,T21,T11
0	1	Covered	T12,T65,T29
0	0	Covered	T19,T20,T21

---

Assert Coverage for Module : edn_ack_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	1469710949	952775	0	0
FpvSecCmErrorStEscalate_A	1469710949	960125	0	0
u_state_regs_A	1469686749	1468545049	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1469710949	952775	0	0
T1	2919231	0	0	0
T2	2919231	0	0	0
T11	7511	4116	0	0
T12	6706	0	0	0
T13	6895	3030	0	0
T14	6895	3030	0	0
T15	0	4116	0	0
T16	0	4116	0	0
T19	6895	3030	0	0
T20	7308	0	0	0
T21	7511	4116	0	0
T28	11151	0	0	0
T32	0	4116	0	0
T52	0	3030	0	0
T53	0	3030	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1469710949	960125	0	0
T1	2919231	0	0	0
T2	2919231	0	0	0
T11	7511	4123	0	0
T12	6706	0	0	0
T13	6895	3037	0	0
T14	6895	3037	0	0
T15	0	4123	0	0
T16	0	4123	0	0
T19	6895	3037	0	0
T20	7308	0	0	0
T21	7511	4123	0	0
T28	11151	0	0	0
T32	0	4123	0	0
T52	0	3037	0	0
T53	0	3037	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1469686749	1468545049	0	0
T1	2919231	2919154	0	0
T2	2919231	2919154	0	0
T11	7399	6398	0	0
T12	6706	6286	0	0
T13	6709	5624	0	0
T14	6709	5624	0	0
T19	6709	5624	0	0
T20	7308	6874	0	0
T21	7399	6398	0	0
T28	11151	10717	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	25	78.12
ALWAYS	52	3	3	100.00
ALWAYS	55	29	22	75.86

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	0	1
73	0	1
			==> MISSING_ELSE
75	0	1
			MISSING_ELSE
79	0	1
80	0	1
			==> MISSING_ELSE
84	0	1
85	0	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T19,T20,T21
1	0	Covered	T19,T20,T21
1	1	Covered	T12,T65,T29

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	4	66.67	(Not included in score)
Transitions	14	6	42.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Not Covered
DataWait	75	Not Covered
Disabled	107	Covered	T19,T20,T21
EndPointClear	63	Covered	T19,T20,T21
Error	99	Covered	T19,T21,T11
Idle	68	Covered	T19,T20,T21

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Not Covered
DataWait->AckPls	80	Not Covered
DataWait->Disabled	107	Not Covered
DataWait->Error	99	Not Covered
Disabled->EndPointClear	63	Covered	T19,T20,T21
Disabled->Error	99	Covered	T25,T26,T27
EndPointClear->Disabled	107	Not Covered
EndPointClear->Error	99	Covered	T25,T26,T27
EndPointClear->Idle	68	Covered	T19,T20,T21
Idle->DataWait	75	Not Covered
Idle->Disabled	107	Covered	T1,T12,T2
Idle->Error	99	Covered	T19,T21,T11

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	11	68.75
IF	52	2	2	100.00
CASE	60	11	6	54.55
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T19,T20,T21
0	Covered	T19,T20,T21

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T19,T20,T21
Disabled	0	-	-	-	Covered	T19,T20,T21
EndPointClear	-	-	-	-	Covered	T19,T20,T21
Idle	-	1	1	-	Not Covered
Idle	-	1	0	-	Not Covered
Idle	-	0	-	-	Covered	T19,T20,T21
DataWait	-	-	-	1	Not Covered
DataWait	-	-	-	0	Not Covered
AckPls	-	-	-	-	Not Covered
Error	-	-	-	-	Covered	T19,T21,T11
default	-	-	-	-	Covered	T25,T26,T27

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T19,T21,T11
0	1	Covered	T12,T65,T29
0	0	Covered	T19,T20,T21

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	209958707	136825	0	0
FpvSecCmErrorStEscalate_A	209958707	137875	0	0
u_state_regs_A	209958707	209795607	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209958707	136825	0	0
T1	417033	0	0	0
T2	417033	0	0	0
T11	1073	588	0	0
T12	958	0	0	0
T13	985	440	0	0
T14	985	440	0	0
T15	0	588	0	0
T16	0	588	0	0
T19	985	440	0	0
T20	1044	0	0	0
T21	1073	588	0	0
T28	1593	0	0	0
T32	0	588	0	0
T52	0	440	0	0
T53	0	440	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209958707	137875	0	0
T1	417033	0	0	0
T2	417033	0	0	0
T11	1073	589	0	0
T12	958	0	0	0
T13	985	441	0	0
T14	985	441	0	0
T15	0	589	0	0
T16	0	589	0	0
T19	985	441	0	0
T20	1044	0	0	0
T21	1073	589	0	0
T28	1593	0	0	0
T32	0	589	0	0
T52	0	441	0	0
T53	0	441	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209958707	209795607	0	0
T1	417033	417022	0	0
T2	417033	417022	0	0
T11	1073	930	0	0
T12	958	898	0	0
T13	985	830	0	0
T14	985	830	0	0
T19	985	830	0	0
T20	1044	982	0	0
T21	1073	930	0	0
T28	1593	1531	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	25	78.12
ALWAYS	52	3	3	100.00
ALWAYS	55	29	22	75.86

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	0	1
73	0	1
			==> MISSING_ELSE
75	0	1
			MISSING_ELSE
79	0	1
80	0	1
			==> MISSING_ELSE
84	0	1
85	0	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T19,T20,T21
1	0	Covered	T19,T20,T21
1	1	Covered	T12,T65,T29

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	4	66.67	(Not included in score)
Transitions	14	6	42.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Not Covered
DataWait	75	Not Covered
Disabled	107	Covered	T19,T20,T21
EndPointClear	63	Covered	T19,T20,T21
Error	99	Covered	T19,T21,T11
Idle	68	Covered	T19,T20,T21

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Not Covered
DataWait->AckPls	80	Not Covered
DataWait->Disabled	107	Not Covered
DataWait->Error	99	Not Covered
Disabled->EndPointClear	63	Covered	T19,T20,T21
Disabled->Error	99	Covered	T25,T26,T27
EndPointClear->Disabled	107	Not Covered
EndPointClear->Error	99	Covered	T25,T26,T27
EndPointClear->Idle	68	Covered	T19,T20,T21
Idle->DataWait	75	Not Covered
Idle->Disabled	107	Covered	T1,T12,T2
Idle->Error	99	Covered	T19,T21,T11

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	11	68.75
IF	52	2	2	100.00
CASE	60	11	6	54.55
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T19,T20,T21
0	Covered	T19,T20,T21

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T19,T20,T21
Disabled	0	-	-	-	Covered	T19,T20,T21
EndPointClear	-	-	-	-	Covered	T19,T20,T21
Idle	-	1	1	-	Not Covered
Idle	-	1	0	-	Not Covered
Idle	-	0	-	-	Covered	T19,T20,T21
DataWait	-	-	-	1	Not Covered
DataWait	-	-	-	0	Not Covered
AckPls	-	-	-	-	Not Covered
Error	-	-	-	-	Covered	T19,T21,T11
default	-	-	-	-	Covered	T25,T26,T27

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T19,T21,T11
0	1	Covered	T12,T65,T29
0	0	Covered	T19,T20,T21

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	209958707	136825	0	0
FpvSecCmErrorStEscalate_A	209958707	137875	0	0
u_state_regs_A	209958707	209795607	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209958707	136825	0	0
T1	417033	0	0	0
T2	417033	0	0	0
T11	1073	588	0	0
T12	958	0	0	0
T13	985	440	0	0
T14	985	440	0	0
T15	0	588	0	0
T16	0	588	0	0
T19	985	440	0	0
T20	1044	0	0	0
T21	1073	588	0	0
T28	1593	0	0	0
T32	0	588	0	0
T52	0	440	0	0
T53	0	440	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209958707	137875	0	0
T1	417033	0	0	0
T2	417033	0	0	0
T11	1073	589	0	0
T12	958	0	0	0
T13	985	441	0	0
T14	985	441	0	0
T15	0	589	0	0
T16	0	589	0	0
T19	985	441	0	0
T20	1044	0	0	0
T21	1073	589	0	0
T28	1593	0	0	0
T32	0	589	0	0
T52	0	441	0	0
T53	0	441	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209958707	209795607	0	0
T1	417033	417022	0	0
T2	417033	417022	0	0
T11	1073	930	0	0
T12	958	898	0	0
T13	985	830	0	0
T14	985	830	0	0
T19	985	830	0	0
T20	1044	982	0	0
T21	1073	930	0	0
T28	1593	1531	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	25	78.12
ALWAYS	52	3	3	100.00
ALWAYS	55	29	22	75.86

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	0	1
73	0	1
			==> MISSING_ELSE
75	0	1
			MISSING_ELSE
79	0	1
80	0	1
			==> MISSING_ELSE
84	0	1
85	0	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T19,T20,T21
1	0	Covered	T19,T20,T21
1	1	Covered	T12,T65,T29

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	4	66.67	(Not included in score)
Transitions	14	6	42.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Not Covered
DataWait	75	Not Covered
Disabled	107	Covered	T19,T20,T21
EndPointClear	63	Covered	T19,T20,T21
Error	99	Covered	T19,T21,T11
Idle	68	Covered	T19,T20,T21

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Not Covered
DataWait->AckPls	80	Not Covered
DataWait->Disabled	107	Not Covered
DataWait->Error	99	Not Covered
Disabled->EndPointClear	63	Covered	T19,T20,T21
Disabled->Error	99	Covered	T25,T26,T27
EndPointClear->Disabled	107	Not Covered
EndPointClear->Error	99	Covered	T25,T26,T27
EndPointClear->Idle	68	Covered	T19,T20,T21
Idle->DataWait	75	Not Covered
Idle->Disabled	107	Covered	T1,T12,T2
Idle->Error	99	Covered	T19,T21,T11

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	11	68.75
IF	52	2	2	100.00
CASE	60	11	6	54.55
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T19,T20,T21
0	Covered	T19,T20,T21

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T19,T20,T21
Disabled	0	-	-	-	Covered	T19,T20,T21
EndPointClear	-	-	-	-	Covered	T19,T20,T21
Idle	-	1	1	-	Not Covered
Idle	-	1	0	-	Not Covered
Idle	-	0	-	-	Covered	T19,T20,T21
DataWait	-	-	-	1	Not Covered
DataWait	-	-	-	0	Not Covered
AckPls	-	-	-	-	Not Covered
Error	-	-	-	-	Covered	T19,T21,T11
default	-	-	-	-	Covered	T25,T26,T27

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T19,T21,T11
0	1	Covered	T12,T65,T29
0	0	Covered	T19,T20,T21

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	209958707	136825	0	0
FpvSecCmErrorStEscalate_A	209958707	137875	0	0
u_state_regs_A	209958707	209795607	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209958707	136825	0	0
T1	417033	0	0	0
T2	417033	0	0	0
T11	1073	588	0	0
T12	958	0	0	0
T13	985	440	0	0
T14	985	440	0	0
T15	0	588	0	0
T16	0	588	0	0
T19	985	440	0	0
T20	1044	0	0	0
T21	1073	588	0	0
T28	1593	0	0	0
T32	0	588	0	0
T52	0	440	0	0
T53	0	440	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209958707	137875	0	0
T1	417033	0	0	0
T2	417033	0	0	0
T11	1073	589	0	0
T12	958	0	0	0
T13	985	441	0	0
T14	985	441	0	0
T15	0	589	0	0
T16	0	589	0	0
T19	985	441	0	0
T20	1044	0	0	0
T21	1073	589	0	0
T28	1593	0	0	0
T32	0	589	0	0
T52	0	441	0	0
T53	0	441	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209958707	209795607	0	0
T1	417033	417022	0	0
T2	417033	417022	0	0
T11	1073	930	0	0
T12	958	898	0	0
T13	985	830	0	0
T14	985	830	0	0
T19	985	830	0	0
T20	1044	982	0	0
T21	1073	930	0	0
T28	1593	1531	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	25	78.12
ALWAYS	52	3	3	100.00
ALWAYS	55	29	22	75.86

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	0	1
73	0	1
			==> MISSING_ELSE
75	0	1
			MISSING_ELSE
79	0	1
80	0	1
			==> MISSING_ELSE
84	0	1
85	0	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T19,T20,T21
1	0	Covered	T19,T20,T21
1	1	Covered	T12,T65,T29

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	4	66.67	(Not included in score)
Transitions	14	6	42.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Not Covered
DataWait	75	Not Covered
Disabled	107	Covered	T19,T20,T21
EndPointClear	63	Covered	T19,T20,T21
Error	99	Covered	T19,T21,T11
Idle	68	Covered	T19,T20,T21

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Not Covered
DataWait->AckPls	80	Not Covered
DataWait->Disabled	107	Not Covered
DataWait->Error	99	Not Covered
Disabled->EndPointClear	63	Covered	T19,T20,T21
Disabled->Error	99	Covered	T25,T26,T27
EndPointClear->Disabled	107	Not Covered
EndPointClear->Error	99	Covered	T25,T26,T27
EndPointClear->Idle	68	Covered	T19,T20,T21
Idle->DataWait	75	Not Covered
Idle->Disabled	107	Covered	T1,T12,T2
Idle->Error	99	Covered	T19,T21,T11

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	11	68.75
IF	52	2	2	100.00
CASE	60	11	6	54.55
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T19,T20,T21
0	Covered	T19,T20,T21

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T19,T20,T21
Disabled	0	-	-	-	Covered	T19,T20,T21
EndPointClear	-	-	-	-	Covered	T19,T20,T21
Idle	-	1	1	-	Not Covered
Idle	-	1	0	-	Not Covered
Idle	-	0	-	-	Covered	T19,T20,T21
DataWait	-	-	-	1	Not Covered
DataWait	-	-	-	0	Not Covered
AckPls	-	-	-	-	Not Covered
Error	-	-	-	-	Covered	T19,T21,T11
default	-	-	-	-	Covered	T25,T26,T27

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T19,T21,T11
0	1	Covered	T12,T65,T29
0	0	Covered	T19,T20,T21

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	209958707	136825	0	0
FpvSecCmErrorStEscalate_A	209958707	137875	0	0
u_state_regs_A	209958707	209795607	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209958707	136825	0	0
T1	417033	0	0	0
T2	417033	0	0	0
T11	1073	588	0	0
T12	958	0	0	0
T13	985	440	0	0
T14	985	440	0	0
T15	0	588	0	0
T16	0	588	0	0
T19	985	440	0	0
T20	1044	0	0	0
T21	1073	588	0	0
T28	1593	0	0	0
T32	0	588	0	0
T52	0	440	0	0
T53	0	440	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209958707	137875	0	0
T1	417033	0	0	0
T2	417033	0	0	0
T11	1073	589	0	0
T12	958	0	0	0
T13	985	441	0	0
T14	985	441	0	0
T15	0	589	0	0
T16	0	589	0	0
T19	985	441	0	0
T20	1044	0	0	0
T21	1073	589	0	0
T28	1593	0	0	0
T32	0	589	0	0
T52	0	441	0	0
T53	0	441	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209958707	209795607	0	0
T1	417033	417022	0	0
T2	417033	417022	0	0
T11	1073	930	0	0
T12	958	898	0	0
T13	985	830	0	0
T14	985	830	0	0
T19	985	830	0	0
T20	1044	982	0	0
T21	1073	930	0	0
T28	1593	1531	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T19,T20,T21
1	0	Covered	T19,T20,T21
1	1	Covered	T12,T65,T29

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	9	64.29
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T20,T21,T1
DataWait	75	Covered	T20,T21,T1
Disabled	107	Covered	T19,T20,T21
EndPointClear	63	Covered	T19,T20,T21
Error	99	Covered	T19,T21,T11
Idle	68	Covered	T19,T20,T21

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T20,T21,T1
DataWait->AckPls	80	Covered	T20,T21,T1
DataWait->Disabled	107	Not Covered
DataWait->Error	99	Not Covered
Disabled->EndPointClear	63	Covered	T19,T20,T21
Disabled->Error	99	Covered	T25,T26,T27
EndPointClear->Disabled	107	Not Covered
EndPointClear->Error	99	Covered	T25,T26,T27
EndPointClear->Idle	68	Covered	T19,T20,T21
Idle->DataWait	75	Covered	T20,T21,T1
Idle->Disabled	107	Covered	T1,T12,T2
Idle->Error	99	Covered	T21,T11,T15

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T19,T20,T21
0	Covered	T19,T20,T21

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T19,T20,T21
Disabled	0	-	-	-	Covered	T19,T20,T21
EndPointClear	-	-	-	-	Covered	T19,T20,T21
Idle	-	1	1	-	Covered	T20,T21,T1
Idle	-	1	0	-	Covered	T20,T21,T1
Idle	-	0	-	-	Covered	T19,T20,T21
DataWait	-	-	-	1	Covered	T20,T21,T1
DataWait	-	-	-	0	Covered	T20,T1,T2
AckPls	-	-	-	-	Covered	T20,T21,T1
Error	-	-	-	-	Covered	T19,T21,T11
default	-	-	-	-	Covered	T19,T13,T14

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T19,T21,T11
0	1	Covered	T12,T65,T29
0	0	Covered	T19,T20,T21

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	209958707	131825	0	0
FpvSecCmErrorStEscalate_A	209958707	132875	0	0
u_state_regs_A	209934507	209771407	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209958707	131825	0	0
T1	417033	0	0	0
T2	417033	0	0	0
T11	1073	588	0	0
T12	958	0	0	0
T13	985	390	0	0
T14	985	390	0	0
T15	0	588	0	0
T16	0	588	0	0
T19	985	390	0	0
T20	1044	0	0	0
T21	1073	588	0	0
T28	1593	0	0	0
T32	0	588	0	0
T52	0	390	0	0
T53	0	390	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209958707	132875	0	0
T1	417033	0	0	0
T2	417033	0	0	0
T11	1073	589	0	0
T12	958	0	0	0
T13	985	391	0	0
T14	985	391	0	0
T15	0	589	0	0
T16	0	589	0	0
T19	985	391	0	0
T20	1044	0	0	0
T21	1073	589	0	0
T28	1593	0	0	0
T32	0	589	0	0
T52	0	391	0	0
T53	0	391	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209934507	209771407	0	0
T1	417033	417022	0	0
T2	417033	417022	0	0
T11	961	818	0	0
T12	958	898	0	0
T13	799	644	0	0
T14	799	644	0	0
T19	799	644	0	0
T20	1044	982	0	0
T21	961	818	0	0
T28	1593	1531	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T19,T20,T21
1	0	Covered	T19,T20,T21
1	1	Covered	T12,T65,T29

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	9	64.29
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T29,T30,T31
DataWait	75	Covered	T29,T30,T31
Disabled	107	Covered	T19,T20,T21
EndPointClear	63	Covered	T19,T20,T21
Error	99	Covered	T19,T21,T11
Idle	68	Covered	T19,T20,T21

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T29,T30,T31
DataWait->AckPls	80	Covered	T29,T30,T31
DataWait->Disabled	107	Not Covered
DataWait->Error	99	Not Covered
Disabled->EndPointClear	63	Covered	T19,T20,T21
Disabled->Error	99	Covered	T25,T26,T27
EndPointClear->Disabled	107	Not Covered
EndPointClear->Error	99	Covered	T25,T26,T27
EndPointClear->Idle	68	Covered	T19,T20,T21
Idle->DataWait	75	Covered	T29,T30,T31
Idle->Disabled	107	Covered	T1,T12,T2
Idle->Error	99	Covered	T19,T21,T11

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T19,T20,T21
0	Covered	T19,T20,T21

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T19,T20,T21
Disabled	0	-	-	-	Covered	T19,T20,T21
EndPointClear	-	-	-	-	Covered	T19,T20,T21
Idle	-	1	1	-	Covered	T29,T30,T31
Idle	-	1	0	-	Covered	T29,T30,T31
Idle	-	0	-	-	Covered	T19,T20,T21
DataWait	-	-	-	1	Covered	T29,T30,T31
DataWait	-	-	-	0	Covered	T29,T30,T31
AckPls	-	-	-	-	Covered	T29,T30,T31
Error	-	-	-	-	Covered	T19,T21,T11
default	-	-	-	-	Covered	T25,T26,T27

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T19,T21,T11
0	1	Covered	T12,T65,T29
0	0	Covered	T19,T20,T21

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	209958707	136825	0	0
FpvSecCmErrorStEscalate_A	209958707	137875	0	0
u_state_regs_A	209958707	209795607	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209958707	136825	0	0
T1	417033	0	0	0
T2	417033	0	0	0
T11	1073	588	0	0
T12	958	0	0	0
T13	985	440	0	0
T14	985	440	0	0
T15	0	588	0	0
T16	0	588	0	0
T19	985	440	0	0
T20	1044	0	0	0
T21	1073	588	0	0
T28	1593	0	0	0
T32	0	588	0	0
T52	0	440	0	0
T53	0	440	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209958707	137875	0	0
T1	417033	0	0	0
T2	417033	0	0	0
T11	1073	589	0	0
T12	958	0	0	0
T13	985	441	0	0
T14	985	441	0	0
T15	0	589	0	0
T16	0	589	0	0
T19	985	441	0	0
T20	1044	0	0	0
T21	1073	589	0	0
T28	1593	0	0	0
T32	0	589	0	0
T52	0	441	0	0
T53	0	441	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209958707	209795607	0	0
T1	417033	417022	0	0
T2	417033	417022	0	0
T11	1073	930	0	0
T12	958	898	0	0
T13	985	830	0	0
T14	985	830	0	0
T19	985	830	0	0
T20	1044	982	0	0
T21	1073	930	0	0
T28	1593	1531	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T19,T20,T21
1	0	Covered	T19,T20,T21
1	1	Covered	T12,T65,T29

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	9	64.29
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T19,T12,T13
DataWait	75	Covered	T19,T12,T13
Disabled	107	Covered	T19,T20,T21
EndPointClear	63	Covered	T19,T20,T21
Error	99	Covered	T19,T21,T11
Idle	68	Covered	T19,T20,T21

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T19,T12,T13
DataWait->AckPls	80	Covered	T19,T12,T13
DataWait->Disabled	107	Not Covered
DataWait->Error	99	Not Covered
Disabled->EndPointClear	63	Covered	T19,T20,T21
Disabled->Error	99	Covered	T25,T26,T27
EndPointClear->Disabled	107	Not Covered
EndPointClear->Error	99	Covered	T25,T26,T27
EndPointClear->Idle	68	Covered	T19,T20,T21
Idle->DataWait	75	Covered	T19,T12,T13
Idle->Disabled	107	Covered	T1,T12,T2
Idle->Error	99	Covered	T19,T21,T11

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T19,T20,T21
0	Covered	T19,T20,T21

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T19,T20,T21
Disabled	0	-	-	-	Covered	T19,T20,T21
EndPointClear	-	-	-	-	Covered	T19,T20,T21
Idle	-	1	1	-	Covered	T19,T12,T13
Idle	-	1	0	-	Covered	T19,T12,T13
Idle	-	0	-	-	Covered	T19,T20,T21
DataWait	-	-	-	1	Covered	T19,T12,T13
DataWait	-	-	-	0	Covered	T19,T12,T13
AckPls	-	-	-	-	Covered	T19,T12,T13
Error	-	-	-	-	Covered	T19,T21,T11
default	-	-	-	-	Covered	T25,T26,T27

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T19,T21,T11
0	1	Covered	T12,T65,T29
0	0	Covered	T19,T20,T21

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	209958707	136825	0	0
FpvSecCmErrorStEscalate_A	209958707	137875	0	0
u_state_regs_A	209958707	209795607	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209958707	136825	0	0
T1	417033	0	0	0
T2	417033	0	0	0
T11	1073	588	0	0
T12	958	0	0	0
T13	985	440	0	0
T14	985	440	0	0
T15	0	588	0	0
T16	0	588	0	0
T19	985	440	0	0
T20	1044	0	0	0
T21	1073	588	0	0
T28	1593	0	0	0
T32	0	588	0	0
T52	0	440	0	0
T53	0	440	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209958707	137875	0	0
T1	417033	0	0	0
T2	417033	0	0	0
T11	1073	589	0	0
T12	958	0	0	0
T13	985	441	0	0
T14	985	441	0	0
T15	0	589	0	0
T16	0	589	0	0
T19	985	441	0	0
T20	1044	0	0	0
T21	1073	589	0	0
T28	1593	0	0	0
T32	0	589	0	0
T52	0	441	0	0
T53	0	441	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	209958707	209795607	0	0
T1	417033	417022	0	0
T2	417033	417022	0	0
T11	1073	930	0	0
T12	958	898	0	0
T13	985	830	0	0
T14	985	830	0	0
T19	985	830	0	0
T20	1044	982	0	0
T21	1073	930	0	0
T28	1593	1531	0	0