Line Coverage for Module :
prim_fifo_sync
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
ALWAYS | 70 | 4 | 4 | 100.00 |
CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 86 | 1 | 1 | 100.00 |
CONT_ASSIGN | 87 | 1 | 1 | 100.00 |
CONT_ASSIGN | 88 | 1 | 1 | 100.00 |
CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 98 | 1 | 1 | 100.00 |
CONT_ASSIGN | 99 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
CONT_ASSIGN | 146 | 1 | 1 | 100.00 |
CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
ALWAYS | 165 | 2 | 2 | 100.00 |
CONT_ASSIGN | 175 | 1 | 1 | 100.00 |
CONT_ASSIGN | 176 | 1 | 1 | 100.00 |
CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
|
|
|
MISSING_ELSE |
84 |
1 |
1 |
85 |
1 |
1 |
86 |
1 |
1 |
87 |
1 |
1 |
88 |
1 |
1 |
92 |
1 |
1 |
93 |
1 |
1 |
98 |
1 |
1 |
99 |
1 |
1 |
100 |
1 |
1 |
145 |
1 |
1 |
146 |
1 |
1 |
162 |
1 |
1 |
165 |
1 |
1 |
166 |
1 |
1 |
|
|
|
MISSING_ELSE |
175 |
1 |
1 |
176 |
1 |
1 |
180 |
1 |
1 |
Cond Coverage for Module :
prim_fifo_sync
| Total | Covered | Percent |
Conditions | 26 | 22 | 84.62 |
Logical | 26 | 22 | 84.62 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 88
EXPRESSION
Number Term
1 gen_normal_fifo.full ? (4'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((4'(gen_normal_fifo.wptr_value) - 4'(gen_normal_fifo.rptr_value))) : (((4'(Depth) - 4'(gen_normal_fifo.rptr_value)) + 4'(gen_normal_fifo.wptr_value)))))
-1- | Status | Tests |
0 | Covered | T19,T20,T21 |
1 | Covered | T19,T13,T14 |
LINE 88
SUB-EXPRESSION
Number Term
1 (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((4'(gen_normal_fifo.wptr_value) - 4'(gen_normal_fifo.rptr_value))) : (((4'(Depth) - 4'(gen_normal_fifo.rptr_value)) + 4'(gen_normal_fifo.wptr_value))))
-1- | Status | Tests |
0 | Covered | T19,T1,T2 |
1 | Covered | T19,T20,T21 |
LINE 88
SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
---------------------------1--------------------------
-1- | Status | Tests |
0 | Covered | T19,T1,T2 |
1 | Covered | T19,T20,T21 |
LINE 92
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T19,T20,T21 |
1 | 0 | 1 | Covered | T29,T30,T31 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T19,T20,T21 |
LINE 93
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T19,T20,T21 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T19,T20,T21 |
LINE 98
EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T19,T13,T14 |
1 | 0 | Covered | T19,T20,T21 |
1 | 1 | Covered | T19,T20,T21 |
LINE 100
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T19,T20,T21 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T19,T20,T21 |
LINE 145
EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
------------------------------------------------------1------------------------------------------------------
-1- | Status | Tests |
0 | Covered | T19,T20,T21 |
1 | Covered | T19,T13,T14 |
LINE 146
EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
----------------------------1---------------------------
-1- | Status | Tests |
0 | Covered | T19,T20,T21 |
1 | Covered | T19,T20,T21 |
LINE 180
EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T19,T20,T21 |
1 | Covered | T19,T20,T21 |
Branch Coverage for Module :
prim_fifo_sync
| Line No. | Total | Covered | Percent |
Branches |
|
10 |
10 |
100.00 |
TERNARY |
88 |
3 |
3 |
100.00 |
TERNARY |
180 |
2 |
2 |
100.00 |
IF |
70 |
3 |
3 |
100.00 |
IF |
165 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 88 (gen_normal_fifo.full) ?
-2-: 88 ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ?
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T19,T13,T14 |
0 |
1 |
Covered |
T19,T20,T21 |
0 |
0 |
Covered |
T19,T1,T2 |
LineNo. Expression
-1-: 180 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T19,T20,T21 |
0 |
Covered |
T19,T20,T21 |
LineNo. Expression
-1-: 70 if ((!rst_ni))
-2-: 72 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T19,T20,T21 |
0 |
1 |
Covered |
T19,T20,T21 |
0 |
0 |
Covered |
T19,T20,T21 |
LineNo. Expression
-1-: 165 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T19,T20,T21 |
0 |
Covered |
T19,T20,T21 |
Assert Coverage for Module :
prim_fifo_sync
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
629613221 |
203925 |
0 |
0 |
T1 |
1251099 |
838 |
0 |
0 |
T2 |
1251099 |
838 |
0 |
0 |
T11 |
1365 |
4 |
0 |
0 |
T12 |
2874 |
25 |
0 |
0 |
T13 |
1253 |
93 |
0 |
0 |
T14 |
1253 |
93 |
0 |
0 |
T15 |
0 |
4 |
0 |
0 |
T19 |
1253 |
93 |
0 |
0 |
T20 |
3132 |
4 |
0 |
0 |
T21 |
1365 |
4 |
0 |
0 |
T28 |
4779 |
0 |
0 |
0 |
T29 |
0 |
2725 |
0 |
0 |
T52 |
0 |
75 |
0 |
0 |
T53 |
0 |
75 |
0 |
0 |
T62 |
0 |
19 |
0 |
0 |
T63 |
0 |
19 |
0 |
0 |
T65 |
0 |
19 |
0 |
0 |
T105 |
0 |
25 |
0 |
0 |
T106 |
0 |
25 |
0 |
0 |
T107 |
0 |
25 |
0 |
0 |
T108 |
0 |
25 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
629876121 |
629386821 |
0 |
0 |
T1 |
1251099 |
1251066 |
0 |
0 |
T2 |
1251099 |
1251066 |
0 |
0 |
T11 |
3219 |
2790 |
0 |
0 |
T12 |
2874 |
2694 |
0 |
0 |
T13 |
2955 |
2490 |
0 |
0 |
T14 |
2955 |
2490 |
0 |
0 |
T19 |
2955 |
2490 |
0 |
0 |
T20 |
3132 |
2946 |
0 |
0 |
T21 |
3219 |
2790 |
0 |
0 |
T28 |
4779 |
4593 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
629876121 |
629386821 |
0 |
0 |
T1 |
1251099 |
1251066 |
0 |
0 |
T2 |
1251099 |
1251066 |
0 |
0 |
T11 |
3219 |
2790 |
0 |
0 |
T12 |
2874 |
2694 |
0 |
0 |
T13 |
2955 |
2490 |
0 |
0 |
T14 |
2955 |
2490 |
0 |
0 |
T19 |
2955 |
2490 |
0 |
0 |
T20 |
3132 |
2946 |
0 |
0 |
T21 |
3219 |
2790 |
0 |
0 |
T28 |
4779 |
4593 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
629876121 |
629386821 |
0 |
0 |
T1 |
1251099 |
1251066 |
0 |
0 |
T2 |
1251099 |
1251066 |
0 |
0 |
T11 |
3219 |
2790 |
0 |
0 |
T12 |
2874 |
2694 |
0 |
0 |
T13 |
2955 |
2490 |
0 |
0 |
T14 |
2955 |
2490 |
0 |
0 |
T19 |
2955 |
2490 |
0 |
0 |
T20 |
3132 |
2946 |
0 |
0 |
T21 |
3219 |
2790 |
0 |
0 |
T28 |
4779 |
4593 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
629876121 |
279825 |
0 |
0 |
T1 |
1251099 |
838 |
0 |
0 |
T2 |
1251099 |
838 |
0 |
0 |
T11 |
3219 |
4 |
0 |
0 |
T12 |
2874 |
25 |
0 |
0 |
T13 |
2955 |
852 |
0 |
0 |
T14 |
2955 |
852 |
0 |
0 |
T15 |
0 |
4 |
0 |
0 |
T19 |
2955 |
852 |
0 |
0 |
T20 |
3132 |
4 |
0 |
0 |
T21 |
3219 |
4 |
0 |
0 |
T28 |
4779 |
0 |
0 |
0 |
T29 |
0 |
2725 |
0 |
0 |
T52 |
0 |
834 |
0 |
0 |
T53 |
0 |
834 |
0 |
0 |
T62 |
0 |
19 |
0 |
0 |
T63 |
0 |
19 |
0 |
0 |
T65 |
0 |
19 |
0 |
0 |
T105 |
0 |
401 |
0 |
0 |
T106 |
0 |
401 |
0 |
0 |
T107 |
0 |
401 |
0 |
0 |
T108 |
0 |
401 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_output
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
ALWAYS | 70 | 4 | 4 | 100.00 |
CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 86 | 1 | 1 | 100.00 |
CONT_ASSIGN | 87 | 1 | 1 | 100.00 |
CONT_ASSIGN | 88 | 1 | 1 | 100.00 |
CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 98 | 1 | 1 | 100.00 |
CONT_ASSIGN | 99 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
CONT_ASSIGN | 146 | 1 | 1 | 100.00 |
CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
ALWAYS | 165 | 2 | 2 | 100.00 |
CONT_ASSIGN | 175 | 1 | 1 | 100.00 |
CONT_ASSIGN | 176 | 1 | 1 | 100.00 |
CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
|
|
|
MISSING_ELSE |
84 |
1 |
1 |
85 |
1 |
1 |
86 |
1 |
1 |
87 |
1 |
1 |
88 |
1 |
1 |
92 |
1 |
1 |
93 |
1 |
1 |
98 |
1 |
1 |
99 |
1 |
1 |
100 |
1 |
1 |
145 |
1 |
1 |
146 |
1 |
1 |
162 |
1 |
1 |
165 |
1 |
1 |
166 |
1 |
1 |
|
|
|
MISSING_ELSE |
175 |
1 |
1 |
176 |
1 |
1 |
180 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_output
| Total | Covered | Percent |
Conditions | 26 | 18 | 69.23 |
Logical | 26 | 18 | 69.23 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 88
EXPRESSION
Number Term
1 gen_normal_fifo.full ? (4'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((4'(gen_normal_fifo.wptr_value) - 4'(gen_normal_fifo.rptr_value))) : (((4'(Depth) - 4'(gen_normal_fifo.rptr_value)) + 4'(gen_normal_fifo.wptr_value)))))
-1- | Status | Tests |
0 | Covered | T19,T20,T21 |
1 | Not Covered | |
LINE 88
SUB-EXPRESSION
Number Term
1 (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((4'(gen_normal_fifo.wptr_value) - 4'(gen_normal_fifo.rptr_value))) : (((4'(Depth) - 4'(gen_normal_fifo.rptr_value)) + 4'(gen_normal_fifo.wptr_value))))
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T19,T20,T21 |
LINE 88
SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
---------------------------1--------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T19,T20,T21 |
LINE 92
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T19,T20,T21 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T19,T20,T21 |
LINE 93
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T19,T20,T21 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T19,T20,T21 |
LINE 98
EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T19,T20,T21 |
1 | 1 | Covered | T19,T20,T21 |
LINE 100
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T19,T20,T21 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T19,T20,T21 |
LINE 145
EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
------------------------------------------------------1------------------------------------------------------
-1- | Status | Tests |
0 | Covered | T19,T20,T21 |
1 | Not Covered | |
LINE 146
EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
----------------------------1---------------------------
-1- | Status | Tests |
0 | Covered | T19,T20,T21 |
1 | Covered | T19,T20,T21 |
LINE 180
EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T19,T20,T21 |
1 | Covered | T19,T20,T21 |
Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_output
| Line No. | Total | Covered | Percent |
Branches |
|
10 |
9 |
90.00 |
TERNARY |
88 |
3 |
2 |
66.67 |
TERNARY |
180 |
2 |
2 |
100.00 |
IF |
70 |
3 |
3 |
100.00 |
IF |
165 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 88 (gen_normal_fifo.full) ?
-2-: 88 ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ?
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Not Covered |
|
0 |
1 |
Covered |
T19,T20,T21 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 180 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T19,T20,T21 |
0 |
Covered |
T19,T20,T21 |
LineNo. Expression
-1-: 70 if ((!rst_ni))
-2-: 72 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T19,T20,T21 |
0 |
1 |
Covered |
T19,T20,T21 |
0 |
0 |
Covered |
T19,T20,T21 |
LineNo. Expression
-1-: 165 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T19,T20,T21 |
0 |
Covered |
T19,T20,T21 |
Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_output
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
209958707 |
59244 |
0 |
0 |
T1 |
417033 |
838 |
0 |
0 |
T2 |
417033 |
838 |
0 |
0 |
T11 |
1073 |
4 |
0 |
0 |
T12 |
958 |
6 |
0 |
0 |
T13 |
985 |
18 |
0 |
0 |
T14 |
985 |
18 |
0 |
0 |
T15 |
0 |
4 |
0 |
0 |
T19 |
985 |
18 |
0 |
0 |
T20 |
1044 |
4 |
0 |
0 |
T21 |
1073 |
4 |
0 |
0 |
T28 |
1593 |
0 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
209958707 |
209795607 |
0 |
0 |
T1 |
417033 |
417022 |
0 |
0 |
T2 |
417033 |
417022 |
0 |
0 |
T11 |
1073 |
930 |
0 |
0 |
T12 |
958 |
898 |
0 |
0 |
T13 |
985 |
830 |
0 |
0 |
T14 |
985 |
830 |
0 |
0 |
T19 |
985 |
830 |
0 |
0 |
T20 |
1044 |
982 |
0 |
0 |
T21 |
1073 |
930 |
0 |
0 |
T28 |
1593 |
1531 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
209958707 |
209795607 |
0 |
0 |
T1 |
417033 |
417022 |
0 |
0 |
T2 |
417033 |
417022 |
0 |
0 |
T11 |
1073 |
930 |
0 |
0 |
T12 |
958 |
898 |
0 |
0 |
T13 |
985 |
830 |
0 |
0 |
T14 |
985 |
830 |
0 |
0 |
T19 |
985 |
830 |
0 |
0 |
T20 |
1044 |
982 |
0 |
0 |
T21 |
1073 |
930 |
0 |
0 |
T28 |
1593 |
1531 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
209958707 |
209795607 |
0 |
0 |
T1 |
417033 |
417022 |
0 |
0 |
T2 |
417033 |
417022 |
0 |
0 |
T11 |
1073 |
930 |
0 |
0 |
T12 |
958 |
898 |
0 |
0 |
T13 |
985 |
830 |
0 |
0 |
T14 |
985 |
830 |
0 |
0 |
T19 |
985 |
830 |
0 |
0 |
T20 |
1044 |
982 |
0 |
0 |
T21 |
1073 |
930 |
0 |
0 |
T28 |
1593 |
1531 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
209958707 |
59244 |
0 |
0 |
T1 |
417033 |
838 |
0 |
0 |
T2 |
417033 |
838 |
0 |
0 |
T11 |
1073 |
4 |
0 |
0 |
T12 |
958 |
6 |
0 |
0 |
T13 |
985 |
18 |
0 |
0 |
T14 |
985 |
18 |
0 |
0 |
T15 |
0 |
4 |
0 |
0 |
T19 |
985 |
18 |
0 |
0 |
T20 |
1044 |
4 |
0 |
0 |
T21 |
1073 |
4 |
0 |
0 |
T28 |
1593 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
ALWAYS | 70 | 4 | 4 | 100.00 |
CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 86 | 1 | 1 | 100.00 |
CONT_ASSIGN | 87 | 1 | 1 | 100.00 |
CONT_ASSIGN | 88 | 1 | 1 | 100.00 |
CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 98 | 1 | 1 | 100.00 |
CONT_ASSIGN | 99 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
CONT_ASSIGN | 146 | 1 | 1 | 100.00 |
CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
ALWAYS | 165 | 2 | 2 | 100.00 |
CONT_ASSIGN | 175 | 1 | 1 | 100.00 |
CONT_ASSIGN | 176 | 1 | 1 | 100.00 |
CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
|
|
|
MISSING_ELSE |
84 |
1 |
1 |
85 |
1 |
1 |
86 |
1 |
1 |
87 |
1 |
1 |
88 |
1 |
1 |
92 |
1 |
1 |
93 |
1 |
1 |
98 |
1 |
1 |
99 |
1 |
1 |
100 |
1 |
1 |
145 |
1 |
1 |
146 |
1 |
1 |
162 |
1 |
1 |
165 |
1 |
1 |
166 |
1 |
1 |
|
|
|
MISSING_ELSE |
175 |
1 |
1 |
176 |
1 |
1 |
180 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd
| Total | Covered | Percent |
Conditions | 26 | 21 | 80.77 |
Logical | 26 | 21 | 80.77 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 88
EXPRESSION
Number Term
1 gen_normal_fifo.full ? (4'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((4'(gen_normal_fifo.wptr_value) - 4'(gen_normal_fifo.rptr_value))) : (((4'(Depth) - 4'(gen_normal_fifo.rptr_value)) + 4'(gen_normal_fifo.wptr_value)))))
-1- | Status | Tests |
0 | Covered | T19,T20,T21 |
1 | Covered | T29,T30,T31 |
LINE 88
SUB-EXPRESSION
Number Term
1 (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((4'(gen_normal_fifo.wptr_value) - 4'(gen_normal_fifo.rptr_value))) : (((4'(Depth) - 4'(gen_normal_fifo.rptr_value)) + 4'(gen_normal_fifo.wptr_value))))
-1- | Status | Tests |
0 | Covered | T29,T30,T31 |
1 | Covered | T19,T20,T21 |
LINE 88
SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
---------------------------1--------------------------
-1- | Status | Tests |
0 | Covered | T29,T30,T31 |
1 | Covered | T19,T20,T21 |
LINE 92
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T19,T20,T21 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T19,T13,T14 |
LINE 93
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T19,T13,T14 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T29,T30,T31 |
LINE 98
EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T29,T30,T31 |
1 | 0 | Covered | T19,T20,T21 |
1 | 1 | Covered | T19,T20,T21 |
LINE 100
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T19,T20,T21 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T19,T13,T14 |
LINE 145
EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
------------------------------------------------------1------------------------------------------------------
-1- | Status | Tests |
0 | Covered | T19,T20,T21 |
1 | Covered | T29,T30,T31 |
LINE 146
EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
----------------------------1---------------------------
-1- | Status | Tests |
0 | Covered | T19,T20,T21 |
1 | Covered | T19,T20,T21 |
LINE 180
EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T19,T13,T14 |
1 | Covered | T19,T20,T21 |
Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd
| Line No. | Total | Covered | Percent |
Branches |
|
10 |
10 |
100.00 |
TERNARY |
88 |
3 |
3 |
100.00 |
TERNARY |
180 |
2 |
2 |
100.00 |
IF |
70 |
3 |
3 |
100.00 |
IF |
165 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 88 (gen_normal_fifo.full) ?
-2-: 88 ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ?
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T29,T30,T31 |
0 |
1 |
Covered |
T19,T20,T21 |
0 |
0 |
Covered |
T29,T30,T31 |
LineNo. Expression
-1-: 180 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T19,T20,T21 |
0 |
Covered |
T19,T13,T14 |
LineNo. Expression
-1-: 70 if ((!rst_ni))
-2-: 72 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T19,T20,T21 |
0 |
1 |
Covered |
T19,T20,T21 |
0 |
0 |
Covered |
T19,T20,T21 |
LineNo. Expression
-1-: 165 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T19,T13,T14 |
0 |
Covered |
T19,T20,T21 |
Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
209827257 |
70800 |
0 |
0 |
T1 |
417033 |
0 |
0 |
0 |
T2 |
417033 |
0 |
0 |
0 |
T11 |
146 |
0 |
0 |
0 |
T12 |
958 |
0 |
0 |
0 |
T13 |
134 |
25 |
0 |
0 |
T14 |
134 |
25 |
0 |
0 |
T19 |
134 |
25 |
0 |
0 |
T20 |
1044 |
0 |
0 |
0 |
T21 |
146 |
0 |
0 |
0 |
T28 |
1593 |
0 |
0 |
0 |
T29 |
0 |
1366 |
0 |
0 |
T52 |
0 |
25 |
0 |
0 |
T53 |
0 |
25 |
0 |
0 |
T105 |
0 |
25 |
0 |
0 |
T106 |
0 |
25 |
0 |
0 |
T107 |
0 |
25 |
0 |
0 |
T108 |
0 |
25 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
209958707 |
209795607 |
0 |
0 |
T1 |
417033 |
417022 |
0 |
0 |
T2 |
417033 |
417022 |
0 |
0 |
T11 |
1073 |
930 |
0 |
0 |
T12 |
958 |
898 |
0 |
0 |
T13 |
985 |
830 |
0 |
0 |
T14 |
985 |
830 |
0 |
0 |
T19 |
985 |
830 |
0 |
0 |
T20 |
1044 |
982 |
0 |
0 |
T21 |
1073 |
930 |
0 |
0 |
T28 |
1593 |
1531 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
209958707 |
209795607 |
0 |
0 |
T1 |
417033 |
417022 |
0 |
0 |
T2 |
417033 |
417022 |
0 |
0 |
T11 |
1073 |
930 |
0 |
0 |
T12 |
958 |
898 |
0 |
0 |
T13 |
985 |
830 |
0 |
0 |
T14 |
985 |
830 |
0 |
0 |
T19 |
985 |
830 |
0 |
0 |
T20 |
1044 |
982 |
0 |
0 |
T21 |
1073 |
930 |
0 |
0 |
T28 |
1593 |
1531 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
209958707 |
209795607 |
0 |
0 |
T1 |
417033 |
417022 |
0 |
0 |
T2 |
417033 |
417022 |
0 |
0 |
T11 |
1073 |
930 |
0 |
0 |
T12 |
958 |
898 |
0 |
0 |
T13 |
985 |
830 |
0 |
0 |
T14 |
985 |
830 |
0 |
0 |
T19 |
985 |
830 |
0 |
0 |
T20 |
1044 |
982 |
0 |
0 |
T21 |
1073 |
930 |
0 |
0 |
T28 |
1593 |
1531 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
209958707 |
108400 |
0 |
0 |
T1 |
417033 |
0 |
0 |
0 |
T2 |
417033 |
0 |
0 |
0 |
T11 |
1073 |
0 |
0 |
0 |
T12 |
958 |
0 |
0 |
0 |
T13 |
985 |
401 |
0 |
0 |
T14 |
985 |
401 |
0 |
0 |
T19 |
985 |
401 |
0 |
0 |
T20 |
1044 |
0 |
0 |
0 |
T21 |
1073 |
0 |
0 |
0 |
T28 |
1593 |
0 |
0 |
0 |
T29 |
0 |
1366 |
0 |
0 |
T52 |
0 |
401 |
0 |
0 |
T53 |
0 |
401 |
0 |
0 |
T105 |
0 |
401 |
0 |
0 |
T106 |
0 |
401 |
0 |
0 |
T107 |
0 |
401 |
0 |
0 |
T108 |
0 |
401 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
ALWAYS | 70 | 4 | 4 | 100.00 |
CONT_ASSIGN | 84 | 1 | 1 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 86 | 1 | 1 | 100.00 |
CONT_ASSIGN | 87 | 1 | 1 | 100.00 |
CONT_ASSIGN | 88 | 1 | 1 | 100.00 |
CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 98 | 1 | 1 | 100.00 |
CONT_ASSIGN | 99 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
CONT_ASSIGN | 146 | 1 | 1 | 100.00 |
CONT_ASSIGN | 162 | 1 | 1 | 100.00 |
ALWAYS | 165 | 2 | 2 | 100.00 |
CONT_ASSIGN | 175 | 1 | 1 | 100.00 |
CONT_ASSIGN | 176 | 1 | 1 | 100.00 |
CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
70 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
|
|
|
MISSING_ELSE |
84 |
1 |
1 |
85 |
1 |
1 |
86 |
1 |
1 |
87 |
1 |
1 |
88 |
1 |
1 |
92 |
1 |
1 |
93 |
1 |
1 |
98 |
1 |
1 |
99 |
1 |
1 |
100 |
1 |
1 |
145 |
1 |
1 |
146 |
1 |
1 |
162 |
1 |
1 |
165 |
1 |
1 |
166 |
1 |
1 |
|
|
|
MISSING_ELSE |
175 |
1 |
1 |
176 |
1 |
1 |
180 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd
| Total | Covered | Percent |
Conditions | 26 | 22 | 84.62 |
Logical | 26 | 22 | 84.62 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 88
EXPRESSION
Number Term
1 gen_normal_fifo.full ? (4'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((4'(gen_normal_fifo.wptr_value) - 4'(gen_normal_fifo.rptr_value))) : (((4'(Depth) - 4'(gen_normal_fifo.rptr_value)) + 4'(gen_normal_fifo.wptr_value)))))
-1- | Status | Tests |
0 | Covered | T19,T20,T21 |
1 | Covered | T19,T13,T14 |
LINE 88
SUB-EXPRESSION
Number Term
1 (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((4'(gen_normal_fifo.wptr_value) - 4'(gen_normal_fifo.rptr_value))) : (((4'(Depth) - 4'(gen_normal_fifo.rptr_value)) + 4'(gen_normal_fifo.wptr_value))))
-1- | Status | Tests |
0 | Covered | T19,T13,T14 |
1 | Covered | T19,T20,T21 |
LINE 88
SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
---------------------------1--------------------------
-1- | Status | Tests |
0 | Covered | T19,T13,T14 |
1 | Covered | T19,T20,T21 |
LINE 92
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T19,T20,T21 |
1 | 0 | 1 | Covered | T29,T30,T31 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T19,T12,T13 |
LINE 93
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T19,T12,T13 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T19,T12,T13 |
LINE 98
EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T19,T13,T14 |
1 | 0 | Covered | T19,T20,T21 |
1 | 1 | Covered | T19,T20,T21 |
LINE 100
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T19,T20,T21 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T19,T12,T13 |
LINE 145
EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
------------------------------------------------------1------------------------------------------------------
-1- | Status | Tests |
0 | Covered | T19,T20,T21 |
1 | Covered | T19,T13,T14 |
LINE 146
EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
----------------------------1---------------------------
-1- | Status | Tests |
0 | Covered | T19,T20,T21 |
1 | Covered | T19,T20,T21 |
LINE 180
EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T19,T12,T13 |
1 | Covered | T19,T20,T21 |
Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd
| Line No. | Total | Covered | Percent |
Branches |
|
10 |
10 |
100.00 |
TERNARY |
88 |
3 |
3 |
100.00 |
TERNARY |
180 |
2 |
2 |
100.00 |
IF |
70 |
3 |
3 |
100.00 |
IF |
165 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 88 (gen_normal_fifo.full) ?
-2-: 88 ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ?
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T19,T13,T14 |
0 |
1 |
Covered |
T19,T20,T21 |
0 |
0 |
Covered |
T19,T13,T14 |
LineNo. Expression
-1-: 180 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T19,T20,T21 |
0 |
Covered |
T19,T12,T13 |
LineNo. Expression
-1-: 70 if ((!rst_ni))
-2-: 72 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T19,T20,T21 |
0 |
1 |
Covered |
T19,T20,T21 |
0 |
0 |
Covered |
T19,T20,T21 |
LineNo. Expression
-1-: 165 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Covered |
T19,T12,T13 |
0 |
Covered |
T19,T20,T21 |
Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
209827257 |
73881 |
0 |
0 |
T1 |
417033 |
0 |
0 |
0 |
T2 |
417033 |
0 |
0 |
0 |
T11 |
146 |
0 |
0 |
0 |
T12 |
958 |
19 |
0 |
0 |
T13 |
134 |
50 |
0 |
0 |
T14 |
134 |
50 |
0 |
0 |
T19 |
134 |
50 |
0 |
0 |
T20 |
1044 |
0 |
0 |
0 |
T21 |
146 |
0 |
0 |
0 |
T28 |
1593 |
0 |
0 |
0 |
T29 |
0 |
1359 |
0 |
0 |
T52 |
0 |
50 |
0 |
0 |
T53 |
0 |
50 |
0 |
0 |
T62 |
0 |
19 |
0 |
0 |
T63 |
0 |
19 |
0 |
0 |
T65 |
0 |
19 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
209958707 |
209795607 |
0 |
0 |
T1 |
417033 |
417022 |
0 |
0 |
T2 |
417033 |
417022 |
0 |
0 |
T11 |
1073 |
930 |
0 |
0 |
T12 |
958 |
898 |
0 |
0 |
T13 |
985 |
830 |
0 |
0 |
T14 |
985 |
830 |
0 |
0 |
T19 |
985 |
830 |
0 |
0 |
T20 |
1044 |
982 |
0 |
0 |
T21 |
1073 |
930 |
0 |
0 |
T28 |
1593 |
1531 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
209958707 |
209795607 |
0 |
0 |
T1 |
417033 |
417022 |
0 |
0 |
T2 |
417033 |
417022 |
0 |
0 |
T11 |
1073 |
930 |
0 |
0 |
T12 |
958 |
898 |
0 |
0 |
T13 |
985 |
830 |
0 |
0 |
T14 |
985 |
830 |
0 |
0 |
T19 |
985 |
830 |
0 |
0 |
T20 |
1044 |
982 |
0 |
0 |
T21 |
1073 |
930 |
0 |
0 |
T28 |
1593 |
1531 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
209958707 |
209795607 |
0 |
0 |
T1 |
417033 |
417022 |
0 |
0 |
T2 |
417033 |
417022 |
0 |
0 |
T11 |
1073 |
930 |
0 |
0 |
T12 |
958 |
898 |
0 |
0 |
T13 |
985 |
830 |
0 |
0 |
T14 |
985 |
830 |
0 |
0 |
T19 |
985 |
830 |
0 |
0 |
T20 |
1044 |
982 |
0 |
0 |
T21 |
1073 |
930 |
0 |
0 |
T28 |
1593 |
1531 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
209958707 |
112181 |
0 |
0 |
T1 |
417033 |
0 |
0 |
0 |
T2 |
417033 |
0 |
0 |
0 |
T11 |
1073 |
0 |
0 |
0 |
T12 |
958 |
19 |
0 |
0 |
T13 |
985 |
433 |
0 |
0 |
T14 |
985 |
433 |
0 |
0 |
T19 |
985 |
433 |
0 |
0 |
T20 |
1044 |
0 |
0 |
0 |
T21 |
1073 |
0 |
0 |
0 |
T28 |
1593 |
0 |
0 |
0 |
T29 |
0 |
1359 |
0 |
0 |
T52 |
0 |
433 |
0 |
0 |
T53 |
0 |
433 |
0 |
0 |
T62 |
0 |
19 |
0 |
0 |
T63 |
0 |
19 |
0 |
0 |
T65 |
0 |
19 |
0 |
0 |