Toggle Coverage for Module :
prim_count
| Total | Covered | Percent |
Totals |
8 |
7 |
87.50 |
Total Bits |
202 |
140 |
69.31 |
Total Bits 0->1 |
101 |
70 |
69.31 |
Total Bits 1->0 |
101 |
70 |
69.31 |
| | | |
Ports |
8 |
7 |
87.50 |
Port Bits |
202 |
140 |
69.31 |
Port Bits 0->1 |
101 |
70 |
69.31 |
Port Bits 1->0 |
101 |
70 |
69.31 |
Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i |
Yes |
Yes |
T19,T20,T21 |
Yes |
T19,T20,T21 |
INPUT |
rst_ni |
Yes |
Yes |
T19,T21,T1 |
Yes |
T19,T20,T21 |
INPUT |
clr_i |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
set_i |
Yes |
Yes |
T19,T20,T21 |
Yes |
T19,T20,T21 |
INPUT |
set_cnt_i[0] |
Yes |
Yes |
*T19,*T13,*T14 |
Yes |
T19,T13,T14 |
INPUT |
set_cnt_i[31:1] |
No |
No |
|
No |
|
INPUT |
incr_en_i |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
decr_en_i |
Yes |
Yes |
T19,T13,T14 |
Yes |
T19,T13,T14 |
INPUT |
step_i[31:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
cnt_o[31:0] |
Yes |
Yes |
T19,T13,T14 |
Yes |
T19,T13,T14 |
OUTPUT |
cnt_next_o[31:0] |
Yes |
Yes |
T19,T13,T14 |
Yes |
T19,T13,T14 |
OUTPUT |
err_o |
Yes |
Yes |
T21,T11,T15 |
Yes |
T21,T11,T15 |
OUTPUT |
*Tests covering at least one bit in the range