Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44		83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	188684048	9163631	0	0
boot_gen_cmd_rd_A	188684048	35799	0	0
boot_ins_cmd_rd_A	188684048	41724	0	0
ctrl_rd_A	188684048	35402	0	0
err_code_test_rd_A	188684048	36047	0	0
intr_enable_rd_A	188684048	39537	0	0
max_num_reqs_between_reseeds_rd_A	188684048	41386	0	0
regwen_rd_A	188684048	42214	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188684048	9163631	0	0
T21	1662	3	0	0
T26	8666	741	0	0
T27	1920	115	0	0
T40	753	0	0	0
T178	2465	218	0	0
T179	1462	48	0	0
T180	8089	12	0	0
T181	0	285	0	0
T183	0	5	0	0
T184	0	49	0	0
T185	0	1063	0	0
T186	943	0	0	0
T187	2229	0	0	0
T188	22405	0	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188684048	35799	0	0
T21	1662	4	0	0
T38	1807	1	0	0
T40	753	0	0	0
T180	8089	3	0	0
T181	2201	0	0	0
T184	1733	0	0	0
T185	0	27	0	0
T186	943	0	0	0
T187	2229	2	0	0
T188	22405	0	0	0
T189	0	22	0	0
T190	0	49	0	0
T191	0	4	0	0
T192	0	35	0	0
T193	0	11	0	0
T194	1276	0	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188684048	41724	0	0
T21	1662	5	0	0
T38	1807	19	0	0
T40	753	0	0	0
T180	8089	5	0	0
T181	2201	0	0	0
T184	1733	2	0	0
T185	0	21	0	0
T186	943	0	0	0
T187	2229	26	0	0
T188	22405	0	0	0
T189	0	5	0	0
T190	0	2	0	0
T191	0	8	0	0
T192	0	28	0	0
T194	1276	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188684048	35402	0	0
T21	1662	8	0	0
T38	1807	40	0	0
T181	2201	0	0	0
T184	1733	5	0	0
T185	0	40	0	0
T187	2229	3	0	0
T188	22405	0	0	0
T189	1847	7	0	0
T190	2221	22	0	0
T191	0	4	0	0
T192	0	42	0	0
T193	0	7	0	0
T194	1276	0	0	0
T195	922	0	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188684048	36047	0	0
T21	1662	12	0	0
T41	1205	0	0	0
T181	2201	0	0	0
T184	1733	3	0	0
T185	0	61	0	0
T187	2229	36	0	0
T188	22405	0	0	0
T189	1847	1	0	0
T190	2221	15	0	0
T191	0	9	0	0
T192	0	19	0	0
T193	0	5	0	0
T194	1276	0	0	0
T195	922	0	0	0
T196	0	29	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188684048	39537	0	0
T21	1662	7	0	0
T38	1807	27	0	0
T40	753	0	0	0
T41	0	4	0	0
T180	8089	122	0	0
T181	2201	0	0	0
T184	1733	11	0	0
T185	0	36	0	0
T186	943	0	0	0
T187	2229	12	0	0
T188	22405	263	0	0
T189	0	18	0	0
T190	0	22	0	0
T194	1276	0	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188684048	41386	0	0
T21	1662	23	0	0
T38	1807	26	0	0
T40	753	0	0	0
T180	8089	64	0	0
T181	2201	0	0	0
T184	1733	19	0	0
T185	0	51	0	0
T186	943	0	0	0
T187	2229	23	0	0
T188	22405	249	0	0
T189	0	2	0	0
T190	0	7	0	0
T194	1276	0	0	0
T197	0	137	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188684048	42214	0	0
T21	1662	22	0	0
T38	1807	11	0	0
T40	753	0	0	0
T180	8089	82	0	0
T181	2201	0	0	0
T184	1733	20	0	0
T185	0	40	0	0
T186	943	0	0	0
T187	2229	17	0	0
T188	22405	266	0	0
T189	0	7	0	0
T190	0	19	0	0
T191	0	7	0	0
T194	1276	0	0	0