Unified Coverage Report :: Module :: edn

Module : edn

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	94.44		83.33	100.00			100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.34	99.02	92.39	96.79	91.45	98.62	99.77

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
edn_csr_assert	100.00						100.00
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_edn_core	91.67	99.92	89.68	70.79	91.45	99.29	98.91
u_edn_cov_if	25.00	50.00	0.00
u_reg	98.63	96.98	98.92	100.00		97.26	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Cond Coverage for Module : edn

	Total	Covered	Percent
Conditions	6	5	83.33
Logical	6	5	83.33
Non-Logical	0	0
Event	0	0

 LINE       99
 EXPRESSION (alert[0] || intg_err_alert[0])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T14,T15,T16

 LINE       99
 EXPRESSION (alert[1] || intg_err_alert[1])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T22,T23,T24
1	0	Covered	T2,T25,T6

---

Toggle Coverage for Module : edn

	Total	Covered	Percent
Totals	69	69	100.00
Total Bits	1168	1168	100.00
Total Bits 0->1	584	584	100.00
Total Bits 1->0	584	584	100.00

Ports	69	69	100.00
Port Bits	1168	1168	100.00
Port Bits 0->1	584	584	100.00
Port Bits 1->0	584	584	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T4,T21	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T17	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T17,T4	Yes	T1,T17,T4	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T3,T17	Yes	T1,T3,T17	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T21,T26,T27	Yes	T21,T26,T27	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i[0].edn_req	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
edn_i[1].edn_req	Yes	Yes	T19,T28,T29	Yes	T19,T28,T29	INPUT
edn_i[2].edn_req	Yes	Yes	T19,T20,T28	Yes	T19,T20,T28	INPUT
edn_i[3].edn_req	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	INPUT
edn_i[4].edn_req	Yes	Yes	T17,T19,T20	Yes	T17,T19,T20	INPUT
edn_i[5].edn_req	Yes	Yes	T19,T20,T28	Yes	T19,T20,T28	INPUT
edn_i[6].edn_req	Yes	Yes	T1,T18,T19	Yes	T1,T18,T19	INPUT
edn_o[0].edn_bus[31:0]	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	OUTPUT
edn_o[0].edn_fips	Yes	Yes	T4,T5,T28	Yes	T3,T4,T19	OUTPUT
edn_o[0].edn_ack	Yes	Yes	T3,T4,T14	Yes	T3,T4,T14	OUTPUT
edn_o[1].edn_bus[31:0]	Yes	Yes	T19,T28,T29	Yes	T19,T28,T29	OUTPUT
edn_o[1].edn_fips	Yes	Yes	T30,T31,T8	Yes	T28,T29,T30	OUTPUT
edn_o[1].edn_ack	Yes	Yes	T19,T28,T29	Yes	T19,T28,T29	OUTPUT
edn_o[2].edn_bus[31:0]	Yes	Yes	T19,T20,T30	Yes	T19,T20,T28	OUTPUT
edn_o[2].edn_fips	Yes	Yes	T19,T32,T33	Yes	T19,T20,T28	OUTPUT
edn_o[2].edn_ack	Yes	Yes	T19,T20,T28	Yes	T19,T20,T28	OUTPUT
edn_o[3].edn_bus[31:0]	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	OUTPUT
edn_o[3].edn_fips	Yes	Yes	T18,T20,T34	Yes	T18,T19,T20	OUTPUT
edn_o[3].edn_ack	Yes	Yes	T18,T19,T20	Yes	T18,T19,T20	OUTPUT
edn_o[4].edn_bus[31:0]	Yes	Yes	T19,T35,T28	Yes	T19,T35,T36	OUTPUT
edn_o[4].edn_fips	Yes	Yes	T19,T30,T31	Yes	T19,T28,T30	OUTPUT
edn_o[4].edn_ack	Yes	Yes	T17,T19,T20	Yes	T17,T19,T20	OUTPUT
edn_o[5].edn_bus[31:0]	Yes	Yes	T19,T20,T28	Yes	T19,T20,T28	OUTPUT
edn_o[5].edn_fips	Yes	Yes	T19,T20,T30	Yes	T19,T20,T28	OUTPUT
edn_o[5].edn_ack	Yes	Yes	T19,T20,T28	Yes	T19,T20,T28	OUTPUT
edn_o[6].edn_bus[31:0]	Yes	Yes	T1,T28,T30	Yes	T1,T18,T19	OUTPUT
edn_o[6].edn_fips	Yes	Yes	T1,T8,T37	Yes	T1,T34,T32	OUTPUT
edn_o[6].edn_ack	Yes	Yes	T1,T18,T19	Yes	T1,T18,T19	OUTPUT
csrng_cmd_o.genbits_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_i.genbits_bus[127:0]	Yes	Yes	T1,T18,T19	Yes	T1,T17,T4	INPUT
csrng_cmd_i.genbits_fips	Yes	Yes	T1,T18,T19	Yes	T1,T17,T18	INPUT
csrng_cmd_i.genbits_valid	Yes	Yes	T1,T3,T17	Yes	T1,T3,T17	INPUT
csrng_cmd_i.csrng_rsp_sts	Yes	Yes	T1,T3,T17	Yes	T1,T3,T17	INPUT
csrng_cmd_i.csrng_rsp_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_req_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T14,T21,T27	Yes	T14,T21,T27	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T2,T27,T38	Yes	T2,T27,T38	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T14,T21,T27	Yes	T14,T21,T27	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T2,T27,T38	Yes	T2,T27,T38	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T39,T40,T41	Yes	T39,T40,T41	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T39,T40,T42	Yes	T39,T40,T42	OUTPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Module : edn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	43	43	100.00	43	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	43	43	100.00	43	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnownO_A	188159295	188014059	0	0
CsrngAppIfOut_A	188159295	188014059	0	0
FpvSecCmCntAlertCheck_A	188159295	117	0	0
FpvSecCmMainFsmCheck_A	188159295	70	0	0
FpvSecCmRegWeOnehotCheck_A	188159295	70	0	0
IntrEdnCmdReqDoneKnownO_A	188159295	188014059	0	0
TlAReadyKnownO_A	188159295	188014059	0	0
TlDValidKnownO_A	188159295	188014059	0	0
gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A	188159295	70	0	0
gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A	188159295	70	0	0
gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A	188159295	70	0	0
gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A	188159295	70	0	0
gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A	188159295	70	0	0
gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A	188159295	70	0	0
gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A	188159295	70	0	0
gen_edn_if_asserts[0].EdnDataStableDisable_A	188159295	502663	0	0
gen_edn_if_asserts[0].EdnDataStable_A	188159295	73377	0	340
gen_edn_if_asserts[0].EdnEndPointOut_A	188159295	188014059	0	0
gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A	188159295	117866	0	0
gen_edn_if_asserts[1].EdnDataStableDisable_A	188159295	502663	0	0
gen_edn_if_asserts[1].EdnDataStable_A	188159295	6328	0	108
gen_edn_if_asserts[1].EdnEndPointOut_A	188159295	188014059	0	0
gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A	188159295	117866	0	0
gen_edn_if_asserts[2].EdnDataStableDisable_A	188159295	502663	0	0
gen_edn_if_asserts[2].EdnDataStable_A	188159295	53430	0	107
gen_edn_if_asserts[2].EdnEndPointOut_A	188159295	188014059	0	0
gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A	188159295	117866	0	0
gen_edn_if_asserts[3].EdnDataStableDisable_A	188159295	502663	0	0
gen_edn_if_asserts[3].EdnDataStable_A	188159295	2175	0	108
gen_edn_if_asserts[3].EdnEndPointOut_A	188159295	188014059	0	0
gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A	188159295	117866	0	0
gen_edn_if_asserts[4].EdnDataStableDisable_A	188159295	502663	0	0
gen_edn_if_asserts[4].EdnDataStable_A	188159295	3476	0	96
gen_edn_if_asserts[4].EdnEndPointOut_A	188159295	188014059	0	0
gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A	188159295	117866	0	0
gen_edn_if_asserts[5].EdnDataStableDisable_A	188159295	502663	0	0
gen_edn_if_asserts[5].EdnDataStable_A	188159295	3779	0	83
gen_edn_if_asserts[5].EdnEndPointOut_A	188159295	188014059	0	0
gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A	188159295	117866	0	0
gen_edn_if_asserts[6].EdnDataStableDisable_A	188159295	502663	0	0
gen_edn_if_asserts[6].EdnDataStable_A	188159295	3082	0	66
gen_edn_if_asserts[6].EdnEndPointOut_A	188159295	188014059	0	0
gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A	188159295	117866	0	0

AlertTxKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188159295	188014059	0	0
T1	1409	1327	0	0
T2	2514	2396	0	0
T3	992	915	0	0
T4	7488	7178	0	0
T5	376093	376080	0	0
T14	1825	1725	0	0
T17	1106	1010	0	0
T18	1392	1299	0	0
T19	1588	1536	0	0
T20	1552	1489	0	0

CsrngAppIfOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188159295	188014059	0	0
T1	1409	1327	0	0
T2	2514	2396	0	0
T3	992	915	0	0
T4	7488	7178	0	0
T5	376093	376080	0	0
T14	1825	1725	0	0
T17	1106	1010	0	0
T18	1392	1299	0	0
T19	1588	1536	0	0
T20	1552	1489	0	0

FpvSecCmCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188159295	117	0	0
T2	2514	1	0	0
T3	992	0	0	0
T4	7488	0	0	0
T7	0	1	0	0
T12	1148	1	0	0
T13	0	1	0	0
T14	1825	0	0	0
T17	1106	0	0	0
T18	1392	0	0	0
T19	1588	0	0	0
T20	1552	0	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	1616	0	0	0

FpvSecCmMainFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188159295	70	0	0
T22	15858	10	0	0
T23	0	10	0	0
T24	0	10	0	0
T50	0	20	0	0
T51	0	20	0	0
T52	1378	0	0	0
T53	7382	0	0	0
T54	1419	0	0	0
T55	1197	0	0	0
T56	1638	0	0	0
T57	332901	0	0	0
T58	2369	0	0	0
T59	7317	0	0	0
T60	6696	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188159295	70	0	0
T22	15858	10	0	0
T23	0	10	0	0
T24	0	10	0	0
T50	0	20	0	0
T51	0	20	0	0
T52	1378	0	0	0
T53	7382	0	0	0
T54	1419	0	0	0
T55	1197	0	0	0
T56	1638	0	0	0
T57	332901	0	0	0
T58	2369	0	0	0
T59	7317	0	0	0
T60	6696	0	0	0

IntrEdnCmdReqDoneKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188159295	188014059	0	0
T1	1409	1327	0	0
T2	2514	2396	0	0
T3	992	915	0	0
T4	7488	7178	0	0
T5	376093	376080	0	0
T14	1825	1725	0	0
T17	1106	1010	0	0
T18	1392	1299	0	0
T19	1588	1536	0	0
T20	1552	1489	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188159295	188014059	0	0
T1	1409	1327	0	0
T2	2514	2396	0	0
T3	992	915	0	0
T4	7488	7178	0	0
T5	376093	376080	0	0
T14	1825	1725	0	0
T17	1106	1010	0	0
T18	1392	1299	0	0
T19	1588	1536	0	0
T20	1552	1489	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188159295	188014059	0	0
T1	1409	1327	0	0
T2	2514	2396	0	0
T3	992	915	0	0
T4	7488	7178	0	0
T5	376093	376080	0	0
T14	1825	1725	0	0
T17	1106	1010	0	0
T18	1392	1299	0	0
T19	1588	1536	0	0
T20	1552	1489	0	0

gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188159295	70	0	0
T22	15858	10	0	0
T23	0	10	0	0
T24	0	10	0	0
T50	0	20	0	0
T51	0	20	0	0
T52	1378	0	0	0
T53	7382	0	0	0
T54	1419	0	0	0
T55	1197	0	0	0
T56	1638	0	0	0
T57	332901	0	0	0
T58	2369	0	0	0
T59	7317	0	0	0
T60	6696	0	0	0

gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188159295	70	0	0
T22	15858	10	0	0
T23	0	10	0	0
T24	0	10	0	0
T50	0	20	0	0
T51	0	20	0	0
T52	1378	0	0	0
T53	7382	0	0	0
T54	1419	0	0	0
T55	1197	0	0	0
T56	1638	0	0	0
T57	332901	0	0	0
T58	2369	0	0	0
T59	7317	0	0	0
T60	6696	0	0	0

gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188159295	70	0	0
T22	15858	10	0	0
T23	0	10	0	0
T24	0	10	0	0
T50	0	20	0	0
T51	0	20	0	0
T52	1378	0	0	0
T53	7382	0	0	0
T54	1419	0	0	0
T55	1197	0	0	0
T56	1638	0	0	0
T57	332901	0	0	0
T58	2369	0	0	0
T59	7317	0	0	0
T60	6696	0	0	0

gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188159295	70	0	0
T22	15858	10	0	0
T23	0	10	0	0
T24	0	10	0	0
T50	0	20	0	0
T51	0	20	0	0
T52	1378	0	0	0
T53	7382	0	0	0
T54	1419	0	0	0
T55	1197	0	0	0
T56	1638	0	0	0
T57	332901	0	0	0
T58	2369	0	0	0
T59	7317	0	0	0
T60	6696	0	0	0

gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188159295	70	0	0
T22	15858	10	0	0
T23	0	10	0	0
T24	0	10	0	0
T50	0	20	0	0
T51	0	20	0	0
T52	1378	0	0	0
T53	7382	0	0	0
T54	1419	0	0	0
T55	1197	0	0	0
T56	1638	0	0	0
T57	332901	0	0	0
T58	2369	0	0	0
T59	7317	0	0	0
T60	6696	0	0	0

gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188159295	70	0	0
T22	15858	10	0	0
T23	0	10	0	0
T24	0	10	0	0
T50	0	20	0	0
T51	0	20	0	0
T52	1378	0	0	0
T53	7382	0	0	0
T54	1419	0	0	0
T55	1197	0	0	0
T56	1638	0	0	0
T57	332901	0	0	0
T58	2369	0	0	0
T59	7317	0	0	0
T60	6696	0	0	0

gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188159295	70	0	0
T22	15858	10	0	0
T23	0	10	0	0
T24	0	10	0	0
T50	0	20	0	0
T51	0	20	0	0
T52	1378	0	0	0
T53	7382	0	0	0
T54	1419	0	0	0
T55	1197	0	0	0
T56	1638	0	0	0
T57	332901	0	0	0
T58	2369	0	0	0
T59	7317	0	0	0
T60	6696	0	0	0

gen_edn_if_asserts[0].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188159295	502663	0	0
T1	1409	13	0	0
T2	2514	1678	0	0
T3	992	75	0	0
T4	7488	68	0	0
T5	376093	1677	0	0
T14	1825	201	0	0
T17	1106	65	0	0
T18	1392	19	0	0
T19	1588	12	0	0
T20	1552	52	0	0

gen_edn_if_asserts[0].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188159295	73377	0	340
T3	992	3	0	1
T4	7488	6	0	0
T5	376093	96	0	0
T14	1825	4	0	1
T15	0	4	0	1
T17	1106	0	0	0
T18	1392	0	0	0
T19	1588	23	0	1
T20	1552	3	0	1
T28	0	42	0	1
T30	0	5	0	1
T35	1274	0	0	0
T61	1228	3	0	1
T62	0	0	0	1
T63	0	0	0	1

gen_edn_if_asserts[0].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188159295	188014059	0	0
T1	1409	1327	0	0
T2	2514	2396	0	0
T3	992	915	0	0
T4	7488	7178	0	0
T5	376093	376080	0	0
T14	1825	1725	0	0
T17	1106	1010	0	0
T18	1392	1299	0	0
T19	1588	1536	0	0
T20	1552	1489	0	0

gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188159295	117866	0	0
T2	2514	1132	0	0
T3	992	0	0	0
T4	7488	0	0	0
T6	0	405	0	0
T7	0	614	0	0
T12	0	580	0	0
T13	0	1110	0	0
T14	1825	0	0	0
T17	1106	0	0	0
T18	1392	0	0	0
T19	1588	0	0	0
T20	1552	0	0	0
T25	503	245	0	0
T64	0	15	0	0
T65	0	352	0	0
T66	0	666	0	0
T67	0	420	0	0
T68	1943	0	0	0

gen_edn_if_asserts[1].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188159295	502663	0	0
T1	1409	13	0	0
T2	2514	1678	0	0
T3	992	75	0	0
T4	7488	68	0	0
T5	376093	1677	0	0
T14	1825	201	0	0
T17	1106	65	0	0
T18	1392	19	0	0
T19	1588	12	0	0
T20	1552	52	0	0

gen_edn_if_asserts[1].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188159295	6328	0	108
T8	0	50	0	1
T9	0	30	0	1
T16	1342	0	0	0
T19	1588	3	0	1
T20	1552	0	0	0
T25	503	0	0	0
T28	1645	3	0	1
T29	1608	19	0	1
T30	1779	25	0	1
T31	0	18	0	1
T33	0	21	0	1
T34	0	3	0	1
T62	1264	0	0	0
T63	1680	0	0	0
T69	0	3	0	1
T70	1235	0	0	0

gen_edn_if_asserts[1].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188159295	188014059	0	0
T1	1409	1327	0	0
T2	2514	2396	0	0
T3	992	915	0	0
T4	7488	7178	0	0
T5	376093	376080	0	0
T14	1825	1725	0	0
T17	1106	1010	0	0
T18	1392	1299	0	0
T19	1588	1536	0	0
T20	1552	1489	0	0

gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188159295	117866	0	0
T2	2514	1132	0	0
T3	992	0	0	0
T4	7488	0	0	0
T6	0	405	0	0
T7	0	614	0	0
T12	0	580	0	0
T13	0	1110	0	0
T14	1825	0	0	0
T17	1106	0	0	0
T18	1392	0	0	0
T19	1588	0	0	0
T20	1552	0	0	0
T25	503	245	0	0
T64	0	15	0	0
T65	0	352	0	0
T66	0	666	0	0
T67	0	420	0	0
T68	1943	0	0	0

gen_edn_if_asserts[2].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188159295	502663	0	0
T1	1409	13	0	0
T2	2514	1678	0	0
T3	992	75	0	0
T4	7488	68	0	0
T5	376093	1677	0	0
T14	1825	201	0	0
T17	1106	65	0	0
T18	1392	19	0	0
T19	1588	12	0	0
T20	1552	52	0	0

gen_edn_if_asserts[2].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188159295	53430	0	107
T8	0	3	0	1
T16	1342	0	0	0
T19	1588	31	0	1
T20	1552	12	0	1
T25	503	0	0	0
T28	1645	3	0	1
T29	1608	0	0	0
T30	1779	3	0	1
T31	0	11	0	1
T32	0	7	0	1
T33	0	41	0	1
T34	0	3	0	1
T62	1264	0	0	0
T63	1680	0	0	0
T70	1235	0	0	0
T71	0	13	0	1

gen_edn_if_asserts[2].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188159295	188014059	0	0
T1	1409	1327	0	0
T2	2514	2396	0	0
T3	992	915	0	0
T4	7488	7178	0	0
T5	376093	376080	0	0
T14	1825	1725	0	0
T17	1106	1010	0	0
T18	1392	1299	0	0
T19	1588	1536	0	0
T20	1552	1489	0	0

gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188159295	117866	0	0
T2	2514	1132	0	0
T3	992	0	0	0
T4	7488	0	0	0
T6	0	405	0	0
T7	0	614	0	0
T12	0	580	0	0
T13	0	1110	0	0
T14	1825	0	0	0
T17	1106	0	0	0
T18	1392	0	0	0
T19	1588	0	0	0
T20	1552	0	0	0
T25	503	245	0	0
T64	0	15	0	0
T65	0	352	0	0
T66	0	666	0	0
T67	0	420	0	0
T68	1943	0	0	0

gen_edn_if_asserts[3].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188159295	502663	0	0
T1	1409	13	0	0
T2	2514	1678	0	0
T3	992	75	0	0
T4	7488	68	0	0
T5	376093	1677	0	0
T14	1825	201	0	0
T17	1106	65	0	0
T18	1392	19	0	0
T19	1588	12	0	0
T20	1552	52	0	0

gen_edn_if_asserts[3].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188159295	2175	0	108
T14	1825	0	0	0
T16	1342	0	0	0
T18	1392	62	0	1
T19	1588	3	0	1
T20	1552	39	0	1
T28	1645	3	0	1
T29	1608	3	0	1
T30	1779	3	0	1
T31	0	5	0	1
T32	0	49	0	1
T34	0	30	0	1
T62	1264	0	0	0
T70	1235	0	0	0
T72	0	3	0	1

gen_edn_if_asserts[3].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188159295	188014059	0	0
T1	1409	1327	0	0
T2	2514	2396	0	0
T3	992	915	0	0
T4	7488	7178	0	0
T5	376093	376080	0	0
T14	1825	1725	0	0
T17	1106	1010	0	0
T18	1392	1299	0	0
T19	1588	1536	0	0
T20	1552	1489	0	0

gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188159295	117866	0	0
T2	2514	1132	0	0
T3	992	0	0	0
T4	7488	0	0	0
T6	0	405	0	0
T7	0	614	0	0
T12	0	580	0	0
T13	0	1110	0	0
T14	1825	0	0	0
T17	1106	0	0	0
T18	1392	0	0	0
T19	1588	0	0	0
T20	1552	0	0	0
T25	503	245	0	0
T64	0	15	0	0
T65	0	352	0	0
T66	0	666	0	0
T67	0	420	0	0
T68	1943	0	0	0

gen_edn_if_asserts[4].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188159295	502663	0	0
T1	1409	13	0	0
T2	2514	1678	0	0
T3	992	75	0	0
T4	7488	68	0	0
T5	376093	1677	0	0
T14	1825	201	0	0
T17	1106	65	0	0
T18	1392	19	0	0
T19	1588	12	0	0
T20	1552	52	0	0

gen_edn_if_asserts[4].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188159295	3476	0	96
T4	7488	0	0	0
T8	0	0	0	1
T9	0	0	0	1
T14	1825	0	0	0
T15	1480	0	0	0
T16	0	4	0	1
T17	1106	3	0	0
T18	1392	0	0	0
T19	1588	36	0	1
T20	1552	3	0	1
T28	0	3	0	1
T30	0	35	0	1
T31	0	26	0	1
T32	0	6	0	1
T35	1274	3	0	0
T36	0	3	0	1
T61	1228	0	0	0
T73	1027	0	0	0

gen_edn_if_asserts[4].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188159295	188014059	0	0
T1	1409	1327	0	0
T2	2514	2396	0	0
T3	992	915	0	0
T4	7488	7178	0	0
T5	376093	376080	0	0
T14	1825	1725	0	0
T17	1106	1010	0	0
T18	1392	1299	0	0
T19	1588	1536	0	0
T20	1552	1489	0	0

gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188159295	117866	0	0
T2	2514	1132	0	0
T3	992	0	0	0
T4	7488	0	0	0
T6	0	405	0	0
T7	0	614	0	0
T12	0	580	0	0
T13	0	1110	0	0
T14	1825	0	0	0
T17	1106	0	0	0
T18	1392	0	0	0
T19	1588	0	0	0
T20	1552	0	0	0
T25	503	245	0	0
T64	0	15	0	0
T65	0	352	0	0
T66	0	666	0	0
T67	0	420	0	0
T68	1943	0	0	0

gen_edn_if_asserts[5].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188159295	502663	0	0
T1	1409	13	0	0
T2	2514	1678	0	0
T3	992	75	0	0
T4	7488	68	0	0
T5	376093	1677	0	0
T14	1825	201	0	0
T17	1106	65	0	0
T18	1392	19	0	0
T19	1588	12	0	0
T20	1552	52	0	0

gen_edn_if_asserts[5].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188159295	3779	0	83
T8	0	7	0	1
T16	1342	0	0	0
T19	1588	30	0	1
T20	1552	41	0	1
T25	503	0	0	0
T28	1645	3	0	1
T29	1608	0	0	0
T30	1779	44	0	1
T32	0	7	0	1
T33	0	12	0	1
T34	0	47	0	1
T62	1264	0	0	0
T63	1680	0	0	0
T70	1235	0	0	0
T74	0	57	0	1
T75	0	21	0	1

gen_edn_if_asserts[5].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188159295	188014059	0	0
T1	1409	1327	0	0
T2	2514	2396	0	0
T3	992	915	0	0
T4	7488	7178	0	0
T5	376093	376080	0	0
T14	1825	1725	0	0
T17	1106	1010	0	0
T18	1392	1299	0	0
T19	1588	1536	0	0
T20	1552	1489	0	0

gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188159295	117866	0	0
T2	2514	1132	0	0
T3	992	0	0	0
T4	7488	0	0	0
T6	0	405	0	0
T7	0	614	0	0
T12	0	580	0	0
T13	0	1110	0	0
T14	1825	0	0	0
T17	1106	0	0	0
T18	1392	0	0	0
T19	1588	0	0	0
T20	1552	0	0	0
T25	503	245	0	0
T64	0	15	0	0
T65	0	352	0	0
T66	0	666	0	0
T67	0	420	0	0
T68	1943	0	0	0

gen_edn_if_asserts[6].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188159295	502663	0	0
T1	1409	13	0	0
T2	2514	1678	0	0
T3	992	75	0	0
T4	7488	68	0	0
T5	376093	1677	0	0
T14	1825	201	0	0
T17	1106	65	0	0
T18	1392	19	0	0
T19	1588	12	0	0
T20	1552	52	0	0

gen_edn_if_asserts[6].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188159295	3082	0	66
T1	1409	63	0	1
T2	2514	0	0	0
T3	992	0	0	0
T4	7488	0	0	0
T8	0	350	0	1
T14	1825	0	0	0
T17	1106	0	0	0
T18	1392	3	0	1
T19	1588	3	0	1
T20	1552	0	0	0
T28	1645	3	0	1
T30	0	3	0	1
T32	0	11	0	1
T34	0	3	0	1
T37	0	56	0	1
T76	0	3	0	0
T77	0	0	0	1

gen_edn_if_asserts[6].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188159295	188014059	0	0
T1	1409	1327	0	0
T2	2514	2396	0	0
T3	992	915	0	0
T4	7488	7178	0	0
T5	376093	376080	0	0
T14	1825	1725	0	0
T17	1106	1010	0	0
T18	1392	1299	0	0
T19	1588	1536	0	0
T20	1552	1489	0	0

gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	188159295	117866	0	0
T2	2514	1132	0	0
T3	992	0	0	0
T4	7488	0	0	0
T6	0	405	0	0
T7	0	614	0	0
T12	0	580	0	0
T13	0	1110	0	0
T14	1825	0	0	0
T17	1106	0	0	0
T18	1392	0	0	0
T19	1588	0	0	0
T20	1552	0	0	0
T25	503	245	0	0
T64	0	15	0	0
T65	0	352	0	0
T66	0	666	0	0
T67	0	420	0	0
T68	1943	0	0	0