Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44		83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	220623868	10792665	0	0
boot_gen_cmd_rd_A	220623868	40406	0	0
boot_ins_cmd_rd_A	220623868	45775	0	0
ctrl_rd_A	220623868	40575	0	0
err_code_test_rd_A	220623868	40372	0	0
intr_enable_rd_A	220623868	42930	0	0
max_num_reqs_between_reseeds_rd_A	220623868	46644	0	0
regwen_rd_A	220623868	45451	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220623868	10792665	0	0
T25	11115	816	0	0
T26	1911	153	0	0
T27	2522	49	0	0
T109	4876	6	0	0
T151	7395	8	0	0
T152	1819	16	0	0
T153	4168	346	0	0
T154	4693	382	0	0
T155	0	4	0	0
T156	0	346	0	0
T157	1424	0	0	0
T158	897	0	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220623868	40406	0	0
T25	11115	9	0	0
T27	2522	14	0	0
T36	1279	0	0	0
T152	1819	2	0	0
T159	1711	11	0	0
T160	3503	52	0	0
T161	2000	8	0	0
T162	0	12	0	0
T163	0	20	0	0
T164	0	4	0	0
T165	0	9	0	0
T166	1730	0	0	0
T167	1275	0	0	0
T168	1374	0	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220623868	45775	0	0
T25	11115	1	0	0
T27	2522	8	0	0
T36	1279	0	0	0
T152	1819	9	0	0
T159	1711	16	0	0
T160	3503	51	0	0
T161	2000	3	0	0
T162	0	13	0	0
T163	0	10	0	0
T165	0	12	0	0
T166	1730	0	0	0
T167	1275	0	0	0
T168	1374	0	0	0
T169	0	6	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220623868	40575	0	0
T25	11115	16	0	0
T36	1279	0	0	0
T152	1819	10	0	0
T159	1711	7	0	0
T160	3503	23	0	0
T161	2000	8	0	0
T162	5800	19	0	0
T163	0	5	0	0
T164	0	7	0	0
T165	0	3	0	0
T166	1730	0	0	0
T167	1275	0	0	0
T168	1374	0	0	0
T170	0	7	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220623868	40372	0	0
T25	11115	13	0	0
T27	2522	4	0	0
T36	1279	0	0	0
T152	1819	6	0	0
T159	1711	2	0	0
T160	3503	43	0	0
T161	2000	5	0	0
T162	0	11	0	0
T163	0	22	0	0
T164	0	8	0	0
T166	1730	0	0	0
T167	1275	0	0	0
T168	1374	0	0	0
T171	0	3	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220623868	42930	0	0
T5	7769	43	0	0
T9	1861	0	0	0
T14	2943	0	0	0
T19	1089	0	0	0
T20	1512	0	0	0
T21	1066	0	0	0
T25	11115	7	0	0
T27	2522	13	0	0
T36	0	28	0	0
T152	1819	11	0	0
T155	3838	53	0	0
T159	0	6	0	0
T160	0	56	0	0
T161	0	11	0	0
T168	0	8	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220623868	46644	0	0
T25	11115	3	0	0
T36	1279	0	0	0
T152	1819	3	0	0
T155	3838	23	0	0
T156	5096	0	0	0
T158	897	5	0	0
T159	1711	23	0	0
T160	3503	31	0	0
T161	0	23	0	0
T162	0	2	0	0
T166	1730	0	0	0
T167	1275	0	0	0
T168	0	6	0	0
T172	0	33	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220623868	45451	0	0
T25	11115	17	0	0
T27	2522	9	0	0
T36	1279	0	0	0
T152	1819	11	0	0
T155	3838	14	0	0
T156	5096	0	0	0
T158	897	7	0	0
T159	1711	11	0	0
T160	3503	50	0	0
T161	0	12	0	0
T162	0	29	0	0
T166	1730	0	0	0
T168	0	7	0	0