Unified Coverage Report :: Module :: edn

Module : edn

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	94.44		83.33	100.00			100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.34	99.02	92.39	96.79	91.45	98.62	99.77

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
edn_csr_assert	100.00						100.00
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_edn_core	91.67	99.92	89.68	70.79	91.45	99.29	98.91
u_edn_cov_if	25.00	50.00	0.00
u_reg	98.63	96.98	98.92	100.00		97.26	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Cond Coverage for Module : edn

	Total	Covered	Percent
Conditions	6	5	83.33
Logical	6	5	83.33
Non-Logical	0	0
Event	0	0

 LINE       99
 EXPRESSION (alert[0] || intg_err_alert[0])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T16,T17,T18

 LINE       99
 EXPRESSION (alert[1] || intg_err_alert[1])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T22,T23,T24
1	0	Covered	T2,T4,T21

---

Toggle Coverage for Module : edn

	Total	Covered	Percent
Totals	69	69	100.00
Total Bits	1168	1168	100.00
Total Bits 0->1	584	584	100.00
Total Bits 1->0	584	584	100.00

Ports	69	69	100.00
Port Bits	1168	1168	100.00
Port Bits 0->1	584	584	100.00
Port Bits 1->0	584	584	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T4,T5	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T3,T5	Yes	T1,T3,T5	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T25,T26,T27	Yes	T25,T26,T27	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T5,T19	Yes	T1,T5,T19	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T4	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i[0].edn_req	Yes	Yes	T2,T5,T19	Yes	T2,T5,T19	INPUT
edn_i[1].edn_req	Yes	Yes	T1,T4,T11	Yes	T1,T4,T11	INPUT
edn_i[2].edn_req	Yes	Yes	T1,T11,T28	Yes	T1,T11,T28	INPUT
edn_i[3].edn_req	Yes	Yes	T14,T11,T28	Yes	T14,T11,T28	INPUT
edn_i[4].edn_req	Yes	Yes	T1,T11,T28	Yes	T1,T11,T28	INPUT
edn_i[5].edn_req	Yes	Yes	T11,T28,T29	Yes	T11,T28,T29	INPUT
edn_i[6].edn_req	Yes	Yes	T28,T29,T30	Yes	T28,T29,T30	INPUT
edn_o[0].edn_bus[31:0]	Yes	Yes	T5,T19,T9	Yes	T5,T19,T9	OUTPUT
edn_o[0].edn_fips	Yes	Yes	T5,T9,T20	Yes	T5,T19,T9	OUTPUT
edn_o[0].edn_ack	Yes	Yes	T5,T19,T9	Yes	T5,T19,T9	OUTPUT
edn_o[1].edn_bus[31:0]	Yes	Yes	T1,T11,T28	Yes	T1,T11,T28	OUTPUT
edn_o[1].edn_fips	Yes	Yes	T11,T28,T31	Yes	T1,T11,T28	OUTPUT
edn_o[1].edn_ack	Yes	Yes	T1,T11,T28	Yes	T1,T11,T28	OUTPUT
edn_o[2].edn_bus[31:0]	Yes	Yes	T1,T11,T28	Yes	T1,T11,T28	OUTPUT
edn_o[2].edn_fips	Yes	Yes	T1,T32,T31	Yes	T1,T11,T28	OUTPUT
edn_o[2].edn_ack	Yes	Yes	T1,T11,T28	Yes	T1,T11,T28	OUTPUT
edn_o[3].edn_bus[31:0]	Yes	Yes	T11,T29,T33	Yes	T11,T29,T33	OUTPUT
edn_o[3].edn_fips	Yes	Yes	T29,T31,T34	Yes	T28,T29,T33	OUTPUT
edn_o[3].edn_ack	Yes	Yes	T11,T28,T29	Yes	T11,T28,T29	OUTPUT
edn_o[4].edn_bus[31:0]	Yes	Yes	T1,T28,T29	Yes	T1,T11,T28	OUTPUT
edn_o[4].edn_fips	Yes	Yes	T1,T28,T29	Yes	T1,T28,T29	OUTPUT
edn_o[4].edn_ack	Yes	Yes	T1,T11,T28	Yes	T1,T11,T28	OUTPUT
edn_o[5].edn_bus[31:0]	Yes	Yes	T11,T28,T29	Yes	T11,T28,T29	OUTPUT
edn_o[5].edn_fips	Yes	Yes	T11,T28,T29	Yes	T11,T28,T29	OUTPUT
edn_o[5].edn_ack	Yes	Yes	T11,T28,T29	Yes	T11,T28,T29	OUTPUT
edn_o[6].edn_bus[31:0]	Yes	Yes	T28,T29,T30	Yes	T28,T29,T30	OUTPUT
edn_o[6].edn_fips	Yes	Yes	T28,T29,T35	Yes	T28,T29,T35	OUTPUT
edn_o[6].edn_ack	Yes	Yes	T28,T29,T30	Yes	T28,T29,T30	OUTPUT
csrng_cmd_o.genbits_ready	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	Yes	Yes	T1,T2,T5	Yes	T1,T2,T5	OUTPUT
csrng_cmd_o.csrng_req_valid	Yes	Yes	T1,T2,T5	Yes	T1,T2,T5	OUTPUT
csrng_cmd_i.genbits_bus[127:0]	Yes	Yes	T1,T5,T19	Yes	T1,T9,T20	INPUT
csrng_cmd_i.genbits_fips	Yes	Yes	T1,T5,T9	Yes	T1,T19,T9	INPUT
csrng_cmd_i.genbits_valid	Yes	Yes	T1,T5,T19	Yes	T1,T5,T19	INPUT
csrng_cmd_i.csrng_rsp_sts	Yes	Yes	T1,T2,T5	Yes	T1,T2,T5	INPUT
csrng_cmd_i.csrng_rsp_ack	Yes	Yes	T1,T2,T5	Yes	T1,T2,T5	INPUT
csrng_cmd_i.csrng_req_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T3,T26,T27	Yes	T3,T26,T27	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T3,T26,T27	Yes	T3,T26,T27	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T5,T36,T37	Yes	T5,T36,T37	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T5,T21,T36	Yes	T5,T21,T36	OUTPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Module : edn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	43	43	100.00	43	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	43	43	100.00	43	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnownO_A	220171838	220020179	0	0
CsrngAppIfOut_A	220171838	220020179	0	0
FpvSecCmCntAlertCheck_A	220171838	134	0	0
FpvSecCmMainFsmCheck_A	220171838	80	0	0
FpvSecCmRegWeOnehotCheck_A	220171838	80	0	0
IntrEdnCmdReqDoneKnownO_A	220171838	220020179	0	0
TlAReadyKnownO_A	220171838	220020179	0	0
TlDValidKnownO_A	220171838	220020179	0	0
gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A	220171838	80	0	0
gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A	220171838	80	0	0
gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A	220171838	80	0	0
gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A	220171838	80	0	0
gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A	220171838	80	0	0
gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A	220171838	80	0	0
gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A	220171838	80	0	0
gen_edn_if_asserts[0].EdnDataStableDisable_A	220171838	510128	0	0
gen_edn_if_asserts[0].EdnDataStable_A	220171838	23316	0	344
gen_edn_if_asserts[0].EdnEndPointOut_A	220171838	220020179	0	0
gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A	220171838	139149	0	0
gen_edn_if_asserts[1].EdnDataStableDisable_A	220171838	510128	0	0
gen_edn_if_asserts[1].EdnDataStable_A	220171838	4310	0	108
gen_edn_if_asserts[1].EdnEndPointOut_A	220171838	220020179	0	0
gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A	220171838	139149	0	0
gen_edn_if_asserts[2].EdnDataStableDisable_A	220171838	510128	0	0
gen_edn_if_asserts[2].EdnDataStable_A	220171838	3277	0	107
gen_edn_if_asserts[2].EdnEndPointOut_A	220171838	220020179	0	0
gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A	220171838	139149	0	0
gen_edn_if_asserts[3].EdnDataStableDisable_A	220171838	510128	0	0
gen_edn_if_asserts[3].EdnDataStable_A	220171838	3193	0	101
gen_edn_if_asserts[3].EdnEndPointOut_A	220171838	220020179	0	0
gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A	220171838	139149	0	0
gen_edn_if_asserts[4].EdnDataStableDisable_A	220171838	510128	0	0
gen_edn_if_asserts[4].EdnDataStable_A	220171838	2557	0	83
gen_edn_if_asserts[4].EdnEndPointOut_A	220171838	220020179	0	0
gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A	220171838	139149	0	0
gen_edn_if_asserts[5].EdnDataStableDisable_A	220171838	510128	0	0
gen_edn_if_asserts[5].EdnDataStable_A	220171838	1749	0	71
gen_edn_if_asserts[5].EdnEndPointOut_A	220171838	220020179	0	0
gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A	220171838	139149	0	0
gen_edn_if_asserts[6].EdnDataStableDisable_A	220171838	510128	0	0
gen_edn_if_asserts[6].EdnDataStable_A	220171838	2826	0	56
gen_edn_if_asserts[6].EdnEndPointOut_A	220171838	220020179	0	0
gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A	220171838	139149	0	0

AlertTxKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220171838	220020179	0	0
T1	1866	1789	0	0
T2	645	524	0	0
T3	1169	1079	0	0
T4	1926	1734	0	0
T5	7769	7320	0	0
T9	1861	1780	0	0
T14	2943	2802	0	0
T19	1089	1028	0	0
T20	1512	1456	0	0
T21	1066	911	0	0

CsrngAppIfOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220171838	220020179	0	0
T1	1866	1789	0	0
T2	645	524	0	0
T3	1169	1079	0	0
T4	1926	1734	0	0
T5	7769	7320	0	0
T9	1861	1780	0	0
T14	2943	2802	0	0
T19	1089	1028	0	0
T20	1512	1456	0	0
T21	1066	911	0	0

FpvSecCmCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220171838	134	0	0
T2	645	1	0	0
T3	1169	0	0	0
T4	1926	0	0	0
T5	7769	0	0	0
T9	1861	0	0	0
T14	2943	1	0	0
T15	704	1	0	0
T19	1089	0	0	0
T20	1512	0	0	0
T21	1066	0	0	0
T22	0	20	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0

FpvSecCmMainFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220171838	80	0	0
T22	36299	20	0	0
T23	31764	20	0	0
T24	0	10	0	0
T44	0	20	0	0
T45	0	10	0	0
T46	1632	0	0	0
T47	1215	0	0	0
T48	739	0	0	0
T49	1845	0	0	0
T50	1692	0	0	0
T51	1828	0	0	0
T52	3755	0	0	0
T53	3369	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220171838	80	0	0
T22	36299	20	0	0
T23	31764	20	0	0
T24	0	10	0	0
T44	0	20	0	0
T45	0	10	0	0
T46	1632	0	0	0
T47	1215	0	0	0
T48	739	0	0	0
T49	1845	0	0	0
T50	1692	0	0	0
T51	1828	0	0	0
T52	3755	0	0	0
T53	3369	0	0	0

IntrEdnCmdReqDoneKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220171838	220020179	0	0
T1	1866	1789	0	0
T2	645	524	0	0
T3	1169	1079	0	0
T4	1926	1734	0	0
T5	7769	7320	0	0
T9	1861	1780	0	0
T14	2943	2802	0	0
T19	1089	1028	0	0
T20	1512	1456	0	0
T21	1066	911	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220171838	220020179	0	0
T1	1866	1789	0	0
T2	645	524	0	0
T3	1169	1079	0	0
T4	1926	1734	0	0
T5	7769	7320	0	0
T9	1861	1780	0	0
T14	2943	2802	0	0
T19	1089	1028	0	0
T20	1512	1456	0	0
T21	1066	911	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220171838	220020179	0	0
T1	1866	1789	0	0
T2	645	524	0	0
T3	1169	1079	0	0
T4	1926	1734	0	0
T5	7769	7320	0	0
T9	1861	1780	0	0
T14	2943	2802	0	0
T19	1089	1028	0	0
T20	1512	1456	0	0
T21	1066	911	0	0

gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220171838	80	0	0
T22	36299	20	0	0
T23	31764	20	0	0
T24	0	10	0	0
T44	0	20	0	0
T45	0	10	0	0
T46	1632	0	0	0
T47	1215	0	0	0
T48	739	0	0	0
T49	1845	0	0	0
T50	1692	0	0	0
T51	1828	0	0	0
T52	3755	0	0	0
T53	3369	0	0	0

gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220171838	80	0	0
T22	36299	20	0	0
T23	31764	20	0	0
T24	0	10	0	0
T44	0	20	0	0
T45	0	10	0	0
T46	1632	0	0	0
T47	1215	0	0	0
T48	739	0	0	0
T49	1845	0	0	0
T50	1692	0	0	0
T51	1828	0	0	0
T52	3755	0	0	0
T53	3369	0	0	0

gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220171838	80	0	0
T22	36299	20	0	0
T23	31764	20	0	0
T24	0	10	0	0
T44	0	20	0	0
T45	0	10	0	0
T46	1632	0	0	0
T47	1215	0	0	0
T48	739	0	0	0
T49	1845	0	0	0
T50	1692	0	0	0
T51	1828	0	0	0
T52	3755	0	0	0
T53	3369	0	0	0

gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220171838	80	0	0
T22	36299	20	0	0
T23	31764	20	0	0
T24	0	10	0	0
T44	0	20	0	0
T45	0	10	0	0
T46	1632	0	0	0
T47	1215	0	0	0
T48	739	0	0	0
T49	1845	0	0	0
T50	1692	0	0	0
T51	1828	0	0	0
T52	3755	0	0	0
T53	3369	0	0	0

gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220171838	80	0	0
T22	36299	20	0	0
T23	31764	20	0	0
T24	0	10	0	0
T44	0	20	0	0
T45	0	10	0	0
T46	1632	0	0	0
T47	1215	0	0	0
T48	739	0	0	0
T49	1845	0	0	0
T50	1692	0	0	0
T51	1828	0	0	0
T52	3755	0	0	0
T53	3369	0	0	0

gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220171838	80	0	0
T22	36299	20	0	0
T23	31764	20	0	0
T24	0	10	0	0
T44	0	20	0	0
T45	0	10	0	0
T46	1632	0	0	0
T47	1215	0	0	0
T48	739	0	0	0
T49	1845	0	0	0
T50	1692	0	0	0
T51	1828	0	0	0
T52	3755	0	0	0
T53	3369	0	0	0

gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220171838	80	0	0
T22	36299	20	0	0
T23	31764	20	0	0
T24	0	10	0	0
T44	0	20	0	0
T45	0	10	0	0
T46	1632	0	0	0
T47	1215	0	0	0
T48	739	0	0	0
T49	1845	0	0	0
T50	1692	0	0	0
T51	1828	0	0	0
T52	3755	0	0	0
T53	3369	0	0	0

gen_edn_if_asserts[0].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220171838	510128	0	0
T1	1866	344	0	0
T2	645	290	0	0
T3	1169	1078	0	0
T4	1926	1092	0	0
T5	7769	3649	0	0
T9	1861	239	0	0
T14	2943	1162	0	0
T19	1089	21	0	0
T20	1512	45	0	0
T21	1066	491	0	0

gen_edn_if_asserts[0].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220171838	23316	0	344
T5	7769	10	0	0
T9	1861	15	0	1
T10	1815	15	0	1
T14	2943	0	0	0
T19	1089	11	0	1
T20	1512	67	0	1
T21	1066	0	0	0
T28	2606	37	0	1
T54	8223	13	0	0
T55	3568	7	0	1
T56	0	19	0	1
T57	0	3	0	1
T58	0	0	0	1
T59	0	0	0	1

gen_edn_if_asserts[0].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220171838	220020179	0	0
T1	1866	1789	0	0
T2	645	524	0	0
T3	1169	1079	0	0
T4	1926	1734	0	0
T5	7769	7320	0	0
T9	1861	1780	0	0
T14	2943	2802	0	0
T19	1089	1028	0	0
T20	1512	1456	0	0
T21	1066	911	0	0

gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220171838	139149	0	0
T2	645	364	0	0
T3	1169	0	0	0
T4	1926	1187	0	0
T5	7769	0	0	0
T6	1531	842	0	0
T7	0	876	0	0
T8	0	1181	0	0
T9	1861	0	0	0
T14	2943	1148	0	0
T15	0	350	0	0
T19	1089	0	0	0
T20	1512	0	0	0
T21	1066	22	0	0
T35	0	7	0	0
T60	0	1093	0	0

gen_edn_if_asserts[1].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220171838	510128	0	0
T1	1866	344	0	0
T2	645	290	0	0
T3	1169	1078	0	0
T4	1926	1092	0	0
T5	7769	3649	0	0
T9	1861	239	0	0
T14	2943	1162	0	0
T19	1089	21	0	0
T20	1512	45	0	0
T21	1066	491	0	0

gen_edn_if_asserts[1].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220171838	4310	0	108
T1	1866	3	0	1
T2	645	0	0	0
T3	1169	0	0	0
T4	1926	0	0	0
T5	7769	0	0	0
T9	1861	0	0	0
T11	0	59	0	1
T14	2943	0	0	0
T19	1089	0	0	0
T20	1512	0	0	0
T21	1066	0	0	0
T28	0	59	0	1
T29	0	3	0	1
T31	0	49	0	1
T34	0	37	0	1
T61	0	4	0	1
T62	0	3	0	1
T63	0	4	0	1
T64	0	3	0	1

gen_edn_if_asserts[1].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220171838	220020179	0	0
T1	1866	1789	0	0
T2	645	524	0	0
T3	1169	1079	0	0
T4	1926	1734	0	0
T5	7769	7320	0	0
T9	1861	1780	0	0
T14	2943	2802	0	0
T19	1089	1028	0	0
T20	1512	1456	0	0
T21	1066	911	0	0

gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220171838	139149	0	0
T2	645	364	0	0
T3	1169	0	0	0
T4	1926	1187	0	0
T5	7769	0	0	0
T6	1531	842	0	0
T7	0	876	0	0
T8	0	1181	0	0
T9	1861	0	0	0
T14	2943	1148	0	0
T15	0	350	0	0
T19	1089	0	0	0
T20	1512	0	0	0
T21	1066	22	0	0
T35	0	7	0	0
T60	0	1093	0	0

gen_edn_if_asserts[2].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220171838	510128	0	0
T1	1866	344	0	0
T2	645	290	0	0
T3	1169	1078	0	0
T4	1926	1092	0	0
T5	7769	3649	0	0
T9	1861	239	0	0
T14	2943	1162	0	0
T19	1089	21	0	0
T20	1512	45	0	0
T21	1066	491	0	0

gen_edn_if_asserts[2].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220171838	3277	0	107
T1	1866	9	0	1
T2	645	0	0	0
T3	1169	0	0	0
T4	1926	0	0	0
T5	7769	0	0	0
T9	1861	0	0	0
T11	0	3	0	1
T14	2943	0	0	0
T18	0	4	0	1
T19	1089	0	0	0
T20	1512	0	0	0
T21	1066	0	0	0
T28	0	3	0	1
T31	0	60	0	1
T32	0	36	0	1
T33	0	3	0	1
T65	0	3	0	1
T66	0	3	0	1
T67	0	36	0	1

gen_edn_if_asserts[2].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220171838	220020179	0	0
T1	1866	1789	0	0
T2	645	524	0	0
T3	1169	1079	0	0
T4	1926	1734	0	0
T5	7769	7320	0	0
T9	1861	1780	0	0
T14	2943	2802	0	0
T19	1089	1028	0	0
T20	1512	1456	0	0
T21	1066	911	0	0

gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220171838	139149	0	0
T2	645	364	0	0
T3	1169	0	0	0
T4	1926	1187	0	0
T5	7769	0	0	0
T6	1531	842	0	0
T7	0	876	0	0
T8	0	1181	0	0
T9	1861	0	0	0
T14	2943	1148	0	0
T15	0	350	0	0
T19	1089	0	0	0
T20	1512	0	0	0
T21	1066	22	0	0
T35	0	7	0	0
T60	0	1093	0	0

gen_edn_if_asserts[3].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220171838	510128	0	0
T1	1866	344	0	0
T2	645	290	0	0
T3	1169	1078	0	0
T4	1926	1092	0	0
T5	7769	3649	0	0
T9	1861	239	0	0
T14	2943	1162	0	0
T19	1089	21	0	0
T20	1512	45	0	0
T21	1066	491	0	0

gen_edn_if_asserts[3].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220171838	3193	0	101
T10	1815	0	0	0
T11	2374	3	0	1
T28	2606	3	0	1
T29	1926	57	0	1
T31	0	65	0	1
T33	0	3	0	1
T34	0	53	0	1
T54	8223	0	0	0
T55	3568	0	0	0
T56	1239	0	0	0
T57	958	0	0	0
T58	1361	0	0	0
T62	0	3	0	1
T68	0	3	0	1
T69	0	3	0	0
T70	0	3	0	1
T71	4478	0	0	0
T72	0	0	0	1

gen_edn_if_asserts[3].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220171838	220020179	0	0
T1	1866	1789	0	0
T2	645	524	0	0
T3	1169	1079	0	0
T4	1926	1734	0	0
T5	7769	7320	0	0
T9	1861	1780	0	0
T14	2943	2802	0	0
T19	1089	1028	0	0
T20	1512	1456	0	0
T21	1066	911	0	0

gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220171838	139149	0	0
T2	645	364	0	0
T3	1169	0	0	0
T4	1926	1187	0	0
T5	7769	0	0	0
T6	1531	842	0	0
T7	0	876	0	0
T8	0	1181	0	0
T9	1861	0	0	0
T14	2943	1148	0	0
T15	0	350	0	0
T19	1089	0	0	0
T20	1512	0	0	0
T21	1066	22	0	0
T35	0	7	0	0
T60	0	1093	0	0

gen_edn_if_asserts[4].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220171838	510128	0	0
T1	1866	344	0	0
T2	645	290	0	0
T3	1169	1078	0	0
T4	1926	1092	0	0
T5	7769	3649	0	0
T9	1861	239	0	0
T14	2943	1162	0	0
T19	1089	21	0	0
T20	1512	45	0	0
T21	1066	491	0	0

gen_edn_if_asserts[4].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220171838	2557	0	83
T1	1866	15	0	1
T2	645	0	0	0
T3	1169	0	0	0
T4	1926	0	0	0
T5	7769	0	0	0
T9	1861	0	0	0
T11	0	3	0	1
T14	2943	0	0	0
T19	1089	0	0	0
T20	1512	0	0	0
T21	1066	0	0	0
T28	0	53	0	1
T29	0	30	0	1
T31	0	62	0	1
T34	0	3	0	1
T62	0	3	0	1
T72	0	0	0	1
T73	0	3	0	0
T74	0	3	0	1
T75	0	3	0	1

gen_edn_if_asserts[4].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220171838	220020179	0	0
T1	1866	1789	0	0
T2	645	524	0	0
T3	1169	1079	0	0
T4	1926	1734	0	0
T5	7769	7320	0	0
T9	1861	1780	0	0
T14	2943	2802	0	0
T19	1089	1028	0	0
T20	1512	1456	0	0
T21	1066	911	0	0

gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220171838	139149	0	0
T2	645	364	0	0
T3	1169	0	0	0
T4	1926	1187	0	0
T5	7769	0	0	0
T6	1531	842	0	0
T7	0	876	0	0
T8	0	1181	0	0
T9	1861	0	0	0
T14	2943	1148	0	0
T15	0	350	0	0
T19	1089	0	0	0
T20	1512	0	0	0
T21	1066	22	0	0
T35	0	7	0	0
T60	0	1093	0	0

gen_edn_if_asserts[5].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220171838	510128	0	0
T1	1866	344	0	0
T2	645	290	0	0
T3	1169	1078	0	0
T4	1926	1092	0	0
T5	7769	3649	0	0
T9	1861	239	0	0
T14	2943	1162	0	0
T19	1089	21	0	0
T20	1512	45	0	0
T21	1066	491	0	0

gen_edn_if_asserts[5].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220171838	1749	0	71
T10	1815	0	0	0
T11	2374	15	0	1
T16	0	4	0	1
T28	2606	56	0	1
T29	1926	45	0	1
T31	0	46	0	1
T34	0	11	0	1
T54	8223	0	0	0
T55	3568	0	0	0
T56	1239	0	0	0
T57	958	0	0	0
T58	1361	0	0	0
T62	0	3	0	1
T67	0	11	0	1
T71	4478	0	0	0
T72	0	3	0	1
T76	0	4	0	1

gen_edn_if_asserts[5].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220171838	220020179	0	0
T1	1866	1789	0	0
T2	645	524	0	0
T3	1169	1079	0	0
T4	1926	1734	0	0
T5	7769	7320	0	0
T9	1861	1780	0	0
T14	2943	2802	0	0
T19	1089	1028	0	0
T20	1512	1456	0	0
T21	1066	911	0	0

gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220171838	139149	0	0
T2	645	364	0	0
T3	1169	0	0	0
T4	1926	1187	0	0
T5	7769	0	0	0
T6	1531	842	0	0
T7	0	876	0	0
T8	0	1181	0	0
T9	1861	0	0	0
T14	2943	1148	0	0
T15	0	350	0	0
T19	1089	0	0	0
T20	1512	0	0	0
T21	1066	22	0	0
T35	0	7	0	0
T60	0	1093	0	0

gen_edn_if_asserts[6].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220171838	510128	0	0
T1	1866	344	0	0
T2	645	290	0	0
T3	1169	1078	0	0
T4	1926	1092	0	0
T5	7769	3649	0	0
T9	1861	239	0	0
T14	2943	1162	0	0
T19	1089	21	0	0
T20	1512	45	0	0
T21	1066	491	0	0

gen_edn_if_asserts[6].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220171838	2826	0	56
T10	1815	0	0	0
T28	2606	31	0	1
T29	1926	52	0	1
T30	1320	3	0	1
T34	0	3	0	1
T56	1239	0	0	0
T57	958	0	0	0
T58	1361	0	0	0
T59	1328	0	0	0
T62	0	0	0	1
T67	0	3	0	1
T71	4478	0	0	0
T72	0	0	0	1
T77	0	3	0	1
T78	0	3	0	0
T79	0	3	0	0
T80	0	3	0	0
T81	0	3	0	0
T82	818661	0	0	0
T83	0	0	0	1
T84	0	0	0	1

gen_edn_if_asserts[6].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220171838	220020179	0	0
T1	1866	1789	0	0
T2	645	524	0	0
T3	1169	1079	0	0
T4	1926	1734	0	0
T5	7769	7320	0	0
T9	1861	1780	0	0
T14	2943	2802	0	0
T19	1089	1028	0	0
T20	1512	1456	0	0
T21	1066	911	0	0

gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	220171838	139149	0	0
T2	645	364	0	0
T3	1169	0	0	0
T4	1926	1187	0	0
T5	7769	0	0	0
T6	1531	842	0	0
T7	0	876	0	0
T8	0	1181	0	0
T9	1861	0	0	0
T14	2943	1148	0	0
T15	0	350	0	0
T19	1089	0	0	0
T20	1512	0	0	0
T21	1066	22	0	0
T35	0	7	0	0
T60	0	1093	0	0