Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44		83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	226246806	10540941	0	0
boot_gen_cmd_rd_A	226246806	34980	0	0
boot_ins_cmd_rd_A	226246806	40610	0	0
ctrl_rd_A	226246806	36060	0	0
err_code_test_rd_A	226246806	35679	0	0
intr_enable_rd_A	226246806	40736	0	0
max_num_reqs_between_reseeds_rd_A	226246806	41335	0	0
regwen_rd_A	226246806	41814	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226246806	10540941	0	0
T5	404764	244784	0	0
T6	2289	0	0	0
T12	1553	0	0	0
T15	2883	0	0	0
T24	840	15	0	0
T25	991	3	0	0
T120	10084	678	0	0
T121	8081	6	0	0
T122	6625	578	0	0
T169	0	253	0	0
T170	0	767	0	0
T171	0	67	0	0
T172	0	772	0	0
T173	1148	0	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226246806	34980	0	0
T42	797	0	0	0
T171	2397	0	0	0
T172	3384	0	0	0
T174	913	4	0	0
T175	0	4	0	0
T176	0	15	0	0
T177	0	13	0	0
T178	0	5	0	0
T179	0	27	0	0
T180	0	6	0	0
T181	0	5	0	0
T182	0	13	0	0
T183	0	8	0	0
T184	1318	0	0	0
T185	1237	0	0	0
T186	971	0	0	0
T187	983	0	0	0
T188	1276	0	0	0
T189	1147	0	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226246806	40610	0	0
T42	797	0	0	0
T171	2397	0	0	0
T172	3384	0	0	0
T174	913	4	0	0
T175	0	55	0	0
T177	0	5	0	0
T178	0	11	0	0
T179	0	29	0	0
T180	0	2	0	0
T181	0	1	0	0
T182	0	15	0	0
T184	1318	0	0	0
T185	1237	0	0	0
T186	971	0	0	0
T187	983	0	0	0
T188	1276	0	0	0
T189	1147	0	0	0
T190	0	7	0	0
T191	0	1	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226246806	36060	0	0
T121	8081	5	0	0
T122	6625	0	0	0
T169	2167	0	0	0
T170	9883	0	0	0
T171	2397	0	0	0
T173	1148	0	0	0
T174	913	6	0	0
T175	0	10	0	0
T176	0	11	0	0
T177	0	3	0	0
T178	0	14	0	0
T179	0	22	0	0
T180	0	4	0	0
T184	1318	0	0	0
T185	1237	0	0	0
T190	0	4	0	0
T192	0	1	0	0
T193	11446	0	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226246806	35679	0	0
T42	797	0	0	0
T171	2397	0	0	0
T172	3384	0	0	0
T174	913	3	0	0
T175	0	13	0	0
T176	0	25	0	0
T177	0	5	0	0
T178	0	16	0	0
T179	0	37	0	0
T180	0	1	0	0
T181	0	2	0	0
T182	0	11	0	0
T183	0	9	0	0
T184	1318	0	0	0
T185	1237	0	0	0
T186	971	0	0	0
T187	983	0	0	0
T188	1276	0	0	0
T189	1147	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226246806	40736	0	0
T121	8081	96	0	0
T122	6625	0	0	0
T169	2167	0	0	0
T170	9883	0	0	0
T171	2397	0	0	0
T173	1148	9	0	0
T174	913	1	0	0
T175	0	30	0	0
T177	0	23	0	0
T184	1318	0	0	0
T185	1237	0	0	0
T190	0	16	0	0
T193	11446	129	0	0
T194	0	7	0	0
T195	0	60	0	0
T196	0	5	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226246806	41335	0	0
T40	1128	3	0	0
T121	8081	78	0	0
T122	6625	0	0	0
T169	2167	0	0	0
T170	9883	0	0	0
T171	2397	0	0	0
T173	1148	3	0	0
T174	913	6	0	0
T175	0	14	0	0
T176	0	22	0	0
T177	0	20	0	0
T184	1318	0	0	0
T190	0	3	0	0
T193	11446	107	0	0
T195	0	27	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226246806	41814	0	0
T40	1128	7	0	0
T121	8081	70	0	0
T122	6625	0	0	0
T169	2167	0	0	0
T170	9883	0	0	0
T171	2397	0	0	0
T173	1148	4	0	0
T174	913	6	0	0
T175	0	10	0	0
T176	0	23	0	0
T177	0	13	0	0
T184	1318	0	0	0
T190	0	10	0	0
T193	11446	135	0	0
T195	0	32	0	0