Unified Coverage Report :: Module :: edn

Module : edn

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	94.44		83.33	100.00			100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.76	99.02	92.26	96.79	94.08	98.62	99.77

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
edn_csr_assert	100.00						100.00
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_edn_core	92.08	99.92	89.48	70.79	94.08	99.29	98.91
u_edn_cov_if	25.00	50.00	0.00
u_reg	98.63	96.98	98.92	100.00		97.26	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Cond Coverage for Module : edn

	Total	Covered	Percent
Conditions	6	5	83.33
Logical	6	5	83.33
Non-Logical	0	0
Event	0	0

 LINE       99
 EXPRESSION (alert[0] || intg_err_alert[0])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T17,T18,T19

 LINE       99
 EXPRESSION (alert[1] || intg_err_alert[1])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T21,T22,T23
1	0	Covered	T4,T6,T15

---

Toggle Coverage for Module : edn

	Total	Covered	Percent
Totals	69	69	100.00
Total Bits	1168	1168	100.00
Total Bits 0->1	584	584	100.00
Total Bits 1->0	584	584	100.00

Ports	69	69	100.00
Port Bits	1168	1168	100.00
Port Bits 0->1	584	584	100.00
Port Bits 1->0	584	584	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T4,T5,T6	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T3,T11,T20	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T7,T20	Yes	T1,T7,T20	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T7,T11	Yes	T1,T7,T11	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T3,T7	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T5,T24,T25	Yes	T5,T24,T25	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T3,T10	Yes	T1,T3,T10	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T3,*T10	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i[0].edn_req	Yes	Yes	T3,T10,T11	Yes	T3,T10,T11	INPUT
edn_i[1].edn_req	Yes	Yes	T11,T18,T26	Yes	T11,T18,T26	INPUT
edn_i[2].edn_req	Yes	Yes	T7,T11,T27	Yes	T7,T11,T27	INPUT
edn_i[3].edn_req	Yes	Yes	T11,T20,T27	Yes	T11,T20,T27	INPUT
edn_i[4].edn_req	Yes	Yes	T28,T29,T30	Yes	T28,T29,T30	INPUT
edn_i[5].edn_req	Yes	Yes	T11,T17,T31	Yes	T11,T17,T31	INPUT
edn_i[6].edn_req	Yes	Yes	T1,T11,T30	Yes	T1,T11,T30	INPUT
edn_o[0].edn_bus[31:0]	Yes	Yes	T10,T11,T5	Yes	T3,T10,T11	OUTPUT
edn_o[0].edn_fips	Yes	Yes	T10,T11,T5	Yes	T10,T11,T5	OUTPUT
edn_o[0].edn_ack	Yes	Yes	T3,T10,T11	Yes	T3,T10,T11	OUTPUT
edn_o[1].edn_bus[31:0]	Yes	Yes	T11,T18,T26	Yes	T11,T18,T26	OUTPUT
edn_o[1].edn_fips	Yes	Yes	T26,T32,T30	Yes	T11,T26,T33	OUTPUT
edn_o[1].edn_ack	Yes	Yes	T11,T18,T26	Yes	T11,T18,T26	OUTPUT
edn_o[2].edn_bus[31:0]	Yes	Yes	T7,T11,T27	Yes	T7,T11,T27	OUTPUT
edn_o[2].edn_fips	Yes	Yes	T7,T11,T27	Yes	T7,T11,T27	OUTPUT
edn_o[2].edn_ack	Yes	Yes	T7,T11,T27	Yes	T7,T11,T27	OUTPUT
edn_o[3].edn_bus[31:0]	Yes	Yes	T11,T20,T27	Yes	T11,T20,T27	OUTPUT
edn_o[3].edn_fips	Yes	Yes	T20,T27,T30	Yes	T20,T27,T31	OUTPUT
edn_o[3].edn_ack	Yes	Yes	T11,T20,T27	Yes	T11,T20,T27	OUTPUT
edn_o[4].edn_bus[31:0]	Yes	Yes	T28,T29,T30	Yes	T28,T29,T30	OUTPUT
edn_o[4].edn_fips	Yes	Yes	T34,T35,T36	Yes	T28,T29,T37	OUTPUT
edn_o[4].edn_ack	Yes	Yes	T28,T29,T30	Yes	T28,T29,T30	OUTPUT
edn_o[5].edn_bus[31:0]	Yes	Yes	T11,T17,T31	Yes	T11,T17,T31	OUTPUT
edn_o[5].edn_fips	Yes	Yes	T31,T30,T38	Yes	T11,T31,T39	OUTPUT
edn_o[5].edn_ack	Yes	Yes	T11,T17,T31	Yes	T11,T17,T31	OUTPUT
edn_o[6].edn_bus[31:0]	Yes	Yes	T1,T11,T30	Yes	T1,T11,T30	OUTPUT
edn_o[6].edn_fips	Yes	Yes	T11,T30,T36	Yes	T1,T11,T30	OUTPUT
edn_o[6].edn_ack	Yes	Yes	T1,T11,T30	Yes	T1,T11,T30	OUTPUT
csrng_cmd_o.genbits_ready	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	OUTPUT
csrng_cmd_o.csrng_req_valid	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	OUTPUT
csrng_cmd_i.genbits_bus[127:0]	Yes	Yes	T1,T10,T11	Yes	T1,T10,T11	INPUT
csrng_cmd_i.genbits_fips	Yes	Yes	T7,T10,T11	Yes	T1,T10,T11	INPUT
csrng_cmd_i.genbits_valid	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	INPUT
csrng_cmd_i.csrng_rsp_sts	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	INPUT
csrng_cmd_i.csrng_rsp_ack	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	INPUT
csrng_cmd_i.csrng_req_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T2,T40,T24	Yes	T2,T40,T24	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T2,T4,T6	Yes	T2,T4,T6	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T2,T40,T24	Yes	T2,T40,T24	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T2,T4,T6	Yes	T2,T4,T6	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T5,T41,T42	Yes	T5,T41,T42	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T4,T5,T41	Yes	T4,T5,T41	OUTPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Module : edn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	43	43	100.00	43	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	43	43	100.00	43	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnownO_A	225776907	225615228	0	0
CsrngAppIfOut_A	225776907	225615228	0	0
FpvSecCmCntAlertCheck_A	225776907	135	0	0
FpvSecCmMainFsmCheck_A	225776907	90	0	0
FpvSecCmRegWeOnehotCheck_A	225776907	90	0	0
IntrEdnCmdReqDoneKnownO_A	225776907	225615228	0	0
TlAReadyKnownO_A	225776907	225615228	0	0
TlDValidKnownO_A	225776907	225615228	0	0
gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A	225776907	90	0	0
gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A	225776907	90	0	0
gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A	225776907	90	0	0
gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A	225776907	90	0	0
gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A	225776907	90	0	0
gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A	225776907	90	0	0
gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A	225776907	90	0	0
gen_edn_if_asserts[0].EdnDataStableDisable_A	225776907	518440	0	0
gen_edn_if_asserts[0].EdnDataStable_A	225776907	28129	0	331
gen_edn_if_asserts[0].EdnEndPointOut_A	225776907	225615228	0	0
gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A	225776907	139227	0	0
gen_edn_if_asserts[1].EdnDataStableDisable_A	225776907	518440	0	0
gen_edn_if_asserts[1].EdnDataStable_A	225776907	7949	0	119
gen_edn_if_asserts[1].EdnEndPointOut_A	225776907	225615228	0	0
gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A	225776907	139227	0	0
gen_edn_if_asserts[2].EdnDataStableDisable_A	225776907	518440	0	0
gen_edn_if_asserts[2].EdnDataStable_A	225776907	7001	0	116
gen_edn_if_asserts[2].EdnEndPointOut_A	225776907	225615228	0	0
gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A	225776907	139227	0	0
gen_edn_if_asserts[3].EdnDataStableDisable_A	225776907	518440	0	0
gen_edn_if_asserts[3].EdnDataStable_A	225776907	3726	0	101
gen_edn_if_asserts[3].EdnEndPointOut_A	225776907	225615228	0	0
gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A	225776907	139227	0	0
gen_edn_if_asserts[4].EdnDataStableDisable_A	225776907	518440	0	0
gen_edn_if_asserts[4].EdnDataStable_A	225776907	2158	0	86
gen_edn_if_asserts[4].EdnEndPointOut_A	225776907	225615228	0	0
gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A	225776907	139227	0	0
gen_edn_if_asserts[5].EdnDataStableDisable_A	225776907	518440	0	0
gen_edn_if_asserts[5].EdnDataStable_A	225776907	4506	0	79
gen_edn_if_asserts[5].EdnEndPointOut_A	225776907	225615228	0	0
gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A	225776907	139227	0	0
gen_edn_if_asserts[6].EdnDataStableDisable_A	225776907	518440	0	0
gen_edn_if_asserts[6].EdnDataStable_A	225776907	3961	0	77
gen_edn_if_asserts[6].EdnEndPointOut_A	225776907	225615228	0	0
gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A	225776907	139227	0	0

AlertTxKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	225776907	225615228	0	0
T1	1196	1109	0	0
T2	1190	1109	0	0
T3	801	736	0	0
T4	665	481	0	0
T5	404764	404752	0	0
T7	918	831	0	0
T10	3794	3738	0	0
T11	2407	2324	0	0
T12	1553	1467	0	0
T20	1722	1633	0	0

CsrngAppIfOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	225776907	225615228	0	0
T1	1196	1109	0	0
T2	1190	1109	0	0
T3	801	736	0	0
T4	665	481	0	0
T5	404764	404752	0	0
T7	918	831	0	0
T10	3794	3738	0	0
T11	2407	2324	0	0
T12	1553	1467	0	0
T20	1722	1633	0	0

FpvSecCmCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	225776907	135	0	0
T8	2132	1	0	0
T9	1246	0	0	0
T15	2883	1	0	0
T16	811	1	0	0
T21	0	20	0	0
T22	0	20	0	0
T32	1291	0	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	2226	0	0	0
T49	841	0	0	0
T50	8567	0	0	0
T51	1258	0	0	0
T52	511	0	0	0

FpvSecCmMainFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	225776907	90	0	0
T21	43639	20	0	0
T22	37859	20	0	0
T23	0	20	0	0
T53	0	20	0	0
T54	0	10	0	0
T55	555	0	0	0
T56	1207	0	0	0
T57	1666	0	0	0
T58	2887	0	0	0
T59	1392	0	0	0
T60	1377	0	0	0
T61	1527	0	0	0
T62	1857	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	225776907	90	0	0
T21	43639	20	0	0
T22	37859	20	0	0
T23	0	20	0	0
T53	0	20	0	0
T54	0	10	0	0
T55	555	0	0	0
T56	1207	0	0	0
T57	1666	0	0	0
T58	2887	0	0	0
T59	1392	0	0	0
T60	1377	0	0	0
T61	1527	0	0	0
T62	1857	0	0	0

IntrEdnCmdReqDoneKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	225776907	225615228	0	0
T1	1196	1109	0	0
T2	1190	1109	0	0
T3	801	736	0	0
T4	665	481	0	0
T5	404764	404752	0	0
T7	918	831	0	0
T10	3794	3738	0	0
T11	2407	2324	0	0
T12	1553	1467	0	0
T20	1722	1633	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	225776907	225615228	0	0
T1	1196	1109	0	0
T2	1190	1109	0	0
T3	801	736	0	0
T4	665	481	0	0
T5	404764	404752	0	0
T7	918	831	0	0
T10	3794	3738	0	0
T11	2407	2324	0	0
T12	1553	1467	0	0
T20	1722	1633	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	225776907	225615228	0	0
T1	1196	1109	0	0
T2	1190	1109	0	0
T3	801	736	0	0
T4	665	481	0	0
T5	404764	404752	0	0
T7	918	831	0	0
T10	3794	3738	0	0
T11	2407	2324	0	0
T12	1553	1467	0	0
T20	1722	1633	0	0

gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	225776907	90	0	0
T21	43639	20	0	0
T22	37859	20	0	0
T23	0	20	0	0
T53	0	20	0	0
T54	0	10	0	0
T55	555	0	0	0
T56	1207	0	0	0
T57	1666	0	0	0
T58	2887	0	0	0
T59	1392	0	0	0
T60	1377	0	0	0
T61	1527	0	0	0
T62	1857	0	0	0

gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	225776907	90	0	0
T21	43639	20	0	0
T22	37859	20	0	0
T23	0	20	0	0
T53	0	20	0	0
T54	0	10	0	0
T55	555	0	0	0
T56	1207	0	0	0
T57	1666	0	0	0
T58	2887	0	0	0
T59	1392	0	0	0
T60	1377	0	0	0
T61	1527	0	0	0
T62	1857	0	0	0

gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	225776907	90	0	0
T21	43639	20	0	0
T22	37859	20	0	0
T23	0	20	0	0
T53	0	20	0	0
T54	0	10	0	0
T55	555	0	0	0
T56	1207	0	0	0
T57	1666	0	0	0
T58	2887	0	0	0
T59	1392	0	0	0
T60	1377	0	0	0
T61	1527	0	0	0
T62	1857	0	0	0

gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	225776907	90	0	0
T21	43639	20	0	0
T22	37859	20	0	0
T23	0	20	0	0
T53	0	20	0	0
T54	0	10	0	0
T55	555	0	0	0
T56	1207	0	0	0
T57	1666	0	0	0
T58	2887	0	0	0
T59	1392	0	0	0
T60	1377	0	0	0
T61	1527	0	0	0
T62	1857	0	0	0

gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	225776907	90	0	0
T21	43639	20	0	0
T22	37859	20	0	0
T23	0	20	0	0
T53	0	20	0	0
T54	0	10	0	0
T55	555	0	0	0
T56	1207	0	0	0
T57	1666	0	0	0
T58	2887	0	0	0
T59	1392	0	0	0
T60	1377	0	0	0
T61	1527	0	0	0
T62	1857	0	0	0

gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	225776907	90	0	0
T21	43639	20	0	0
T22	37859	20	0	0
T23	0	20	0	0
T53	0	20	0	0
T54	0	10	0	0
T55	555	0	0	0
T56	1207	0	0	0
T57	1666	0	0	0
T58	2887	0	0	0
T59	1392	0	0	0
T60	1377	0	0	0
T61	1527	0	0	0
T62	1857	0	0	0

gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	225776907	90	0	0
T21	43639	20	0	0
T22	37859	20	0	0
T23	0	20	0	0
T53	0	20	0	0
T54	0	10	0	0
T55	555	0	0	0
T56	1207	0	0	0
T57	1666	0	0	0
T58	2887	0	0	0
T59	1392	0	0	0
T60	1377	0	0	0
T61	1527	0	0	0
T62	1857	0	0	0

gen_edn_if_asserts[0].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	225776907	518440	0	0
T1	1196	21	0	0
T2	1190	1108	0	0
T3	801	26	0	0
T4	665	268	0	0
T5	404764	1749	0	0
T7	918	34	0	0
T10	3794	65	0	0
T11	2407	360	0	0
T12	1553	238	0	0
T20	1722	18	0	0

gen_edn_if_asserts[0].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	225776907	28129	0	331
T3	801	3	0	1
T4	665	0	0	0
T5	404764	78	0	0
T6	2289	0	0	0
T7	918	0	0	0
T10	3794	627	0	1
T11	2407	21	0	1
T12	1553	15	0	1
T15	2883	0	0	0
T20	1722	0	0	0
T27	0	19	0	1
T30	0	0	0	1
T32	0	3	0	1
T48	0	267	0	1
T49	0	3	0	1
T63	0	79	0	1

gen_edn_if_asserts[0].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	225776907	225615228	0	0
T1	1196	1109	0	0
T2	1190	1109	0	0
T3	801	736	0	0
T4	665	481	0	0
T5	404764	404752	0	0
T7	918	831	0	0
T10	3794	3738	0	0
T11	2407	2324	0	0
T12	1553	1467	0	0
T20	1722	1633	0	0

gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	225776907	139227	0	0
T4	665	7	0	0
T5	404764	0	0	0
T6	2289	1097	0	0
T8	0	1023	0	0
T9	0	366	0	0
T12	1553	0	0	0
T13	1313	0	0	0
T15	2883	1114	0	0
T16	0	430	0	0
T31	3583	0	0	0
T52	0	210	0	0
T63	2053	0	0	0
T64	1119	672	0	0
T65	0	612	0	0
T66	0	591	0	0
T67	6185	0	0	0

gen_edn_if_asserts[1].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	225776907	518440	0	0
T1	1196	21	0	0
T2	1190	1108	0	0
T3	801	26	0	0
T4	665	268	0	0
T5	404764	1749	0	0
T7	918	34	0	0
T10	3794	65	0	0
T11	2407	360	0	0
T12	1553	238	0	0
T20	1722	18	0	0

gen_edn_if_asserts[1].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	225776907	7949	0	119
T4	665	0	0	0
T5	404764	0	0	0
T6	2289	0	0	0
T11	2407	10	0	1
T12	1553	0	0	0
T15	2883	0	0	0
T18	1272	4	0	1
T20	1722	0	0	0
T26	5430	894	0	1
T27	1919	3	0	1
T30	0	34	0	1
T32	0	24	0	1
T33	0	23	0	1
T68	0	3	0	0
T69	0	183	0	1
T70	0	50	0	1
T71	0	0	0	1

gen_edn_if_asserts[1].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	225776907	225615228	0	0
T1	1196	1109	0	0
T2	1190	1109	0	0
T3	801	736	0	0
T4	665	481	0	0
T5	404764	404752	0	0
T7	918	831	0	0
T10	3794	3738	0	0
T11	2407	2324	0	0
T12	1553	1467	0	0
T20	1722	1633	0	0

gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	225776907	139227	0	0
T4	665	7	0	0
T5	404764	0	0	0
T6	2289	1097	0	0
T8	0	1023	0	0
T9	0	366	0	0
T12	1553	0	0	0
T13	1313	0	0	0
T15	2883	1114	0	0
T16	0	430	0	0
T31	3583	0	0	0
T52	0	210	0	0
T63	2053	0	0	0
T64	1119	672	0	0
T65	0	612	0	0
T66	0	591	0	0
T67	6185	0	0	0

gen_edn_if_asserts[2].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	225776907	518440	0	0
T1	1196	21	0	0
T2	1190	1108	0	0
T3	801	26	0	0
T4	665	268	0	0
T5	404764	1749	0	0
T7	918	34	0	0
T10	3794	65	0	0
T11	2407	360	0	0
T12	1553	238	0	0
T20	1722	18	0	0

gen_edn_if_asserts[2].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	225776907	7001	0	116
T4	665	0	0	0
T5	404764	0	0	0
T6	2289	0	0	0
T7	918	3	0	0
T10	3794	0	0	0
T11	2407	31	0	1
T12	1553	0	0	0
T13	0	35	0	1
T15	2883	0	0	0
T20	1722	0	0	0
T27	1919	63	0	1
T30	0	18	0	1
T32	0	3	0	1
T34	0	0	0	1
T67	0	1155	0	1
T69	0	34	0	1
T70	0	18	0	1
T72	0	50	0	1

gen_edn_if_asserts[2].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	225776907	225615228	0	0
T1	1196	1109	0	0
T2	1190	1109	0	0
T3	801	736	0	0
T4	665	481	0	0
T5	404764	404752	0	0
T7	918	831	0	0
T10	3794	3738	0	0
T11	2407	2324	0	0
T12	1553	1467	0	0
T20	1722	1633	0	0

gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	225776907	139227	0	0
T4	665	7	0	0
T5	404764	0	0	0
T6	2289	1097	0	0
T8	0	1023	0	0
T9	0	366	0	0
T12	1553	0	0	0
T13	1313	0	0	0
T15	2883	1114	0	0
T16	0	430	0	0
T31	3583	0	0	0
T52	0	210	0	0
T63	2053	0	0	0
T64	1119	672	0	0
T65	0	612	0	0
T66	0	591	0	0
T67	6185	0	0	0

gen_edn_if_asserts[3].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	225776907	518440	0	0
T1	1196	21	0	0
T2	1190	1108	0	0
T3	801	26	0	0
T4	665	268	0	0
T5	404764	1749	0	0
T7	918	34	0	0
T10	3794	65	0	0
T11	2407	360	0	0
T12	1553	238	0	0
T20	1722	18	0	0

gen_edn_if_asserts[3].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	225776907	3726	0	101
T4	665	0	0	0
T5	404764	0	0	0
T6	2289	0	0	0
T11	2407	3	0	1
T12	1553	0	0	0
T15	2883	0	0	0
T20	1722	31	0	1
T27	1919	46	0	1
T30	0	43	0	1
T31	0	3	0	1
T33	1185	0	0	0
T64	1119	0	0	0
T67	0	3	0	1
T69	0	61	0	1
T70	0	3	0	1
T72	0	31	0	1
T73	0	3	0	1

gen_edn_if_asserts[3].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	225776907	225615228	0	0
T1	1196	1109	0	0
T2	1190	1109	0	0
T3	801	736	0	0
T4	665	481	0	0
T5	404764	404752	0	0
T7	918	831	0	0
T10	3794	3738	0	0
T11	2407	2324	0	0
T12	1553	1467	0	0
T20	1722	1633	0	0

gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	225776907	139227	0	0
T4	665	7	0	0
T5	404764	0	0	0
T6	2289	1097	0	0
T8	0	1023	0	0
T9	0	366	0	0
T12	1553	0	0	0
T13	1313	0	0	0
T15	2883	1114	0	0
T16	0	430	0	0
T31	3583	0	0	0
T52	0	210	0	0
T63	2053	0	0	0
T64	1119	672	0	0
T65	0	612	0	0
T66	0	591	0	0
T67	6185	0	0	0

gen_edn_if_asserts[4].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	225776907	518440	0	0
T1	1196	21	0	0
T2	1190	1108	0	0
T3	801	26	0	0
T4	665	268	0	0
T5	404764	1749	0	0
T7	918	34	0	0
T10	3794	65	0	0
T11	2407	360	0	0
T12	1553	238	0	0
T20	1722	18	0	0

gen_edn_if_asserts[4].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	225776907	2158	0	86
T8	2132	0	0	0
T28	994	3	0	1
T29	2284	4	0	0
T30	1924	3	0	1
T32	1291	0	0	0
T34	0	22	0	1
T35	0	25	0	1
T36	0	0	0	1
T37	0	3	0	0
T39	1954	0	0	0
T48	2226	0	0	0
T49	841	0	0	0
T65	1122	0	0	0
T72	0	3	0	1
T74	0	15	0	1
T75	0	3	0	1
T76	0	3	0	1
T77	927	0	0	0
T78	0	0	0	1

gen_edn_if_asserts[4].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	225776907	225615228	0	0
T1	1196	1109	0	0
T2	1190	1109	0	0
T3	801	736	0	0
T4	665	481	0	0
T5	404764	404752	0	0
T7	918	831	0	0
T10	3794	3738	0	0
T11	2407	2324	0	0
T12	1553	1467	0	0
T20	1722	1633	0	0

gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	225776907	139227	0	0
T4	665	7	0	0
T5	404764	0	0	0
T6	2289	1097	0	0
T8	0	1023	0	0
T9	0	366	0	0
T12	1553	0	0	0
T13	1313	0	0	0
T15	2883	1114	0	0
T16	0	430	0	0
T31	3583	0	0	0
T52	0	210	0	0
T63	2053	0	0	0
T64	1119	672	0	0
T65	0	612	0	0
T66	0	591	0	0
T67	6185	0	0	0

gen_edn_if_asserts[5].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	225776907	518440	0	0
T1	1196	21	0	0
T2	1190	1108	0	0
T3	801	26	0	0
T4	665	268	0	0
T5	404764	1749	0	0
T7	918	34	0	0
T10	3794	65	0	0
T11	2407	360	0	0
T12	1553	238	0	0
T20	1722	18	0	0

gen_edn_if_asserts[5].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	225776907	4506	0	79
T4	665	0	0	0
T5	404764	0	0	0
T6	2289	0	0	0
T11	2407	3	0	1
T12	1553	0	0	0
T15	2883	0	0	0
T17	1603	4	0	1
T18	1272	0	0	0
T20	1722	0	0	0
T26	5430	0	0	0
T30	0	16	0	1
T31	0	399	0	1
T35	0	0	0	1
T38	0	58	0	1
T39	0	3	0	0
T69	0	3	0	1
T74	0	3	0	1
T76	0	3	0	1
T79	0	38	0	1

gen_edn_if_asserts[5].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	225776907	225615228	0	0
T1	1196	1109	0	0
T2	1190	1109	0	0
T3	801	736	0	0
T4	665	481	0	0
T5	404764	404752	0	0
T7	918	831	0	0
T10	3794	3738	0	0
T11	2407	2324	0	0
T12	1553	1467	0	0
T20	1722	1633	0	0

gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	225776907	139227	0	0
T4	665	7	0	0
T5	404764	0	0	0
T6	2289	1097	0	0
T8	0	1023	0	0
T9	0	366	0	0
T12	1553	0	0	0
T13	1313	0	0	0
T15	2883	1114	0	0
T16	0	430	0	0
T31	3583	0	0	0
T52	0	210	0	0
T63	2053	0	0	0
T64	1119	672	0	0
T65	0	612	0	0
T66	0	591	0	0
T67	6185	0	0	0

gen_edn_if_asserts[6].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	225776907	518440	0	0
T1	1196	21	0	0
T2	1190	1108	0	0
T3	801	26	0	0
T4	665	268	0	0
T5	404764	1749	0	0
T7	918	34	0	0
T10	3794	65	0	0
T11	2407	360	0	0
T12	1553	238	0	0
T20	1722	18	0	0

gen_edn_if_asserts[6].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	225776907	3961	0	77
T1	1196	28	0	1
T2	1190	0	0	0
T3	801	0	0	0
T4	665	0	0	0
T5	404764	0	0	0
T7	918	0	0	0
T10	3794	0	0	0
T11	2407	15	0	1
T12	1553	0	0	0
T20	1722	0	0	0
T30	0	47	0	1
T34	0	3	0	1
T35	0	3	0	1
T69	0	3	0	1
T72	0	15	0	1
T75	0	3	0	1
T76	0	3	0	1
T80	0	3	0	1

gen_edn_if_asserts[6].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	225776907	225615228	0	0
T1	1196	1109	0	0
T2	1190	1109	0	0
T3	801	736	0	0
T4	665	481	0	0
T5	404764	404752	0	0
T7	918	831	0	0
T10	3794	3738	0	0
T11	2407	2324	0	0
T12	1553	1467	0	0
T20	1722	1633	0	0

gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	225776907	139227	0	0
T4	665	7	0	0
T5	404764	0	0	0
T6	2289	1097	0	0
T8	0	1023	0	0
T9	0	366	0	0
T12	1553	0	0	0
T13	1313	0	0	0
T15	2883	1114	0	0
T16	0	430	0	0
T31	3583	0	0	0
T52	0	210	0	0
T63	2053	0	0	0
T64	1119	672	0	0
T65	0	612	0	0
T66	0	591	0	0
T67	6185	0	0	0