Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44		83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	194950714	9473923	0	0
boot_gen_cmd_rd_A	194950714	38485	0	0
boot_ins_cmd_rd_A	194950714	44076	0	0
ctrl_rd_A	194950714	38297	0	0
err_code_test_rd_A	194950714	38635	0	0
intr_enable_rd_A	194950714	44370	0	0
max_num_reqs_between_reseeds_rd_A	194950714	45429	0	0
regwen_rd_A	194950714	44644	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	194950714	9473923	0	0
T27	6860	504	0	0
T28	9565	718	0	0
T29	1716	47	0	0
T46	15816	8	0	0
T136	1640	33	0	0
T137	2463	54	0	0
T138	1879	43	0	0
T139	3194	713	0	0
T140	4341	215	0	0
T141	0	4	0	0
T142	1540	0	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	194950714	38485	0	0
T49	1346	0	0	0
T140	4341	9	0	0
T141	3881	0	0	0
T142	1540	0	0	0
T143	4242	30	0	0
T144	0	17	0	0
T145	0	24	0	0
T146	0	25	0	0
T147	0	2	0	0
T148	0	6	0	0
T149	0	2	0	0
T150	0	20	0	0
T151	0	28	0	0
T152	1418	0	0	0
T153	1048	0	0	0
T154	6594	0	0	0
T155	5741	0	0	0
T156	2224	0	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	194950714	44076	0	0
T49	1346	0	0	0
T143	4242	22	0	0
T144	0	7	0	0
T145	0	57	0	0
T146	0	6	0	0
T148	0	12	0	0
T149	0	8	0	0
T150	0	19	0	0
T151	0	11	0	0
T155	5741	0	0	0
T156	2224	0	0	0
T157	0	2	0	0
T158	0	3	0	0
T159	1395	0	0	0
T160	1841	0	0	0
T161	6023	0	0	0
T162	654	0	0	0
T163	7585	0	0	0
T164	1428	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	194950714	38297	0	0
T49	1346	0	0	0
T140	4341	9	0	0
T141	3881	0	0	0
T142	1540	0	0	0
T143	4242	55	0	0
T144	0	22	0	0
T145	0	44	0	0
T146	0	14	0	0
T148	0	14	0	0
T149	0	2	0	0
T150	0	32	0	0
T152	1418	0	0	0
T153	1048	0	0	0
T154	6594	0	0	0
T155	5741	0	0	0
T156	2224	0	0	0
T157	0	15	0	0
T165	0	1	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	194950714	38635	0	0
T49	1346	0	0	0
T143	4242	28	0	0
T144	0	45	0	0
T145	0	37	0	0
T146	0	5	0	0
T148	0	6	0	0
T149	0	21	0	0
T155	5741	0	0	0
T156	2224	0	0	0
T157	0	3	0	0
T158	0	7	0	0
T159	1395	0	0	0
T160	1841	0	0	0
T161	6023	0	0	0
T162	654	0	0	0
T163	7585	12	0	0
T164	1428	0	0	0
T165	0	1	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	194950714	44370	0	0
T46	15816	62	0	0
T48	987	20	0	0
T49	1346	0	0	0
T141	3881	37	0	0
T143	4242	62	0	0
T144	0	29	0	0
T153	1048	0	0	0
T154	6594	0	0	0
T155	5741	0	0	0
T156	2224	0	0	0
T159	1395	0	0	0
T163	0	98	0	0
T166	0	8	0	0
T167	0	16	0	0
T168	0	3	0	0
T169	0	20	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	194950714	45429	0	0
T46	15816	49	0	0
T140	4341	2	0	0
T141	3881	36	0	0
T142	1540	0	0	0
T143	4242	67	0	0
T144	0	22	0	0
T145	0	30	0	0
T146	0	30	0	0
T147	0	1	0	0
T152	1418	0	0	0
T153	1048	0	0	0
T154	6594	0	0	0
T155	5741	0	0	0
T156	2224	0	0	0
T163	0	77	0	0
T170	0	1	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	194950714	44644	0	0
T46	15816	54	0	0
T140	4341	15	0	0
T141	3881	36	0	0
T142	1540	0	0	0
T143	4242	57	0	0
T144	0	34	0	0
T145	0	65	0	0
T146	0	31	0	0
T148	0	10	0	0
T152	1418	0	0	0
T153	1048	0	0	0
T154	6594	0	0	0
T155	5741	0	0	0
T156	2224	0	0	0
T163	0	81	0	0
T171	0	56	0	0