Unified Coverage Report :: Module :: edn

Module : edn

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	94.44		83.33	100.00			100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.78	99.02	92.32	96.84	94.08	98.62	99.77

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
edn_csr_assert	100.00						100.00
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_edn_core	92.18	99.92	89.58	71.29	94.08	99.29	98.91
u_edn_cov_if	25.00	50.00	0.00
u_reg	98.63	96.98	98.92	100.00		97.26	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Cond Coverage for Module : edn

	Total	Covered	Percent
Conditions	6	5	83.33
Logical	6	5	83.33
Non-Logical	0	0
Event	0	0

 LINE       99
 EXPRESSION (alert[0] || intg_err_alert[0])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T16,T17,T18

 LINE       99
 EXPRESSION (alert[1] || intg_err_alert[1])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T24,T25,T26
1	0	Covered	T3,T4,T5

---

Toggle Coverage for Module : edn

	Total	Covered	Percent
Totals	69	69	100.00
Total Bits	1168	1168	100.00
Total Bits 0->1	584	584	100.00
Total Bits 1->0	584	584	100.00

Ports	69	69	100.00
Port Bits	1168	1168	100.00
Port Bits 0->1	584	584	100.00
Port Bits 1->0	584	584	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T3,T4,T5	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T23,T5,T27	Yes	T23,T5,T27	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T4	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T20,T21	Yes	T1,T19,T20	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T4	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T27,T28,T29	Yes	T27,T28,T29	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i[0].edn_req	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
edn_i[1].edn_req	Yes	Yes	T1,T16,T30	Yes	T1,T16,T30	INPUT
edn_i[2].edn_req	Yes	Yes	T2,T31,T32	Yes	T2,T31,T32	INPUT
edn_i[3].edn_req	Yes	Yes	T2,T9,T30	Yes	T2,T9,T30	INPUT
edn_i[4].edn_req	Yes	Yes	T9,T30,T33	Yes	T9,T30,T33	INPUT
edn_i[5].edn_req	Yes	Yes	T9,T34,T30	Yes	T9,T34,T30	INPUT
edn_i[6].edn_req	Yes	Yes	T9,T17,T35	Yes	T9,T17,T35	INPUT
edn_o[0].edn_bus[31:0]	Yes	Yes	T1,T4,T20	Yes	T1,T4,T20	OUTPUT
edn_o[0].edn_fips	Yes	Yes	T1,T23,T36	Yes	T1,T20,T23	OUTPUT
edn_o[0].edn_ack	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
edn_o[1].edn_bus[31:0]	Yes	Yes	T1,T16,T37	Yes	T1,T16,T37	OUTPUT
edn_o[1].edn_fips	Yes	Yes	T1,T32,T38	Yes	T1,T32,T38	OUTPUT
edn_o[1].edn_ack	Yes	Yes	T1,T16,T30	Yes	T1,T16,T30	OUTPUT
edn_o[2].edn_bus[31:0]	Yes	Yes	T2,T31,T32	Yes	T2,T31,T32	OUTPUT
edn_o[2].edn_fips	Yes	Yes	T31,T32,T38	Yes	T2,T31,T32	OUTPUT
edn_o[2].edn_ack	Yes	Yes	T2,T31,T32	Yes	T2,T31,T32	OUTPUT
edn_o[3].edn_bus[31:0]	Yes	Yes	T2,T9,T30	Yes	T2,T9,T30	OUTPUT
edn_o[3].edn_fips	Yes	Yes	T2,T32,T39	Yes	T2,T9,T32	OUTPUT
edn_o[3].edn_ack	Yes	Yes	T2,T9,T30	Yes	T2,T9,T30	OUTPUT
edn_o[4].edn_bus[31:0]	Yes	Yes	T33,T35,T40	Yes	T9,T30,T33	OUTPUT
edn_o[4].edn_fips	Yes	Yes	T33,T40,T41	Yes	T9,T30,T33	OUTPUT
edn_o[4].edn_ack	Yes	Yes	T9,T30,T33	Yes	T9,T30,T33	OUTPUT
edn_o[5].edn_bus[31:0]	Yes	Yes	T9,T30,T7	Yes	T9,T30,T7	OUTPUT
edn_o[5].edn_fips	Yes	Yes	T9,T30,T7	Yes	T9,T30,T7	OUTPUT
edn_o[5].edn_ack	Yes	Yes	T9,T30,T7	Yes	T9,T30,T7	OUTPUT
edn_o[6].edn_bus[31:0]	Yes	Yes	T9,T17,T41	Yes	T9,T17,T42	OUTPUT
edn_o[6].edn_fips	Yes	Yes	T9,T43,T44	Yes	T9,T43,T44	OUTPUT
edn_o[6].edn_ack	Yes	Yes	T9,T17,T35	Yes	T9,T17,T35	OUTPUT
csrng_cmd_o.genbits_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_i.genbits_bus[127:0]	Yes	Yes	T1,T2,T23	Yes	T1,T2,T21	INPUT
csrng_cmd_i.genbits_fips	Yes	Yes	T1,T2,T23	Yes	T1,T2,T23	INPUT
csrng_cmd_i.genbits_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_rsp_sts	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_rsp_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_req_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T19,T45,T46	Yes	T19,T45,T46	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T3,T19,T4	Yes	T3,T19,T4	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T19,T45,T46	Yes	T19,T45,T46	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T3,T19,T4	Yes	T3,T19,T4	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T47,T48,T49	Yes	T47,T48,T49	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	OUTPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Module : edn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	43	43	100.00	43	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	43	43	100.00	43	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnownO_A	194453532	194305799	0	0
CsrngAppIfOut_A	194453532	194305799	0	0
FpvSecCmCntAlertCheck_A	194453532	113	0	0
FpvSecCmMainFsmCheck_A	194453532	70	0	0
FpvSecCmRegWeOnehotCheck_A	194453532	70	0	0
IntrEdnCmdReqDoneKnownO_A	194453532	194305799	0	0
TlAReadyKnownO_A	194453532	194305799	0	0
TlDValidKnownO_A	194453532	194305799	0	0
gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A	194453532	70	0	0
gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A	194453532	70	0	0
gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A	194453532	70	0	0
gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A	194453532	70	0	0
gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A	194453532	70	0	0
gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A	194453532	70	0	0
gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A	194453532	70	0	0
gen_edn_if_asserts[0].EdnDataStableDisable_A	194453532	495463	0	0
gen_edn_if_asserts[0].EdnDataStable_A	194453532	18947	0	337
gen_edn_if_asserts[0].EdnEndPointOut_A	194453532	194305799	0	0
gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A	194453532	136020	0	0
gen_edn_if_asserts[1].EdnDataStableDisable_A	194453532	495463	0	0
gen_edn_if_asserts[1].EdnDataStable_A	194453532	4710	0	110
gen_edn_if_asserts[1].EdnEndPointOut_A	194453532	194305799	0	0
gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A	194453532	136020	0	0
gen_edn_if_asserts[2].EdnDataStableDisable_A	194453532	495463	0	0
gen_edn_if_asserts[2].EdnDataStable_A	194453532	4217	0	104
gen_edn_if_asserts[2].EdnEndPointOut_A	194453532	194305799	0	0
gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A	194453532	136020	0	0
gen_edn_if_asserts[3].EdnDataStableDisable_A	194453532	495463	0	0
gen_edn_if_asserts[3].EdnDataStable_A	194453532	3463	0	107
gen_edn_if_asserts[3].EdnEndPointOut_A	194453532	194305799	0	0
gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A	194453532	136020	0	0
gen_edn_if_asserts[4].EdnDataStableDisable_A	194453532	495463	0	0
gen_edn_if_asserts[4].EdnDataStable_A	194453532	5638	0	100
gen_edn_if_asserts[4].EdnEndPointOut_A	194453532	194305799	0	0
gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A	194453532	136020	0	0
gen_edn_if_asserts[5].EdnDataStableDisable_A	194453532	495463	0	0
gen_edn_if_asserts[5].EdnDataStable_A	194453532	4273	0	90
gen_edn_if_asserts[5].EdnEndPointOut_A	194453532	194305799	0	0
gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A	194453532	136020	0	0
gen_edn_if_asserts[6].EdnDataStableDisable_A	194453532	495463	0	0
gen_edn_if_asserts[6].EdnDataStable_A	194453532	3425	0	82
gen_edn_if_asserts[6].EdnEndPointOut_A	194453532	194305799	0	0
gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A	194453532	136020	0	0

AlertTxKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	194453532	194305799	0	0
T1	6691	6640	0	0
T2	1289	1219	0	0
T3	1730	1599	0	0
T4	921	781	0	0
T5	1848	1707	0	0
T19	1259	1179	0	0
T20	1062	998	0	0
T21	1124	1057	0	0
T22	1105	1050	0	0
T23	1168	1082	0	0

CsrngAppIfOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	194453532	194305799	0	0
T1	6691	6640	0	0
T2	1289	1219	0	0
T3	1730	1599	0	0
T4	921	781	0	0
T5	1848	1707	0	0
T19	1259	1179	0	0
T20	1062	998	0	0
T21	1124	1057	0	0
T22	1105	1050	0	0
T23	1168	1082	0	0

FpvSecCmCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	194453532	113	0	0
T13	1288	1	0	0
T14	885	1	0	0
T15	0	1	0	0
T38	2006	0	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	652	0	0	0
T58	247217	0	0	0
T59	1399	0	0	0
T60	346	0	0	0
T61	2114	0	0	0
T62	1450	0	0	0
T63	12358	0	0	0

FpvSecCmMainFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	194453532	70	0	0
T24	32519	20	0	0
T25	0	10	0	0
T26	0	10	0	0
T64	0	20	0	0
T65	0	10	0	0
T66	1435	0	0	0
T67	1007	0	0	0
T68	1007	0	0	0
T69	1039	0	0	0
T70	1680	0	0	0
T71	1625	0	0	0
T72	1486	0	0	0
T73	1107	0	0	0
T74	1299	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	194453532	70	0	0
T24	32519	20	0	0
T25	0	10	0	0
T26	0	10	0	0
T64	0	20	0	0
T65	0	10	0	0
T66	1435	0	0	0
T67	1007	0	0	0
T68	1007	0	0	0
T69	1039	0	0	0
T70	1680	0	0	0
T71	1625	0	0	0
T72	1486	0	0	0
T73	1107	0	0	0
T74	1299	0	0	0

IntrEdnCmdReqDoneKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	194453532	194305799	0	0
T1	6691	6640	0	0
T2	1289	1219	0	0
T3	1730	1599	0	0
T4	921	781	0	0
T5	1848	1707	0	0
T19	1259	1179	0	0
T20	1062	998	0	0
T21	1124	1057	0	0
T22	1105	1050	0	0
T23	1168	1082	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	194453532	194305799	0	0
T1	6691	6640	0	0
T2	1289	1219	0	0
T3	1730	1599	0	0
T4	921	781	0	0
T5	1848	1707	0	0
T19	1259	1179	0	0
T20	1062	998	0	0
T21	1124	1057	0	0
T22	1105	1050	0	0
T23	1168	1082	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	194453532	194305799	0	0
T1	6691	6640	0	0
T2	1289	1219	0	0
T3	1730	1599	0	0
T4	921	781	0	0
T5	1848	1707	0	0
T19	1259	1179	0	0
T20	1062	998	0	0
T21	1124	1057	0	0
T22	1105	1050	0	0
T23	1168	1082	0	0

gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	194453532	70	0	0
T24	32519	20	0	0
T25	0	10	0	0
T26	0	10	0	0
T64	0	20	0	0
T65	0	10	0	0
T66	1435	0	0	0
T67	1007	0	0	0
T68	1007	0	0	0
T69	1039	0	0	0
T70	1680	0	0	0
T71	1625	0	0	0
T72	1486	0	0	0
T73	1107	0	0	0
T74	1299	0	0	0

gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	194453532	70	0	0
T24	32519	20	0	0
T25	0	10	0	0
T26	0	10	0	0
T64	0	20	0	0
T65	0	10	0	0
T66	1435	0	0	0
T67	1007	0	0	0
T68	1007	0	0	0
T69	1039	0	0	0
T70	1680	0	0	0
T71	1625	0	0	0
T72	1486	0	0	0
T73	1107	0	0	0
T74	1299	0	0	0

gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	194453532	70	0	0
T24	32519	20	0	0
T25	0	10	0	0
T26	0	10	0	0
T64	0	20	0	0
T65	0	10	0	0
T66	1435	0	0	0
T67	1007	0	0	0
T68	1007	0	0	0
T69	1039	0	0	0
T70	1680	0	0	0
T71	1625	0	0	0
T72	1486	0	0	0
T73	1107	0	0	0
T74	1299	0	0	0

gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	194453532	70	0	0
T24	32519	20	0	0
T25	0	10	0	0
T26	0	10	0	0
T64	0	20	0	0
T65	0	10	0	0
T66	1435	0	0	0
T67	1007	0	0	0
T68	1007	0	0	0
T69	1039	0	0	0
T70	1680	0	0	0
T71	1625	0	0	0
T72	1486	0	0	0
T73	1107	0	0	0
T74	1299	0	0	0

gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	194453532	70	0	0
T24	32519	20	0	0
T25	0	10	0	0
T26	0	10	0	0
T64	0	20	0	0
T65	0	10	0	0
T66	1435	0	0	0
T67	1007	0	0	0
T68	1007	0	0	0
T69	1039	0	0	0
T70	1680	0	0	0
T71	1625	0	0	0
T72	1486	0	0	0
T73	1107	0	0	0
T74	1299	0	0	0

gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	194453532	70	0	0
T24	32519	20	0	0
T25	0	10	0	0
T26	0	10	0	0
T64	0	20	0	0
T65	0	10	0	0
T66	1435	0	0	0
T67	1007	0	0	0
T68	1007	0	0	0
T69	1039	0	0	0
T70	1680	0	0	0
T71	1625	0	0	0
T72	1486	0	0	0
T73	1107	0	0	0
T74	1299	0	0	0

gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	194453532	70	0	0
T24	32519	20	0	0
T25	0	10	0	0
T26	0	10	0	0
T64	0	20	0	0
T65	0	10	0	0
T66	1435	0	0	0
T67	1007	0	0	0
T68	1007	0	0	0
T69	1039	0	0	0
T70	1680	0	0	0
T71	1625	0	0	0
T72	1486	0	0	0
T73	1107	0	0	0
T74	1299	0	0	0

gen_edn_if_asserts[0].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	194453532	495463	0	0
T1	6691	300	0	0
T2	1289	38	0	0
T3	1730	884	0	0
T4	921	305	0	0
T5	1848	1033	0	0
T19	1259	1178	0	0
T20	1062	14	0	0
T21	1124	31	0	0
T22	1105	16	0	0
T23	1168	22	0	0

gen_edn_if_asserts[0].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	194453532	18947	0	337
T1	6691	1047	0	1
T2	1289	0	0	0
T3	1730	0	0	0
T4	921	0	0	0
T5	1848	0	0	0
T19	1259	0	0	0
T20	1062	3	0	1
T21	1124	7	0	1
T22	1105	3	0	1
T23	1168	15	0	1
T30	0	3	0	1
T36	0	131	0	0
T75	0	10	0	1
T76	0	3	0	1
T77	0	7	0	1
T78	0	0	0	1

gen_edn_if_asserts[0].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	194453532	194305799	0	0
T1	6691	6640	0	0
T2	1289	1219	0	0
T3	1730	1599	0	0
T4	921	781	0	0
T5	1848	1707	0	0
T19	1259	1179	0	0
T20	1062	998	0	0
T21	1124	1057	0	0
T22	1105	1050	0	0
T23	1168	1082	0	0

gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	194453532	136020	0	0
T3	1730	957	0	0
T4	921	405	0	0
T5	1848	1090	0	0
T6	1923	1086	0	0
T7	0	612	0	0
T19	1259	0	0	0
T20	1062	0	0	0
T21	1124	0	0	0
T22	1105	0	0	0
T23	1168	0	0	0
T34	0	362	0	0
T79	1582	312	0	0
T80	0	1105	0	0
T81	0	1102	0	0
T82	0	1140	0	0

gen_edn_if_asserts[1].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	194453532	495463	0	0
T1	6691	300	0	0
T2	1289	38	0	0
T3	1730	884	0	0
T4	921	305	0	0
T5	1848	1033	0	0
T19	1259	1178	0	0
T20	1062	14	0	0
T21	1124	31	0	0
T22	1105	16	0	0
T23	1168	22	0	0

gen_edn_if_asserts[1].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	194453532	4710	0	110
T1	6691	52	0	1
T2	1289	0	0	0
T3	1730	0	0	0
T4	921	0	0	0
T5	1848	0	0	0
T16	0	4	0	1
T19	1259	0	0	0
T20	1062	0	0	0
T21	1124	0	0	0
T22	1105	0	0	0
T23	1168	0	0	0
T30	0	3	0	1
T32	0	50	0	1
T38	0	31	0	1
T40	0	16	0	1
T41	0	56	0	1
T83	0	19	0	1
T84	0	11	0	1
T85	0	3	0	1

gen_edn_if_asserts[1].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	194453532	194305799	0	0
T1	6691	6640	0	0
T2	1289	1219	0	0
T3	1730	1599	0	0
T4	921	781	0	0
T5	1848	1707	0	0
T19	1259	1179	0	0
T20	1062	998	0	0
T21	1124	1057	0	0
T22	1105	1050	0	0
T23	1168	1082	0	0

gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	194453532	136020	0	0
T3	1730	957	0	0
T4	921	405	0	0
T5	1848	1090	0	0
T6	1923	1086	0	0
T7	0	612	0	0
T19	1259	0	0	0
T20	1062	0	0	0
T21	1124	0	0	0
T22	1105	0	0	0
T23	1168	0	0	0
T34	0	362	0	0
T79	1582	312	0	0
T80	0	1105	0	0
T81	0	1102	0	0
T82	0	1140	0	0

gen_edn_if_asserts[2].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	194453532	495463	0	0
T1	6691	300	0	0
T2	1289	38	0	0
T3	1730	884	0	0
T4	921	305	0	0
T5	1848	1033	0	0
T19	1259	1178	0	0
T20	1062	14	0	0
T21	1124	31	0	0
T22	1105	16	0	0
T23	1168	22	0	0

gen_edn_if_asserts[2].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	194453532	4217	0	104
T2	1289	3	0	1
T3	1730	0	0	0
T4	921	0	0	0
T5	1848	0	0	0
T10	0	3	0	1
T19	1259	0	0	0
T20	1062	0	0	0
T21	1124	0	0	0
T22	1105	0	0	0
T23	1168	0	0	0
T31	945	19	0	1
T32	0	57	0	1
T35	0	42	0	1
T38	0	63	0	1
T40	0	3	0	1
T83	0	3	0	1
T86	0	3	0	1
T87	0	3	0	1

gen_edn_if_asserts[2].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	194453532	194305799	0	0
T1	6691	6640	0	0
T2	1289	1219	0	0
T3	1730	1599	0	0
T4	921	781	0	0
T5	1848	1707	0	0
T19	1259	1179	0	0
T20	1062	998	0	0
T21	1124	1057	0	0
T22	1105	1050	0	0
T23	1168	1082	0	0

gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	194453532	136020	0	0
T3	1730	957	0	0
T4	921	405	0	0
T5	1848	1090	0	0
T6	1923	1086	0	0
T7	0	612	0	0
T19	1259	0	0	0
T20	1062	0	0	0
T21	1124	0	0	0
T22	1105	0	0	0
T23	1168	0	0	0
T34	0	362	0	0
T79	1582	312	0	0
T80	0	1105	0	0
T81	0	1102	0	0
T82	0	1140	0	0

gen_edn_if_asserts[3].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	194453532	495463	0	0
T1	6691	300	0	0
T2	1289	38	0	0
T3	1730	884	0	0
T4	921	305	0	0
T5	1848	1033	0	0
T19	1259	1178	0	0
T20	1062	14	0	0
T21	1124	31	0	0
T22	1105	16	0	0
T23	1168	22	0	0

gen_edn_if_asserts[3].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	194453532	3463	0	107
T2	1289	35	0	1
T3	1730	0	0	0
T4	921	0	0	0
T5	1848	0	0	0
T9	2947	3	0	1
T18	0	4	0	1
T19	1259	0	0	0
T20	1062	0	0	0
T21	1124	0	0	0
T22	1105	0	0	0
T23	1168	0	0	0
T30	0	3	0	1
T32	0	21	0	1
T38	0	3	0	1
T39	0	11	0	1
T40	0	3	0	1
T41	0	13	0	1
T88	0	3	0	1

gen_edn_if_asserts[3].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	194453532	194305799	0	0
T1	6691	6640	0	0
T2	1289	1219	0	0
T3	1730	1599	0	0
T4	921	781	0	0
T5	1848	1707	0	0
T19	1259	1179	0	0
T20	1062	998	0	0
T21	1124	1057	0	0
T22	1105	1050	0	0
T23	1168	1082	0	0

gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	194453532	136020	0	0
T3	1730	957	0	0
T4	921	405	0	0
T5	1848	1090	0	0
T6	1923	1086	0	0
T7	0	612	0	0
T19	1259	0	0	0
T20	1062	0	0	0
T21	1124	0	0	0
T22	1105	0	0	0
T23	1168	0	0	0
T34	0	362	0	0
T79	1582	312	0	0
T80	0	1105	0	0
T81	0	1102	0	0
T82	0	1140	0	0

gen_edn_if_asserts[4].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	194453532	495463	0	0
T1	6691	300	0	0
T2	1289	38	0	0
T3	1730	884	0	0
T4	921	305	0	0
T5	1848	1033	0	0
T19	1259	1178	0	0
T20	1062	14	0	0
T21	1124	31	0	0
T22	1105	16	0	0
T23	1168	22	0	0

gen_edn_if_asserts[4].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	194453532	5638	0	100
T7	2188	0	0	0
T9	2947	3	0	1
T16	1689	0	0	0
T30	1235	3	0	1
T33	0	42	0	1
T34	751	0	0	0
T35	0	3	0	1
T36	609242	0	0	0
T40	0	32	0	1
T41	0	1149	0	1
T75	1058	0	0	0
T76	1086	0	0	0
T80	1958	0	0	0
T81	2827	0	0	0
T83	0	37	0	1
T84	0	3	0	1
T89	0	3	0	0
T90	0	5	0	1
T91	0	0	0	1

gen_edn_if_asserts[4].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	194453532	194305799	0	0
T1	6691	6640	0	0
T2	1289	1219	0	0
T3	1730	1599	0	0
T4	921	781	0	0
T5	1848	1707	0	0
T19	1259	1179	0	0
T20	1062	998	0	0
T21	1124	1057	0	0
T22	1105	1050	0	0
T23	1168	1082	0	0

gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	194453532	136020	0	0
T3	1730	957	0	0
T4	921	405	0	0
T5	1848	1090	0	0
T6	1923	1086	0	0
T7	0	612	0	0
T19	1259	0	0	0
T20	1062	0	0	0
T21	1124	0	0	0
T22	1105	0	0	0
T23	1168	0	0	0
T34	0	362	0	0
T79	1582	312	0	0
T80	0	1105	0	0
T81	0	1102	0	0
T82	0	1140	0	0

gen_edn_if_asserts[5].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	194453532	495463	0	0
T1	6691	300	0	0
T2	1289	38	0	0
T3	1730	884	0	0
T4	921	305	0	0
T5	1848	1033	0	0
T19	1259	1178	0	0
T20	1062	14	0	0
T21	1124	31	0	0
T22	1105	16	0	0
T23	1168	22	0	0

gen_edn_if_asserts[5].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	194453532	4273	0	90
T7	2188	0	0	0
T9	2947	46	0	1
T16	1689	0	0	0
T30	1235	18	0	1
T32	0	3	0	1
T33	0	3	0	1
T34	751	0	0	0
T36	609242	0	0	0
T40	0	7	0	1
T41	0	32	0	1
T44	0	32	0	1
T75	1058	0	0	0
T76	1086	0	0	0
T80	1958	0	0	0
T81	2827	0	0	0
T83	0	27	0	1
T84	0	3	0	1
T92	0	4	0	1

gen_edn_if_asserts[5].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	194453532	194305799	0	0
T1	6691	6640	0	0
T2	1289	1219	0	0
T3	1730	1599	0	0
T4	921	781	0	0
T5	1848	1707	0	0
T19	1259	1179	0	0
T20	1062	998	0	0
T21	1124	1057	0	0
T22	1105	1050	0	0
T23	1168	1082	0	0

gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	194453532	136020	0	0
T3	1730	957	0	0
T4	921	405	0	0
T5	1848	1090	0	0
T6	1923	1086	0	0
T7	0	612	0	0
T19	1259	0	0	0
T20	1062	0	0	0
T21	1124	0	0	0
T22	1105	0	0	0
T23	1168	0	0	0
T34	0	362	0	0
T79	1582	312	0	0
T80	0	1105	0	0
T81	0	1102	0	0
T82	0	1140	0	0

gen_edn_if_asserts[6].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	194453532	495463	0	0
T1	6691	300	0	0
T2	1289	38	0	0
T3	1730	884	0	0
T4	921	305	0	0
T5	1848	1033	0	0
T19	1259	1178	0	0
T20	1062	14	0	0
T21	1124	31	0	0
T22	1105	16	0	0
T23	1168	22	0	0

gen_edn_if_asserts[6].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	194453532	3425	0	82
T7	2188	0	0	0
T9	2947	207	0	1
T16	1689	0	0	0
T17	0	4	0	1
T30	1235	0	0	0
T34	751	0	0	0
T35	0	3	0	1
T36	609242	0	0	0
T40	0	3	0	1
T41	0	3	0	1
T43	0	18	0	1
T44	0	0	0	1
T75	1058	0	0	0
T76	1086	0	0	0
T80	1958	0	0	0
T81	2827	0	0	0
T83	0	3	0	1
T84	0	3	0	1
T87	0	3	0	1
T93	0	3	0	0

gen_edn_if_asserts[6].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	194453532	194305799	0	0
T1	6691	6640	0	0
T2	1289	1219	0	0
T3	1730	1599	0	0
T4	921	781	0	0
T5	1848	1707	0	0
T19	1259	1179	0	0
T20	1062	998	0	0
T21	1124	1057	0	0
T22	1105	1050	0	0
T23	1168	1082	0	0

gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	194453532	136020	0	0
T3	1730	957	0	0
T4	921	405	0	0
T5	1848	1090	0	0
T6	1923	1086	0	0
T7	0	612	0	0
T19	1259	0	0	0
T20	1062	0	0	0
T21	1124	0	0	0
T22	1105	0	0	0
T23	1168	0	0	0
T34	0	362	0	0
T79	1582	312	0	0
T80	0	1105	0	0
T81	0	1102	0	0
T82	0	1140	0	0