Unified Coverage Report :: Module :: edn_reg_top

Module : edn_reg_top

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_reg_top.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.63	96.98	98.92	100.00		97.26	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44		83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_alert_test_fatal_alert	100.00	100.00
u_alert_test_recov_alert	100.00	100.00
u_boot_gen_cmd	100.00	100.00	100.00			100.00
u_boot_ins_cmd	100.00	100.00	100.00			100.00
u_chk	100.00	100.00		100.00			100.00
u_ctrl_auto_req_mode	100.00	100.00	100.00			100.00
u_ctrl_boot_req_mode	100.00	100.00	100.00			100.00
u_ctrl_cmd_fifo_rst	100.00	100.00	100.00			100.00
u_ctrl_edn_enable	100.00	100.00	100.00			100.00
u_err_code_edn_ack_sm_err	96.30	88.89	100.00			100.00
u_err_code_edn_cntr_err	96.30	88.89	100.00			100.00
u_err_code_edn_main_sm_err	96.30	88.89	100.00			100.00
u_err_code_fifo_read_err	96.30	88.89	100.00			100.00
u_err_code_fifo_state_err	96.30	88.89	100.00			100.00
u_err_code_fifo_write_err	96.30	88.89	100.00			100.00
u_err_code_sfifo_gencmd_err	96.30	88.89	100.00			100.00
u_err_code_sfifo_output_err	62.59	77.78	50.00			60.00
u_err_code_sfifo_rescmd_err	96.30	88.89	100.00			100.00
u_err_code_test	100.00	100.00	100.00			100.00
u_err_code_test0_qe	100.00	100.00				100.00
u_generate_cmd	100.00	100.00
u_intr_enable_edn_cmd_req_done	100.00	100.00	100.00			100.00
u_intr_enable_edn_fatal_err	100.00	100.00	100.00			100.00
u_intr_state_edn_cmd_req_done	100.00	100.00	100.00			100.00
u_intr_state_edn_fatal_err	100.00	100.00	100.00			100.00
u_intr_test_edn_cmd_req_done	100.00	100.00
u_intr_test_edn_fatal_err	100.00	100.00
u_main_sm_state	62.59	77.78	50.00			60.00
u_max_num_reqs_between_reseeds	100.00	100.00	100.00			100.00
u_max_num_reqs_between_reseeds0_qe	100.00	100.00				100.00
u_prim_reg_we_check	100.00	100.00		100.00
u_recov_alert_sts_auto_req_mode_field_alert	100.00	100.00	100.00			100.00
u_recov_alert_sts_boot_req_mode_field_alert	100.00	100.00	100.00			100.00
u_recov_alert_sts_cmd_fifo_rst_field_alert	100.00	100.00	100.00			100.00
u_recov_alert_sts_edn_bus_cmp_alert	100.00	100.00	100.00			100.00
u_recov_alert_sts_edn_enable_field_alert	100.00	100.00	100.00			100.00
u_reg_if	98.67	97.14	97.53			100.00	100.00
u_regwen	100.00	100.00	100.00			100.00
u_reseed_cmd	100.00	100.00
u_rsp_intg_gen	100.00	100.00					100.00
u_sw_cmd_req	100.00	100.00
u_sw_cmd_sts_cmd_rdy	62.59	77.78	50.00			60.00
u_sw_cmd_sts_cmd_sts	100.00	100.00	100.00			100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : edn_reg_top

	Line No.	Total	Covered	Percent
TOTAL		142	142	100.00
ALWAYS	71	4	4	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	313	1	1	100.00
CONT_ASSIGN	328	1	1	100.00
CONT_ASSIGN	344	1	1	100.00
CONT_ASSIGN	350	1	1	100.00
CONT_ASSIGN	365	1	1	100.00
CONT_ASSIGN	381	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	584	1	1	100.00
CONT_ASSIGN	598	1	1	100.00
CONT_ASSIGN	660	1	1	100.00
CONT_ASSIGN	674	1	1	100.00
CONT_ASSIGN	680	1	1	100.00
CONT_ASSIGN	694	1	1	100.00
CONT_ASSIGN	734	1	1	100.00
CONT_ASSIGN	1156	1	1	100.00
ALWAYS	1190	18	18	100.00
CONT_ASSIGN	1210	1	1	100.00
ALWAYS	1214	1	1	100.00
CONT_ASSIGN	1235	1	1	100.00
CONT_ASSIGN	1237	1	1	100.00
CONT_ASSIGN	1239	1	1	100.00
CONT_ASSIGN	1240	1	1	100.00
CONT_ASSIGN	1242	1	1	100.00
CONT_ASSIGN	1244	1	1	100.00
CONT_ASSIGN	1245	1	1	100.00
CONT_ASSIGN	1247	1	1	100.00
CONT_ASSIGN	1249	1	1	100.00
CONT_ASSIGN	1250	1	1	100.00
CONT_ASSIGN	1252	1	1	100.00
CONT_ASSIGN	1254	1	1	100.00
CONT_ASSIGN	1255	1	1	100.00
CONT_ASSIGN	1257	1	1	100.00
CONT_ASSIGN	1258	1	1	100.00
CONT_ASSIGN	1260	1	1	100.00
CONT_ASSIGN	1262	1	1	100.00
CONT_ASSIGN	1264	1	1	100.00
CONT_ASSIGN	1266	1	1	100.00
CONT_ASSIGN	1267	1	1	100.00
CONT_ASSIGN	1269	1	1	100.00
CONT_ASSIGN	1270	1	1	100.00
CONT_ASSIGN	1272	1	1	100.00
CONT_ASSIGN	1273	1	1	100.00
CONT_ASSIGN	1275	1	1	100.00
CONT_ASSIGN	1276	1	1	100.00
CONT_ASSIGN	1278	1	1	100.00
CONT_ASSIGN	1279	1	1	100.00
CONT_ASSIGN	1281	1	1	100.00
CONT_ASSIGN	1282	1	1	100.00
CONT_ASSIGN	1284	1	1	100.00
CONT_ASSIGN	1285	1	1	100.00
CONT_ASSIGN	1287	1	1	100.00
CONT_ASSIGN	1289	1	1	100.00
CONT_ASSIGN	1291	1	1	100.00
CONT_ASSIGN	1293	1	1	100.00
CONT_ASSIGN	1295	1	1	100.00
CONT_ASSIGN	1296	1	1	100.00
CONT_ASSIGN	1298	1	1	100.00
ALWAYS	1302	18	18	100.00
ALWAYS	1324	39	39	100.00
CONT_ASSIGN	1425	0	0
CONT_ASSIGN	1433	1	1	100.00
CONT_ASSIGN	1434	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_reg_top.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_reg_top.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
71	1	1
72	1	1
73	1	1
74	1	1
			MISSING_ELSE
80	1	1
92	1	1
93	1	1
121	1	1
122	1	1
313	1	1
328	1	1
344	1	1
350	1	1
365	1	1
381	1	1
415	1	1
584	1	1
598	1	1
660	1	1
674	1	1
680	1	1
694	1	1
734	1	1
1156	1	1
1190	1	1
1191	1	1
1192	1	1
1193	1	1
1194	1	1
1195	1	1
1196	1	1
1197	1	1
1198	1	1
1199	1	1
1200	1	1
1201	1	1
1202	1	1
1203	1	1
1204	1	1
1205	1	1
1206	1	1
1207	1	1
1210	1	1
1214	1	1
1235	1	1
1237	1	1
1239	1	1
1240	1	1
1242	1	1
1244	1	1
1245	1	1
1247	1	1
1249	1	1
1250	1	1
1252	1	1
1254	1	1
1255	1	1
1257	1	1
1258	1	1
1260	1	1
1262	1	1
1264	1	1
1266	1	1
1267	1	1
1269	1	1
1270	1	1
1272	1	1
1273	1	1
1275	1	1
1276	1	1
1278	1	1
1279	1	1
1281	1	1
1282	1	1
1284	1	1
1285	1	1
1287	1	1
1289	1	1
1291	1	1
1293	1	1
1295	1	1
1296	1	1
1298	1	1
1302	1	1
1303	1	1
1304	1	1
1305	1	1
1306	1	1
1307	1	1
1308	1	1
1309	1	1
1310	1	1
1311	1	1
1312	1	1
1313	1	1
1314	1	1
1315	1	1
1316	1	1
1317	1	1
1318	1	1
1319	1	1
1324	1	1
1325	1	1
1327	1	1
1328	1	1
1332	1	1
1333	1	1
1337	1	1
1338	1	1
1342	1	1
1343	1	1
1347	1	1
1351	1	1
1352	1	1
1353	1	1
1354	1	1
1358	1	1
1362	1	1
1366	1	1
1370	1	1
1371	1	1
1375	1	1
1379	1	1
1383	1	1
1387	1	1
1388	1	1
1389	1	1
1390	1	1
1391	1	1
1395	1	1
1396	1	1
1397	1	1
1398	1	1
1399	1	1
1400	1	1
1401	1	1
1402	1	1
1403	1	1
1407	1	1
1411	1	1
1425		unreachable
1433	1	1
1434	1	1

---

Cond Coverage for Module : edn_reg_top

	Total	Covered	Percent
Conditions	186	186	100.00
Logical	186	186	100.00
Non-Logical	0	0
Event	0	0

 LINE       61
 EXPRESSION (reg_we && ((!addrmiss)))
             ---1--    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T27,T28,T46
1	1	Covered	T1,T2,T3

 LINE       73
 EXPRESSION (intg_err || reg_we_err)
             ----1---    -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T24,T25,T26
1	0	Covered	T46,T141,T154

 LINE       80
 EXPRESSION (err_q | intg_err | reg_we_err)
             --1--   ----2---   -----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T24,T25,T26
0	1	0	Covered	T46,T141,T154
1	0	0	Covered	T46,T141,T154

 LINE       122
 EXPRESSION ((devmode_i & addrmiss) | wr_err | intg_err)
             -----------1----------   ---2--   ----3---

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T46,T141,T154
0	1	0	Covered	T27,T28,T137
1	0	0	Covered	T27,T28,T139

 LINE       122
 SUB-EXPRESSION (devmode_i & addrmiss)
                 ----1----   ----2---

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Covered	T1,T2,T3
1	1	Covered	T27,T28,T46

 LINE       415
 EXPRESSION (ctrl_we & regwen_qs)
             ---1---   ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T277,T278,T279
1	1	Covered	T1,T2,T3

 LINE       1191
 EXPRESSION (reg_addr == edn_reg_pkg::EDN_INTR_STATE_OFFSET)
            ------------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1192
 EXPRESSION (reg_addr == edn_reg_pkg::EDN_INTR_ENABLE_OFFSET)
            ------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T23

 LINE       1193
 EXPRESSION (reg_addr == edn_reg_pkg::EDN_INTR_TEST_OFFSET)
            -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T23,T5,T27

 LINE       1194
 EXPRESSION (reg_addr == edn_reg_pkg::EDN_ALERT_TEST_OFFSET)
            ------------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T19,T23,T27

 LINE       1195
 EXPRESSION (reg_addr == edn_reg_pkg::EDN_REGWEN_OFFSET)
            ----------------------1---------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T23,T27,T45

 LINE       1196
 EXPRESSION (reg_addr == edn_reg_pkg::EDN_CTRL_OFFSET)
            ---------------------1--------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1197
 EXPRESSION (reg_addr == edn_reg_pkg::EDN_BOOT_INS_CMD_OFFSET)
            -------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T21,T23

 LINE       1198
 EXPRESSION (reg_addr == edn_reg_pkg::EDN_BOOT_GEN_CMD_OFFSET)
            -------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T21,T23

 LINE       1199
 EXPRESSION (reg_addr == edn_reg_pkg::EDN_SW_CMD_REQ_OFFSET)
            ------------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1200
 EXPRESSION (reg_addr == edn_reg_pkg::EDN_SW_CMD_STS_OFFSET)
            ------------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1201
 EXPRESSION (reg_addr == edn_reg_pkg::EDN_RESEED_CMD_OFFSET)
            ------------------------1-----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T23,T5

 LINE       1202
 EXPRESSION (reg_addr == edn_reg_pkg::EDN_GENERATE_CMD_OFFSET)
            -------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T23,T5

 LINE       1203
 EXPRESSION (reg_addr == edn_reg_pkg::EDN_MAX_NUM_REQS_BETWEEN_RESEEDS_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T23,T5

 LINE       1204
 EXPRESSION (reg_addr == edn_reg_pkg::EDN_RECOV_ALERT_STS_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T27,T45,T28

 LINE       1205
 EXPRESSION (reg_addr == edn_reg_pkg::EDN_ERR_CODE_OFFSET)
            -----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T23,T5,T27

 LINE       1206
 EXPRESSION (reg_addr == edn_reg_pkg::EDN_ERR_CODE_TEST_OFFSET)
            -------------------------1-------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T20,T21

 LINE       1207
 EXPRESSION (reg_addr == edn_reg_pkg::EDN_MAIN_SM_STATE_OFFSET)
            -------------------------1-------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T23,T5,T27

 LINE       1210
 EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1210
 SUB-EXPRESSION (reg_re || reg_we)
                 ---1--    ---2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       1214
 EXPRESSION 
 Number  Term
      1  reg_we & 
      2  ((addr_hit[0] & ((|(4'b1 & (~reg_be))))) | (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | (addr_hit[5] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[6] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[7] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[8] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[9] & ((|(4'b1 & (~reg_be))))) | (addr_hit[10] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[11] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[12] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[13] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[14] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[15] & ((|(4'b1 & (~reg_be))))) | (addr_hit[16] & ((|(4'b0011 & (~reg_be)))))))

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T27,T28,T46

 LINE       1214
 SUB-EXPRESSION 
 Number  Term
      1  (addr_hit[0] & ((|(4'b1 & (~reg_be))))) | 
      2  (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | 
      3  (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | 
      4  (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | 
      5  (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | 
      6  (addr_hit[5] & ((|(4'b0011 & (~reg_be))))) | 
      7  (addr_hit[6] & ((|(4'b1111 & (~reg_be))))) | 
      8  (addr_hit[7] & ((|(4'b1111 & (~reg_be))))) | 
      9  (addr_hit[8] & ((|(4'b1111 & (~reg_be))))) | 
     10  (addr_hit[9] & ((|(4'b1 & (~reg_be))))) | 
     11  (addr_hit[10] & ((|(4'b1111 & (~reg_be))))) | 
     12  (addr_hit[11] & ((|(4'b1111 & (~reg_be))))) | 
     13  (addr_hit[12] & ((|(4'b1111 & (~reg_be))))) | 
     14  (addr_hit[13] & ((|(4'b0011 & (~reg_be))))) | 
     15  (addr_hit[14] & ((|(4'b1111 & (~reg_be))))) | 
     16  (addr_hit[15] & ((|(4'b1 & (~reg_be))))) | 
     17  (addr_hit[16] & ((|(4'b0011 & (~reg_be))))))

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	-17-	Status	Tests
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	Covered	T1,T2,T3
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	Covered	T23,T5,T27
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	Covered	T27,T28,T29
0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	Covered	T23,T5,T27
0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	Covered	T27,T28,T29
0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	0	Covered	T23,T5,T27
0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	Covered	T23,T5,T27
0	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	Covered	T23,T5,T27
0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	Covered	T23,T27,T28
0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	Covered	T23,T5,T27
0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	Covered	T23,T5,T27
0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	Covered	T23,T5,T27
0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	0	Covered	T23,T5,T27
0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	Covered	T23,T27,T28
0	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	Covered	T23,T27,T28
0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	Covered	T5,T27,T47
0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	Covered	T27,T47,T28
1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	Covered	T1,T2,T3

 LINE       1214
 SUB-EXPRESSION (addr_hit[0] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T23,T5,T27
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       1214
 SUB-EXPRESSION (addr_hit[1] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T23
1	1	Covered	T27,T47,T28

 LINE       1214
 SUB-EXPRESSION (addr_hit[2] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T23,T5,T27
1	1	Covered	T5,T27,T47

 LINE       1214
 SUB-EXPRESSION (addr_hit[3] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T19,T27,T45
1	1	Covered	T23,T27,T28

 LINE       1214
 SUB-EXPRESSION (addr_hit[4] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T27,T45,T28
1	1	Covered	T23,T27,T28

 LINE       1214
 SUB-EXPRESSION (addr_hit[5] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T23,T5,T27

 LINE       1214
 SUB-EXPRESSION (addr_hit[6] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T21,T27
1	1	Covered	T23,T5,T27

 LINE       1214
 SUB-EXPRESSION (addr_hit[7] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T21,T27
1	1	Covered	T23,T5,T27

 LINE       1214
 SUB-EXPRESSION (addr_hit[8] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T23,T5,T27

 LINE       1214
 SUB-EXPRESSION (addr_hit[9] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T23,T27,T28

 LINE       1214
 SUB-EXPRESSION (addr_hit[10] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T27,T45
1	1	Covered	T23,T5,T27

 LINE       1214
 SUB-EXPRESSION (addr_hit[11] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T27,T45
1	1	Covered	T23,T5,T27

 LINE       1214
 SUB-EXPRESSION (addr_hit[12] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T23,T27
1	1	Covered	T23,T5,T27

 LINE       1214
 SUB-EXPRESSION (addr_hit[13] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T27,T45,T28
1	1	Covered	T27,T28,T29

 LINE       1214
 SUB-EXPRESSION (addr_hit[14] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T27,T45,T28
1	1	Covered	T23,T5,T27

 LINE       1214
 SUB-EXPRESSION (addr_hit[15] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T20,T21
1	1	Covered	T27,T28,T29

 LINE       1214
 SUB-EXPRESSION (addr_hit[16] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T27,T45,T28
1	1	Covered	T23,T5,T27

 LINE       1235
 EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T28,T139,T163
1	1	1	Covered	T1,T2,T3

 LINE       1240
 EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T4,T23
1	1	0	Covered	T27,T28,T155
1	1	1	Covered	T3,T4,T5

 LINE       1245
 EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T23,T5,T27
1	1	0	Covered	T27,T28,T139
1	1	1	Covered	T47,T48,T153

 LINE       1250
 EXPRESSION (addr_hit[3] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T19,T23,T27
1	1	0	Covered	T27,T28,T137
1	1	1	Covered	T19,T45,T29

 LINE       1255
 EXPRESSION (addr_hit[4] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T23,T27,T45
1	1	0	Covered	T27,T28,T139
1	1	1	Covered	T45,T29,T46

 LINE       1258
 EXPRESSION (addr_hit[5] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T27,T28,T137
1	1	1	Covered	T1,T2,T3

 LINE       1267
 EXPRESSION (addr_hit[6] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T21,T23
1	1	0	Covered	T27,T28,T46
1	1	1	Covered	T2,T21,T31

 LINE       1270
 EXPRESSION (addr_hit[7] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T21,T23
1	1	0	Covered	T27,T28,T139
1	1	1	Covered	T2,T21,T31

 LINE       1273
 EXPRESSION (addr_hit[8] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T27,T28,T46
1	1	1	Covered	T1,T2,T3

 LINE       1276
 EXPRESSION (addr_hit[10] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T23,T5
1	1	0	Covered	T27,T28,T139
1	1	1	Covered	T1,T45,T29

 LINE       1279
 EXPRESSION (addr_hit[11] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T23,T5
1	1	0	Covered	T27,T28,T140
1	1	1	Covered	T1,T45,T29

 LINE       1282
 EXPRESSION (addr_hit[12] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T23,T5
1	1	0	Covered	T27,T28,T137
1	1	1	Covered	T1,T45,T29

 LINE       1285
 EXPRESSION (addr_hit[13] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T27,T45,T28
1	1	0	Covered	T27,T28,T46
1	1	1	Covered	T45,T29,T46

 LINE       1296
 EXPRESSION (addr_hit[15] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T20,T21
1	1	0	Covered	T27,T28,T139
1	1	1	Covered	T2,T20,T21

---

Branch Coverage for Module : edn_reg_top

	Line No.	Total	Covered	Percent
Branches		23	23	100.00
TERNARY	1210	2	2	100.00
IF	71	3	3	100.00
CASE	1325	18	18	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_reg_top.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	1210	((reg_re || reg_we)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	71	if ((!rst_ni))
-2-:	73	if ((intg_err || reg_we_err))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T46,T141,T154
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1325	case (1'b1)

Branches:

-1-	Status	Tests
addr_hit[0]	Covered	T1,T2,T3
addr_hit[1]	Covered	T1,T2,T3
addr_hit[2]	Covered	T1,T2,T3
addr_hit[3]	Covered	T1,T2,T3
addr_hit[4]	Covered	T1,T2,T3
addr_hit[5]	Covered	T1,T2,T3
addr_hit[6]	Covered	T1,T2,T3
addr_hit[7]	Covered	T1,T2,T3
addr_hit[8]	Covered	T1,T2,T3
addr_hit[9]	Covered	T1,T2,T3
addr_hit[10]	Covered	T1,T2,T3
addr_hit[11]	Covered	T1,T2,T3
addr_hit[12]	Covered	T1,T2,T3
addr_hit[13]	Covered	T1,T2,T3
addr_hit[14]	Covered	T1,T2,T3
addr_hit[15]	Covered	T1,T2,T3
addr_hit[16]	Covered	T1,T2,T3
default	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_reg_top

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
en2addrHit	194950714	679996	0	0
reAfterRv	194950714	679989	0	0
rePulse	194950714	256917	0	0
wePulse	194950714	423072	0	0

en2addrHit

Name	Attempts	Real Successes	Failures	Incomplete
Total	194950714	679996	0	0
T1	6691	128	0	0
T2	1289	46	0	0
T3	1730	25	0	0
T4	921	25	0	0
T5	1848	44	0	0
T19	1259	43	0	0
T20	1062	62	0	0
T21	1124	35	0	0
T22	1105	50	0	0
T23	1168	59	0	0

reAfterRv

Name	Attempts	Real Successes	Failures	Incomplete
Total	194950714	679989	0	0
T1	6691	128	0	0
T2	1289	46	0	0
T3	1730	25	0	0
T4	921	25	0	0
T5	1848	44	0	0
T19	1259	43	0	0
T20	1062	62	0	0
T21	1124	35	0	0
T22	1105	50	0	0
T23	1168	59	0	0

rePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	194950714	256917	0	0
T1	6691	63	0	0
T2	1289	33	0	0
T3	1730	15	0	0
T4	921	15	0	0
T5	1848	34	0	0
T19	1259	1	0	0
T20	1062	54	0	0
T21	1124	25	0	0
T22	1105	29	0	0
T23	1168	38	0	0

wePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	194950714	423072	0	0
T1	6691	65	0	0
T2	1289	13	0	0
T3	1730	10	0	0
T4	921	10	0	0
T5	1848	10	0	0
T19	1259	42	0	0
T20	1062	8	0	0
T21	1124	10	0	0
T22	1105	21	0	0
T23	1168	21	0	0