Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44		83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	212520222	9506864	0	0
boot_gen_cmd_rd_A	212520222	71686	0	0
boot_ins_cmd_rd_A	212520222	84973	0	0
ctrl_rd_A	212520222	73562	0	0
err_code_test_rd_A	212520222	74100	0	0
intr_enable_rd_A	212520222	79894	0	0
max_num_reqs_between_reseeds_rd_A	212520222	85144	0	0
regwen_rd_A	212520222	85233	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212520222	9506864	0	0
T20	8261	11	0	0
T21	757	0	0	0
T22	864	0	0	0
T23	1132	0	0	0
T24	3396	4	0	0
T25	889	0	0	0
T26	17660	12	0	0
T27	958	0	0	0
T28	1436	0	0	0
T128	0	24	0	0
T129	0	62	0	0
T130	0	1230	0	0
T131	0	4	0	0
T132	0	36	0	0
T133	0	7	0	0
T134	0	39	0	0
T135	2127	0	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212520222	71686	0	0
T133	10616	6	0	0
T134	2142	13	0	0
T136	5797	9	0	0
T137	0	34	0	0
T138	0	23	0	0
T139	0	10	0	0
T140	0	10	0	0
T141	0	25	0	0
T142	0	6	0	0
T143	0	10	0	0
T144	3696	0	0	0
T145	1263	0	0	0
T146	1216	0	0	0
T147	4519	0	0	0
T148	1278	0	0	0
T149	1084	0	0	0
T150	1086	0	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212520222	84973	0	0
T134	2142	17	0	0
T136	5797	8	0	0
T137	3808	50	0	0
T138	0	26	0	0
T139	0	13	0	0
T140	0	13	0	0
T141	0	23	0	0
T142	0	57	0	0
T143	0	10	0	0
T144	3696	0	0	0
T145	1263	0	0	0
T146	1216	0	0	0
T147	4519	0	0	0
T148	1278	0	0	0
T149	1084	0	0	0
T150	1086	0	0	0
T151	0	10	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212520222	73562	0	0
T134	2142	12	0	0
T136	5797	2	0	0
T137	3808	36	0	0
T138	0	35	0	0
T139	0	30	0	0
T140	0	23	0	0
T141	0	14	0	0
T142	0	26	0	0
T143	0	3	0	0
T144	3696	0	0	0
T145	1263	0	0	0
T146	1216	0	0	0
T147	4519	0	0	0
T148	1278	0	0	0
T149	1084	0	0	0
T150	1086	0	0	0
T152	0	46	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212520222	74100	0	0
T134	2142	10	0	0
T136	5797	31	0	0
T137	3808	35	0	0
T138	0	60	0	0
T139	0	13	0	0
T140	0	27	0	0
T141	0	48	0	0
T142	0	18	0	0
T143	0	9	0	0
T144	3696	0	0	0
T145	1263	0	0	0
T146	1216	0	0	0
T147	4519	0	0	0
T148	1278	0	0	0
T149	1084	0	0	0
T150	1086	0	0	0
T151	0	6	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212520222	79894	0	0
T20	8261	82	0	0
T21	757	0	0	0
T22	864	0	0	0
T23	1132	0	0	0
T24	3396	0	0	0
T25	889	0	0	0
T26	17660	0	0	0
T27	958	0	0	0
T28	1436	33	0	0
T133	0	129	0	0
T134	0	19	0	0
T135	2127	0	0	0
T136	0	1	0	0
T146	0	4	0	0
T149	0	10	0	0
T153	0	462	0	0
T154	0	9	0	0
T155	0	30	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212520222	85144	0	0
T20	8261	43	0	0
T21	757	0	0	0
T22	864	0	0	0
T23	1132	0	0	0
T24	3396	0	0	0
T25	889	0	0	0
T26	17660	0	0	0
T27	958	0	0	0
T28	1436	0	0	0
T133	0	66	0	0
T134	0	25	0	0
T135	2127	0	0	0
T137	0	26	0	0
T138	0	54	0	0
T139	0	35	0	0
T140	0	36	0	0
T146	0	2	0	0
T153	0	410	0	0
T156	0	9	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212520222	85233	0	0
T20	8261	57	0	0
T21	757	0	0	0
T22	864	0	0	0
T23	1132	0	0	0
T24	3396	0	0	0
T25	889	0	0	0
T26	17660	0	0	0
T27	958	0	0	0
T28	1436	0	0	0
T133	0	69	0	0
T134	0	23	0	0
T135	2127	0	0	0
T136	0	3	0	0
T137	0	52	0	0
T138	0	77	0	0
T139	0	25	0	0
T140	0	29	0	0
T153	0	457	0	0
T156	0	4	0	0