Unified Coverage Report :: Module :: edn

Module : edn

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	94.44		83.33	100.00			100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.67	99.02	92.32	96.84	93.42	98.62	99.77

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
edn_csr_assert	100.00						100.00
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_edn_core	92.07	99.92	89.58	71.29	93.42	99.29	98.91
u_edn_cov_if	25.00	50.00	0.00
u_reg	98.63	96.98	98.92	100.00		97.26	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Cond Coverage for Module : edn

	Total	Covered	Percent
Conditions	6	5	83.33
Logical	6	5	83.33
Non-Logical	0	0
Event	0	0

 LINE       99
 EXPRESSION (alert[0] || intg_err_alert[0])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T16,T17,T18

 LINE       99
 EXPRESSION (alert[1] || intg_err_alert[1])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T29,T30,T31
1	0	Covered	T4,T14,T7

---

Toggle Coverage for Module : edn

	Total	Covered	Percent
Totals	69	69	100.00
Total Bits	1168	1168	100.00
Total Bits 0->1	584	584	100.00
Total Bits 1->0	584	584	100.00

Ports	69	69	100.00
Port Bits	1168	1168	100.00
Port Bits 0->1	584	584	100.00
Port Bits 1->0	584	584	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T19,T20,T21	Yes	T19,T20,T21	INPUT
rst_ni	Yes	Yes	T20,T24,T26	Yes	T19,T20,T21	INPUT
tl_i.d_ready	Yes	Yes	T20,T23,T24	Yes	T19,T20,T21	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T19,T20,T21	Yes	T19,T20,T21	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T19,T20,T21	Yes	T19,T20,T21	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T19,T20,T25	Yes	T19,T20,T25	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T19,T20,T21	Yes	T19,T20,T21	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T19,T20,T21	Yes	T19,T20,T21	INPUT
tl_i.a_address[31:0]	Yes	Yes	T19,T20,T22	Yes	T19,T20,T22	INPUT
tl_i.a_source[7:0]	Yes	Yes	T19,T20,T21	Yes	T19,T20,T21	INPUT
tl_i.a_size[1:0]	Yes	Yes	T19,T20,T21	Yes	T19,T20,T21	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T19,T20,T21	Yes	T19,T20,T21	INPUT
tl_i.a_valid	Yes	Yes	T19,T20,T21	Yes	T19,T20,T21	INPUT
tl_o.a_ready	Yes	Yes	T19,T20,T21	Yes	T19,T20,T21	OUTPUT
tl_o.d_error	Yes	Yes	T20,T24,T26	Yes	T20,T24,T26	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T19,T20,T21	Yes	T19,T20,T21	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T19,T20,*T21	Yes	T19,T20,T21	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T19,T20,T21	Yes	T19,T20,T21	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T19,T20,T21	Yes	T19,T20,T21	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T19,*T20,*T21	Yes	T19,T20,T21	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T19,T20,T21	Yes	T19,T20,T21	OUTPUT
edn_i[0].edn_req	Yes	Yes	T1,T32,T10	Yes	T1,T32,T10	INPUT
edn_i[1].edn_req	Yes	Yes	T33,T34,T35	Yes	T33,T34,T35	INPUT
edn_i[2].edn_req	Yes	Yes	T33,T35,T36	Yes	T33,T35,T36	INPUT
edn_i[3].edn_req	Yes	Yes	T3,T4,T11	Yes	T3,T4,T11	INPUT
edn_i[4].edn_req	Yes	Yes	T2,T10,T37	Yes	T2,T10,T37	INPUT
edn_i[5].edn_req	Yes	Yes	T2,T16,T11	Yes	T2,T16,T11	INPUT
edn_i[6].edn_req	Yes	Yes	T2,T38,T11	Yes	T2,T38,T11	INPUT
edn_o[0].edn_bus[31:0]	Yes	Yes	T1,T32,T39	Yes	T1,T32,T39	OUTPUT
edn_o[0].edn_fips	Yes	Yes	T1,T40,T5	Yes	T1,T32,T40	OUTPUT
edn_o[0].edn_ack	Yes	Yes	T1,T32,T10	Yes	T1,T32,T10	OUTPUT
edn_o[1].edn_bus[31:0]	Yes	Yes	T33,T34,T35	Yes	T33,T34,T35	OUTPUT
edn_o[1].edn_fips	Yes	Yes	T41,T42,T43	Yes	T35,T36,T41	OUTPUT
edn_o[1].edn_ack	Yes	Yes	T33,T34,T35	Yes	T33,T34,T35	OUTPUT
edn_o[2].edn_bus[31:0]	Yes	Yes	T33,T35,T41	Yes	T33,T35,T36	OUTPUT
edn_o[2].edn_fips	Yes	Yes	T41,T12,T44	Yes	T33,T41,T12	OUTPUT
edn_o[2].edn_ack	Yes	Yes	T33,T35,T36	Yes	T33,T35,T36	OUTPUT
edn_o[3].edn_bus[31:0]	Yes	Yes	T3,T11,T33	Yes	T3,T11,T33	OUTPUT
edn_o[3].edn_fips	Yes	Yes	T3,T11,T33	Yes	T3,T11,T33	OUTPUT
edn_o[3].edn_ack	Yes	Yes	T3,T11,T33	Yes	T3,T11,T33	OUTPUT
edn_o[4].edn_bus[31:0]	Yes	Yes	T2,T10,T45	Yes	T2,T10,T45	OUTPUT
edn_o[4].edn_fips	Yes	Yes	T10,T45,T13	Yes	T2,T10,T45	OUTPUT
edn_o[4].edn_ack	Yes	Yes	T2,T10,T37	Yes	T2,T10,T37	OUTPUT
edn_o[5].edn_bus[31:0]	Yes	Yes	T2,T16,T11	Yes	T2,T16,T11	OUTPUT
edn_o[5].edn_fips	Yes	Yes	T2,T14,T33	Yes	T2,T16,T11	OUTPUT
edn_o[5].edn_ack	Yes	Yes	T2,T16,T11	Yes	T2,T16,T11	OUTPUT
edn_o[6].edn_bus[31:0]	Yes	Yes	T2,T38,T11	Yes	T2,T38,T11	OUTPUT
edn_o[6].edn_fips	Yes	Yes	T2,T38,T35	Yes	T2,T38,T11	OUTPUT
edn_o[6].edn_ack	Yes	Yes	T2,T38,T11	Yes	T2,T38,T11	OUTPUT
csrng_cmd_o.genbits_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_i.genbits_bus[127:0]	Yes	Yes	T1,T2,T10	Yes	T1,T2,T10	INPUT
csrng_cmd_i.genbits_fips	Yes	Yes	T1,T2,T3	Yes	T1,T2,T10	INPUT
csrng_cmd_i.genbits_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_rsp_sts	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_rsp_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_req_ready	Yes	Yes	T19,T20,T21	Yes	T19,T20,T21	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T19,T20,T21	Yes	T19,T20,T21	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T20,T23,T24	Yes	T20,T23,T24	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T19,T20,T21	Yes	T19,T20,T21	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T20,T23,T24	Yes	T20,T23,T24	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T19,T20,T21	Yes	T19,T20,T21	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T20,T23,T24	Yes	T20,T23,T24	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T19,T20,T21	Yes	T19,T20,T21	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T20,T23,T24	Yes	T20,T23,T24	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T19,T21,T22	Yes	T19,T21,T22	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T22,T25,T27	Yes	T22,T25,T27	OUTPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Module : edn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	43	43	100.00	43	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	43	43	100.00	43	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnownO_A	212032559	211921591	0	0
CsrngAppIfOut_A	212032559	211921591	0	0
FpvSecCmCntAlertCheck_A	212032559	67	0	0
FpvSecCmMainFsmCheck_A	212032559	30	0	0
FpvSecCmRegWeOnehotCheck_A	212032559	30	0	0
IntrEdnCmdReqDoneKnownO_A	212032559	211921591	0	0
TlAReadyKnownO_A	212032559	211921591	0	0
TlDValidKnownO_A	212032559	211921591	0	0
gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A	212032559	30	0	0
gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A	212032559	30	0	0
gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A	212032559	30	0	0
gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A	212032559	30	0	0
gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A	212032559	30	0	0
gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A	212032559	30	0	0
gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A	212032559	30	0	0
gen_edn_if_asserts[0].EdnDataStableDisable_A	212032559	443163	0	0
gen_edn_if_asserts[0].EdnDataStable_A	212032559	121082	0	345
gen_edn_if_asserts[0].EdnEndPointOut_A	212032559	211921591	0	0
gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A	212032559	99815	0	0
gen_edn_if_asserts[1].EdnDataStableDisable_A	212032559	443163	0	0
gen_edn_if_asserts[1].EdnDataStable_A	212032559	4400	0	108
gen_edn_if_asserts[1].EdnEndPointOut_A	212032559	211921591	0	0
gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A	212032559	99815	0	0
gen_edn_if_asserts[2].EdnDataStableDisable_A	212032559	443163	0	0
gen_edn_if_asserts[2].EdnDataStable_A	212032559	3749	0	106
gen_edn_if_asserts[2].EdnEndPointOut_A	212032559	211921591	0	0
gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A	212032559	99815	0	0
gen_edn_if_asserts[3].EdnDataStableDisable_A	212032559	443163	0	0
gen_edn_if_asserts[3].EdnDataStable_A	212032559	2582	0	94
gen_edn_if_asserts[3].EdnEndPointOut_A	212032559	211921591	0	0
gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A	212032559	99815	0	0
gen_edn_if_asserts[4].EdnDataStableDisable_A	212032559	443163	0	0
gen_edn_if_asserts[4].EdnDataStable_A	212032559	3227	0	73
gen_edn_if_asserts[4].EdnEndPointOut_A	212032559	211921591	0	0
gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A	212032559	99815	0	0
gen_edn_if_asserts[5].EdnDataStableDisable_A	212032559	443163	0	0
gen_edn_if_asserts[5].EdnDataStable_A	212032559	54859	0	85
gen_edn_if_asserts[5].EdnEndPointOut_A	212032559	211921591	0	0
gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A	212032559	99815	0	0
gen_edn_if_asserts[6].EdnDataStableDisable_A	212032559	443163	0	0
gen_edn_if_asserts[6].EdnDataStable_A	212032559	4817	0	77
gen_edn_if_asserts[6].EdnEndPointOut_A	212032559	211921591	0	0
gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A	212032559	99815	0	0

AlertTxKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212032559	211921591	0	0
T1	1907	1826	0	0
T2	4733	4646	0	0
T3	985	891	0	0
T4	1892	1738	0	0
T10	3651	3576	0	0
T32	1080	1015	0	0
T38	1282	1190	0	0
T39	1474	1378	0	0
T40	1150	1056	0	0
T46	1606	1517	0	0

CsrngAppIfOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212032559	211921591	0	0
T1	1907	1826	0	0
T2	4733	4646	0	0
T3	985	891	0	0
T4	1892	1738	0	0
T10	3651	3576	0	0
T32	1080	1015	0	0
T38	1282	1190	0	0
T39	1474	1378	0	0
T40	1150	1056	0	0
T46	1606	1517	0	0

FpvSecCmCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212032559	67	0	0
T7	1148	1	0	0
T14	2058	1	0	0
T15	0	1	0	0
T17	1724	0	0	0
T35	1920	0	0	0
T36	1917	0	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	108711	0	0	0
T55	18954	0	0	0
T56	991	0	0	0
T57	1334	0	0	0
T58	7364	0	0	0

FpvSecCmMainFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212032559	30	0	0
T29	16040	10	0	0
T30	0	10	0	0
T31	0	10	0	0
T59	1653	0	0	0
T60	1781	0	0	0
T61	289528	0	0	0
T62	1240	0	0	0
T63	1251	0	0	0
T64	1459	0	0	0
T65	2068	0	0	0
T66	1701	0	0	0
T67	1132	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212032559	30	0	0
T29	16040	10	0	0
T30	0	10	0	0
T31	0	10	0	0
T59	1653	0	0	0
T60	1781	0	0	0
T61	289528	0	0	0
T62	1240	0	0	0
T63	1251	0	0	0
T64	1459	0	0	0
T65	2068	0	0	0
T66	1701	0	0	0
T67	1132	0	0	0

IntrEdnCmdReqDoneKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212032559	211921591	0	0
T1	1907	1826	0	0
T2	4733	4646	0	0
T3	985	891	0	0
T4	1892	1738	0	0
T10	3651	3576	0	0
T32	1080	1015	0	0
T38	1282	1190	0	0
T39	1474	1378	0	0
T40	1150	1056	0	0
T46	1606	1517	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212032559	211921591	0	0
T1	1907	1826	0	0
T2	4733	4646	0	0
T3	985	891	0	0
T4	1892	1738	0	0
T10	3651	3576	0	0
T32	1080	1015	0	0
T38	1282	1190	0	0
T39	1474	1378	0	0
T40	1150	1056	0	0
T46	1606	1517	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212032559	211921591	0	0
T1	1907	1826	0	0
T2	4733	4646	0	0
T3	985	891	0	0
T4	1892	1738	0	0
T10	3651	3576	0	0
T32	1080	1015	0	0
T38	1282	1190	0	0
T39	1474	1378	0	0
T40	1150	1056	0	0
T46	1606	1517	0	0

gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212032559	30	0	0
T29	16040	10	0	0
T30	0	10	0	0
T31	0	10	0	0
T59	1653	0	0	0
T60	1781	0	0	0
T61	289528	0	0	0
T62	1240	0	0	0
T63	1251	0	0	0
T64	1459	0	0	0
T65	2068	0	0	0
T66	1701	0	0	0
T67	1132	0	0	0

gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212032559	30	0	0
T29	16040	10	0	0
T30	0	10	0	0
T31	0	10	0	0
T59	1653	0	0	0
T60	1781	0	0	0
T61	289528	0	0	0
T62	1240	0	0	0
T63	1251	0	0	0
T64	1459	0	0	0
T65	2068	0	0	0
T66	1701	0	0	0
T67	1132	0	0	0

gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212032559	30	0	0
T29	16040	10	0	0
T30	0	10	0	0
T31	0	10	0	0
T59	1653	0	0	0
T60	1781	0	0	0
T61	289528	0	0	0
T62	1240	0	0	0
T63	1251	0	0	0
T64	1459	0	0	0
T65	2068	0	0	0
T66	1701	0	0	0
T67	1132	0	0	0

gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212032559	30	0	0
T29	16040	10	0	0
T30	0	10	0	0
T31	0	10	0	0
T59	1653	0	0	0
T60	1781	0	0	0
T61	289528	0	0	0
T62	1240	0	0	0
T63	1251	0	0	0
T64	1459	0	0	0
T65	2068	0	0	0
T66	1701	0	0	0
T67	1132	0	0	0

gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212032559	30	0	0
T29	16040	10	0	0
T30	0	10	0	0
T31	0	10	0	0
T59	1653	0	0	0
T60	1781	0	0	0
T61	289528	0	0	0
T62	1240	0	0	0
T63	1251	0	0	0
T64	1459	0	0	0
T65	2068	0	0	0
T66	1701	0	0	0
T67	1132	0	0	0

gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212032559	30	0	0
T29	16040	10	0	0
T30	0	10	0	0
T31	0	10	0	0
T59	1653	0	0	0
T60	1781	0	0	0
T61	289528	0	0	0
T62	1240	0	0	0
T63	1251	0	0	0
T64	1459	0	0	0
T65	2068	0	0	0
T66	1701	0	0	0
T67	1132	0	0	0

gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212032559	30	0	0
T29	16040	10	0	0
T30	0	10	0	0
T31	0	10	0	0
T59	1653	0	0	0
T60	1781	0	0	0
T61	289528	0	0	0
T62	1240	0	0	0
T63	1251	0	0	0
T64	1459	0	0	0
T65	2068	0	0	0
T66	1701	0	0	0
T67	1132	0	0	0

gen_edn_if_asserts[0].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212032559	443163	0	0
T1	1907	87	0	0
T2	4733	181	0	0
T3	985	59	0	0
T4	1892	1090	0	0
T10	3651	75	0	0
T32	1080	19	0	0
T38	1282	23	0	0
T39	1474	14	0	0
T40	1150	19	0	0
T46	1606	1516	0	0

gen_edn_if_asserts[0].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212032559	121082	0	345
T1	1907	60	0	1
T2	4733	0	0	0
T3	985	0	0	0
T4	1892	0	0	0
T5	0	109	0	0
T6	0	129	0	0
T10	3651	3	0	1
T11	0	3	0	1
T32	1080	3	0	1
T38	1282	0	0	0
T39	1474	3	0	1
T40	1150	63	0	1
T45	0	3	0	1
T46	1606	0	0	0
T55	0	0	0	1
T68	0	19	0	1
T69	0	0	0	1

gen_edn_if_asserts[0].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212032559	211921591	0	0
T1	1907	1826	0	0
T2	4733	4646	0	0
T3	985	891	0	0
T4	1892	1738	0	0
T10	3651	3576	0	0
T32	1080	1015	0	0
T38	1282	1190	0	0
T39	1474	1378	0	0
T40	1150	1056	0	0
T46	1606	1517	0	0

gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212032559	99815	0	0
T4	1892	1180	0	0
T5	459436	0	0	0
T6	145953	0	0	0
T7	0	325	0	0
T8	0	365	0	0
T11	1767	0	0	0
T14	0	1109	0	0
T16	1849	0	0	0
T37	790	0	0	0
T38	1282	0	0	0
T40	1150	0	0	0
T45	2057	0	0	0
T68	13568	0	0	0
T70	0	217	0	0
T71	0	592	0	0
T72	0	24	0	0
T73	0	362	0	0
T74	0	641	0	0
T75	0	419	0	0

gen_edn_if_asserts[1].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212032559	443163	0	0
T1	1907	87	0	0
T2	4733	181	0	0
T3	985	59	0	0
T4	1892	1090	0	0
T10	3651	75	0	0
T32	1080	19	0	0
T38	1282	23	0	0
T39	1474	14	0	0
T40	1150	19	0	0
T46	1606	1516	0	0

gen_edn_if_asserts[1].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212032559	4400	0	108
T7	1148	0	0	0
T12	0	3	0	1
T33	1335	3	0	1
T34	1530	3	0	1
T35	0	3	0	1
T36	0	3	0	1
T41	0	387	0	1
T42	0	32	0	1
T43	0	20	0	1
T76	0	3	0	1
T77	0	4	0	1
T78	4317	0	0	0
T79	1232	0	0	0
T80	1005	0	0	0
T81	1267	0	0	0
T82	649735	0	0	0
T83	9428	0	0	0
T84	1236	0	0	0

gen_edn_if_asserts[1].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212032559	211921591	0	0
T1	1907	1826	0	0
T2	4733	4646	0	0
T3	985	891	0	0
T4	1892	1738	0	0
T10	3651	3576	0	0
T32	1080	1015	0	0
T38	1282	1190	0	0
T39	1474	1378	0	0
T40	1150	1056	0	0
T46	1606	1517	0	0

gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212032559	99815	0	0
T4	1892	1180	0	0
T5	459436	0	0	0
T6	145953	0	0	0
T7	0	325	0	0
T8	0	365	0	0
T11	1767	0	0	0
T14	0	1109	0	0
T16	1849	0	0	0
T37	790	0	0	0
T38	1282	0	0	0
T40	1150	0	0	0
T45	2057	0	0	0
T68	13568	0	0	0
T70	0	217	0	0
T71	0	592	0	0
T72	0	24	0	0
T73	0	362	0	0
T74	0	641	0	0
T75	0	419	0	0

gen_edn_if_asserts[2].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212032559	443163	0	0
T1	1907	87	0	0
T2	4733	181	0	0
T3	985	59	0	0
T4	1892	1090	0	0
T10	3651	75	0	0
T32	1080	19	0	0
T38	1282	23	0	0
T39	1474	14	0	0
T40	1150	19	0	0
T46	1606	1516	0	0

gen_edn_if_asserts[2].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212032559	3749	0	106
T7	1148	0	0	0
T12	0	45	0	1
T13	0	3	0	1
T33	1335	3	0	1
T34	1530	0	0	0
T35	0	3	0	1
T36	0	3	0	1
T41	0	40	0	1
T42	0	3	0	1
T44	0	52	0	1
T76	0	3	0	1
T78	4317	0	0	0
T79	1232	0	0	0
T80	1005	0	0	0
T81	1267	0	0	0
T82	649735	0	0	0
T83	9428	0	0	0
T84	1236	0	0	0
T85	0	7	0	1

gen_edn_if_asserts[2].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212032559	211921591	0	0
T1	1907	1826	0	0
T2	4733	4646	0	0
T3	985	891	0	0
T4	1892	1738	0	0
T10	3651	3576	0	0
T32	1080	1015	0	0
T38	1282	1190	0	0
T39	1474	1378	0	0
T40	1150	1056	0	0
T46	1606	1517	0	0

gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212032559	99815	0	0
T4	1892	1180	0	0
T5	459436	0	0	0
T6	145953	0	0	0
T7	0	325	0	0
T8	0	365	0	0
T11	1767	0	0	0
T14	0	1109	0	0
T16	1849	0	0	0
T37	790	0	0	0
T38	1282	0	0	0
T40	1150	0	0	0
T45	2057	0	0	0
T68	13568	0	0	0
T70	0	217	0	0
T71	0	592	0	0
T72	0	24	0	0
T73	0	362	0	0
T74	0	641	0	0
T75	0	419	0	0

gen_edn_if_asserts[3].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212032559	443163	0	0
T1	1907	87	0	0
T2	4733	181	0	0
T3	985	59	0	0
T4	1892	1090	0	0
T10	3651	75	0	0
T32	1080	19	0	0
T38	1282	23	0	0
T39	1474	14	0	0
T40	1150	19	0	0
T46	1606	1516	0	0

gen_edn_if_asserts[3].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212032559	2582	0	94
T3	985	3	0	0
T4	1892	0	0	0
T5	459436	0	0	0
T10	3651	0	0	0
T11	0	15	0	1
T13	0	0	0	1
T18	0	4	0	1
T32	1080	0	0	0
T33	0	18	0	1
T35	0	3	0	1
T36	0	11	0	1
T37	790	0	0	0
T38	1282	0	0	0
T39	1474	0	0	0
T40	1150	0	0	0
T41	0	3	0	1
T42	0	25	0	1
T44	0	3	0	1
T46	1606	0	0	0
T85	0	0	0	1
T86	0	3	0	0

gen_edn_if_asserts[3].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212032559	211921591	0	0
T1	1907	1826	0	0
T2	4733	4646	0	0
T3	985	891	0	0
T4	1892	1738	0	0
T10	3651	3576	0	0
T32	1080	1015	0	0
T38	1282	1190	0	0
T39	1474	1378	0	0
T40	1150	1056	0	0
T46	1606	1517	0	0

gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212032559	99815	0	0
T4	1892	1180	0	0
T5	459436	0	0	0
T6	145953	0	0	0
T7	0	325	0	0
T8	0	365	0	0
T11	1767	0	0	0
T14	0	1109	0	0
T16	1849	0	0	0
T37	790	0	0	0
T38	1282	0	0	0
T40	1150	0	0	0
T45	2057	0	0	0
T68	13568	0	0	0
T70	0	217	0	0
T71	0	592	0	0
T72	0	24	0	0
T73	0	362	0	0
T74	0	641	0	0
T75	0	419	0	0

gen_edn_if_asserts[4].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212032559	443163	0	0
T1	1907	87	0	0
T2	4733	181	0	0
T3	985	59	0	0
T4	1892	1090	0	0
T10	3651	75	0	0
T32	1080	19	0	0
T38	1282	23	0	0
T39	1474	14	0	0
T40	1150	19	0	0
T46	1606	1516	0	0

gen_edn_if_asserts[4].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212032559	3227	0	73
T2	4733	3	0	1
T3	985	0	0	0
T4	1892	0	0	0
T10	3651	547	0	1
T12	0	3	0	1
T32	1080	0	0	0
T33	0	3	0	1
T36	0	13	0	1
T37	790	3	0	1
T38	1282	0	0	0
T39	1474	0	0	0
T40	1150	0	0	0
T42	0	10	0	1
T45	0	38	0	1
T46	1606	0	0	0
T57	0	27	0	1
T87	0	3	0	1

gen_edn_if_asserts[4].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212032559	211921591	0	0
T1	1907	1826	0	0
T2	4733	4646	0	0
T3	985	891	0	0
T4	1892	1738	0	0
T10	3651	3576	0	0
T32	1080	1015	0	0
T38	1282	1190	0	0
T39	1474	1378	0	0
T40	1150	1056	0	0
T46	1606	1517	0	0

gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212032559	99815	0	0
T4	1892	1180	0	0
T5	459436	0	0	0
T6	145953	0	0	0
T7	0	325	0	0
T8	0	365	0	0
T11	1767	0	0	0
T14	0	1109	0	0
T16	1849	0	0	0
T37	790	0	0	0
T38	1282	0	0	0
T40	1150	0	0	0
T45	2057	0	0	0
T68	13568	0	0	0
T70	0	217	0	0
T71	0	592	0	0
T72	0	24	0	0
T73	0	362	0	0
T74	0	641	0	0
T75	0	419	0	0

gen_edn_if_asserts[5].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212032559	443163	0	0
T1	1907	87	0	0
T2	4733	181	0	0
T3	985	59	0	0
T4	1892	1090	0	0
T10	3651	75	0	0
T32	1080	19	0	0
T38	1282	23	0	0
T39	1474	14	0	0
T40	1150	19	0	0
T46	1606	1516	0	0

gen_edn_if_asserts[5].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212032559	54859	0	85
T2	4733	755	0	1
T3	985	0	0	0
T4	1892	0	0	0
T10	3651	0	0	0
T11	0	3	0	1
T12	0	48	0	1
T16	0	4	0	1
T32	1080	0	0	0
T33	0	19	0	1
T35	0	3	0	1
T36	0	3	0	1
T37	790	0	0	0
T38	1282	0	0	0
T39	1474	0	0	0
T40	1150	0	0	0
T41	0	62	0	1
T42	0	4	0	1
T46	1606	0	0	0
T85	0	61	0	1

gen_edn_if_asserts[5].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212032559	211921591	0	0
T1	1907	1826	0	0
T2	4733	4646	0	0
T3	985	891	0	0
T4	1892	1738	0	0
T10	3651	3576	0	0
T32	1080	1015	0	0
T38	1282	1190	0	0
T39	1474	1378	0	0
T40	1150	1056	0	0
T46	1606	1517	0	0

gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212032559	99815	0	0
T4	1892	1180	0	0
T5	459436	0	0	0
T6	145953	0	0	0
T7	0	325	0	0
T8	0	365	0	0
T11	1767	0	0	0
T14	0	1109	0	0
T16	1849	0	0	0
T37	790	0	0	0
T38	1282	0	0	0
T40	1150	0	0	0
T45	2057	0	0	0
T68	13568	0	0	0
T70	0	217	0	0
T71	0	592	0	0
T72	0	24	0	0
T73	0	362	0	0
T74	0	641	0	0
T75	0	419	0	0

gen_edn_if_asserts[6].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212032559	443163	0	0
T1	1907	87	0	0
T2	4733	181	0	0
T3	985	59	0	0
T4	1892	1090	0	0
T10	3651	75	0	0
T32	1080	19	0	0
T38	1282	23	0	0
T39	1474	14	0	0
T40	1150	19	0	0
T46	1606	1516	0	0

gen_edn_if_asserts[6].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212032559	4817	0	77
T2	4733	39	0	1
T3	985	0	0	0
T4	1892	0	0	0
T10	3651	0	0	0
T11	0	20	0	1
T13	0	10	0	1
T32	1080	0	0	0
T33	0	3	0	1
T35	0	40	0	1
T37	790	0	0	0
T38	1282	29	0	1
T39	1474	0	0	0
T40	1150	0	0	0
T42	0	19	0	1
T44	0	59	0	1
T46	1606	0	0	0
T69	0	3	0	1
T85	0	14	0	1

gen_edn_if_asserts[6].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212032559	211921591	0	0
T1	1907	1826	0	0
T2	4733	4646	0	0
T3	985	891	0	0
T4	1892	1738	0	0
T10	3651	3576	0	0
T32	1080	1015	0	0
T38	1282	1190	0	0
T39	1474	1378	0	0
T40	1150	1056	0	0
T46	1606	1517	0	0

gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212032559	99815	0	0
T4	1892	1180	0	0
T5	459436	0	0	0
T6	145953	0	0	0
T7	0	325	0	0
T8	0	365	0	0
T11	1767	0	0	0
T14	0	1109	0	0
T16	1849	0	0	0
T37	790	0	0	0
T38	1282	0	0	0
T40	1150	0	0	0
T45	2057	0	0	0
T68	13568	0	0	0
T70	0	217	0	0
T71	0	592	0	0
T72	0	24	0	0
T73	0	362	0	0
T74	0	641	0	0
T75	0	419	0	0