Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44		83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	208389306	9315121	0	0
boot_gen_cmd_rd_A	208389306	68320	0	0
boot_ins_cmd_rd_A	208389306	77191	0	0
ctrl_rd_A	208389306	67854	0	0
err_code_test_rd_A	208389306	67566	0	0
intr_enable_rd_A	208389306	74179	0	0
max_num_reqs_between_reseeds_rd_A	208389306	77128	0	0
regwen_rd_A	208389306	77837	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	208389306	9315121	0	0
T20	8379	9	0	0
T21	1143	0	0	0
T22	2887	86	0	0
T23	1687	0	0	0
T24	5607	518	0	0
T25	926	0	0	0
T26	9207	895	0	0
T27	978	0	0	0
T28	1950	0	0	0
T29	3310	0	0	0
T33	0	37	0	0
T47	0	257670	0	0
T82	0	354477	0	0
T143	0	6	0	0
T144	0	45	0	0
T145	0	56	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	208389306	68320	0	0
T29	3310	77	0	0
T33	1142	0	0	0
T61	1180	0	0	0
T62	1284	0	0	0
T82	0	10247	0	0
T143	5024	0	0	0
T144	1171	0	0	0
T145	1403	0	0	0
T146	2151	32	0	0
T147	0	602	0	0
T148	0	4001	0	0
T149	0	11370	0	0
T150	0	5713	0	0
T151	0	3063	0	0
T152	0	1919	0	0
T153	0	3463	0	0
T154	768	0	0	0
T155	1010	0	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	208389306	77191	0	0
T28	1950	16	0	0
T29	3310	94	0	0
T33	1142	0	0	0
T61	1180	0	0	0
T62	1284	0	0	0
T82	0	11601	0	0
T144	1171	0	0	0
T145	1403	0	0	0
T146	2151	12	0	0
T147	0	777	0	0
T148	0	4071	0	0
T149	0	13121	0	0
T150	0	6053	0	0
T151	0	3377	0	0
T152	0	1914	0	0
T154	768	0	0	0
T155	1010	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	208389306	67854	0	0
T29	3310	83	0	0
T33	1142	0	0	0
T41	0	3	0	0
T46	0	5	0	0
T61	1180	0	0	0
T62	1284	0	0	0
T82	0	10556	0	0
T105	0	3	0	0
T143	5024	0	0	0
T144	1171	0	0	0
T145	1403	0	0	0
T146	2151	44	0	0
T147	0	599	0	0
T148	0	3529	0	0
T154	768	0	0	0
T155	1010	0	0	0
T156	0	8	0	0
T157	0	7	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	208389306	67566	0	0
T28	1950	23	0	0
T29	3310	92	0	0
T33	1142	0	0	0
T61	1180	0	0	0
T62	1284	0	0	0
T82	0	9866	0	0
T144	1171	0	0	0
T145	1403	0	0	0
T146	2151	18	0	0
T147	0	595	0	0
T148	0	3643	0	0
T149	0	11096	0	0
T150	0	5246	0	0
T151	0	2769	0	0
T152	0	1956	0	0
T154	768	0	0	0
T155	1010	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	208389306	74179	0	0
T20	8379	106	0	0
T21	1143	0	0	0
T22	2887	0	0	0
T23	1687	0	0	0
T24	5607	0	0	0
T25	926	13	0	0
T26	9207	0	0	0
T27	978	0	0	0
T28	1950	14	0	0
T29	3310	75	0	0
T46	0	20	0	0
T62	0	16	0	0
T82	0	11230	0	0
T146	0	13	0	0
T147	0	781	0	0
T156	0	55	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	208389306	77128	0	0
T20	8379	81	0	0
T21	1143	0	0	0
T22	2887	0	0	0
T23	1687	0	0	0
T24	5607	0	0	0
T25	926	0	0	0
T26	9207	0	0	0
T27	978	0	0	0
T28	1950	11	0	0
T29	3310	93	0	0
T82	0	11640	0	0
T146	0	21	0	0
T147	0	756	0	0
T148	0	3997	0	0
T149	0	13019	0	0
T150	0	6090	0	0
T151	0	3360	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	208389306	77837	0	0
T20	8379	95	0	0
T21	1143	0	0	0
T22	2887	0	0	0
T23	1687	0	0	0
T24	5607	0	0	0
T25	926	0	0	0
T26	9207	0	0	0
T27	978	0	0	0
T28	1950	23	0	0
T29	3310	65	0	0
T82	0	11640	0	0
T146	0	35	0	0
T147	0	780	0	0
T148	0	4229	0	0
T149	0	12750	0	0
T150	0	6263	0	0
T151	0	3422	0	0