Unified Coverage Report :: Module :: edn

Module : edn

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	94.44		83.33	100.00			100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.61	99.02	92.05	96.79	93.42	98.62	99.77

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
edn_csr_assert	100.00						100.00
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_edn_core	91.92	99.92	89.18	70.79	93.42	99.29	98.91
u_edn_cov_if	25.00	50.00	0.00
u_reg	98.63	96.98	98.92	100.00		97.26	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Cond Coverage for Module : edn

	Total	Covered	Percent
Conditions	6	5	83.33
Logical	6	5	83.33
Non-Logical	0	0
Event	0	0

 LINE       99
 EXPRESSION (alert[0] || intg_err_alert[0])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T17,T18,T19

 LINE       99
 EXPRESSION (alert[1] || intg_err_alert[1])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T30,T31,T32
1	0	Covered	T4,T5,T6

---

Toggle Coverage for Module : edn

	Total	Covered	Percent
Totals	69	69	100.00
Total Bits	1168	1168	100.00
Total Bits 0->1	584	584	100.00
Total Bits 1->0	584	584	100.00

Ports	69	69	100.00
Port Bits	1168	1168	100.00
Port Bits 0->1	584	584	100.00
Port Bits 1->0	584	584	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
rst_ni	Yes	Yes	T20,T22,T33	Yes	T20,T21,T22	INPUT
tl_i.d_ready	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T22,T24,T26	Yes	T22,T24,T26	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
tl_i.a_address[31:0]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
tl_i.a_source[7:0]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
tl_i.a_size[1:0]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
tl_i.a_valid	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
tl_o.a_ready	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
tl_o.d_error	Yes	Yes	T20,T22,T24	Yes	T20,T22,T24	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	T20,*T21,T22	Yes	T20,T21,T22	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T20,*T22,*T23	Yes	T20,T21,T22	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
edn_i[0].edn_req	Yes	Yes	T7,T34,T35	Yes	T7,T34,T35	INPUT
edn_i[1].edn_req	Yes	Yes	T1,T6,T36	Yes	T1,T6,T36	INPUT
edn_i[2].edn_req	Yes	Yes	T37,T38,T39	Yes	T37,T38,T39	INPUT
edn_i[3].edn_req	Yes	Yes	T5,T40,T41	Yes	T5,T40,T41	INPUT
edn_i[4].edn_req	Yes	Yes	T42,T15,T43	Yes	T42,T15,T43	INPUT
edn_i[5].edn_req	Yes	Yes	T2,T42,T44	Yes	T2,T42,T44	INPUT
edn_i[6].edn_req	Yes	Yes	T4,T11,T44	Yes	T4,T11,T44	INPUT
edn_o[0].edn_bus[31:0]	Yes	Yes	T34,T45,T46	Yes	T7,T34,T35	OUTPUT
edn_o[0].edn_fips	Yes	Yes	T45,T46,T47	Yes	T35,T45,T46	OUTPUT
edn_o[0].edn_ack	Yes	Yes	T7,T34,T35	Yes	T7,T34,T35	OUTPUT
edn_o[1].edn_bus[31:0]	Yes	Yes	T1,T6,T36	Yes	T1,T6,T36	OUTPUT
edn_o[1].edn_fips	Yes	Yes	T1,T39,T48	Yes	T1,T36,T39	OUTPUT
edn_o[1].edn_ack	Yes	Yes	T1,T6,T36	Yes	T1,T6,T36	OUTPUT
edn_o[2].edn_bus[31:0]	Yes	Yes	T38,T39,T48	Yes	T38,T39,T48	OUTPUT
edn_o[2].edn_fips	Yes	Yes	T39,T48,T49	Yes	T38,T39,T48	OUTPUT
edn_o[2].edn_ack	Yes	Yes	T38,T39,T48	Yes	T38,T39,T48	OUTPUT
edn_o[3].edn_bus[31:0]	Yes	Yes	T5,T50,T51	Yes	T5,T40,T41	OUTPUT
edn_o[3].edn_fips	Yes	Yes	T52,T53,T54	Yes	T51,T52,T53	OUTPUT
edn_o[3].edn_ack	Yes	Yes	T5,T40,T41	Yes	T5,T40,T41	OUTPUT
edn_o[4].edn_bus[31:0]	Yes	Yes	T42,T39,T55	Yes	T42,T39,T55	OUTPUT
edn_o[4].edn_fips	Yes	Yes	T39,T56,T57	Yes	T39,T55,T56	OUTPUT
edn_o[4].edn_ack	Yes	Yes	T42,T39,T55	Yes	T42,T39,T55	OUTPUT
edn_o[5].edn_bus[31:0]	Yes	Yes	T2,T42,T44	Yes	T2,T42,T44	OUTPUT
edn_o[5].edn_fips	Yes	Yes	T42,T44,T58	Yes	T2,T42,T44	OUTPUT
edn_o[5].edn_ack	Yes	Yes	T2,T42,T44	Yes	T2,T42,T44	OUTPUT
edn_o[6].edn_bus[31:0]	Yes	Yes	T11,T44,T59	Yes	T11,T44,T59	OUTPUT
edn_o[6].edn_fips	Yes	Yes	T44,T53,T54	Yes	T44,T59,T53	OUTPUT
edn_o[6].edn_ack	Yes	Yes	T11,T44,T59	Yes	T11,T44,T59	OUTPUT
csrng_cmd_o.genbits_ready	Yes	Yes	T1,T2,T7	Yes	T1,T2,T7	OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	Yes	Yes	T1,T2,T7	Yes	T1,T2,T7	OUTPUT
csrng_cmd_o.csrng_req_valid	Yes	Yes	T1,T2,T7	Yes	T1,T2,T7	OUTPUT
csrng_cmd_i.genbits_bus[127:0]	Yes	Yes	T2,T11,T47	Yes	T1,T47,T60	INPUT
csrng_cmd_i.genbits_fips	Yes	Yes	T1,T42,T45	Yes	T42,T45,T11	INPUT
csrng_cmd_i.genbits_valid	Yes	Yes	T1,T2,T7	Yes	T1,T2,T7	INPUT
csrng_cmd_i.csrng_rsp_sts	Yes	Yes	T1,T2,T7	Yes	T1,T2,T7	INPUT
csrng_cmd_i.csrng_rsp_ack	Yes	Yes	T1,T2,T7	Yes	T1,T2,T7	INPUT
csrng_cmd_i.csrng_req_ready	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T20,T22,T23	Yes	T20,T22,T23	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T20,T22,T23	Yes	T20,T22,T23	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T27,T61,T62	Yes	T27,T61,T62	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T25,T27,T61	Yes	T25,T27,T61	OUTPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Module : edn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	43	43	100.00	43	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	43	43	100.00	43	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnownO_A	207952174	207827874	0	0
CsrngAppIfOut_A	207952174	207827874	0	0
FpvSecCmCntAlertCheck_A	207952174	98	0	0
FpvSecCmMainFsmCheck_A	207952174	60	0	0
FpvSecCmRegWeOnehotCheck_A	207952174	60	0	0
IntrEdnCmdReqDoneKnownO_A	207952174	207827874	0	0
TlAReadyKnownO_A	207952174	207827874	0	0
TlDValidKnownO_A	207952174	207827874	0	0
gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A	207952174	60	0	0
gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A	207952174	60	0	0
gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A	207952174	60	0	0
gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A	207952174	60	0	0
gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A	207952174	60	0	0
gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A	207952174	60	0	0
gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A	207952174	60	0	0
gen_edn_if_asserts[0].EdnDataStableDisable_A	207952174	427066	0	0
gen_edn_if_asserts[0].EdnDataStable_A	207952174	113914	0	304
gen_edn_if_asserts[0].EdnEndPointOut_A	207952174	207827874	0	0
gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A	207952174	114819	0	0
gen_edn_if_asserts[1].EdnDataStableDisable_A	207952174	427066	0	0
gen_edn_if_asserts[1].EdnDataStable_A	207952174	4478	0	110
gen_edn_if_asserts[1].EdnEndPointOut_A	207952174	207827874	0	0
gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A	207952174	114819	0	0
gen_edn_if_asserts[2].EdnDataStableDisable_A	207952174	427066	0	0
gen_edn_if_asserts[2].EdnDataStable_A	207952174	55372	0	86
gen_edn_if_asserts[2].EdnEndPointOut_A	207952174	207827874	0	0
gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A	207952174	114819	0	0
gen_edn_if_asserts[3].EdnDataStableDisable_A	207952174	427066	0	0
gen_edn_if_asserts[3].EdnDataStable_A	207952174	2679	0	71
gen_edn_if_asserts[3].EdnEndPointOut_A	207952174	207827874	0	0
gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A	207952174	114819	0	0
gen_edn_if_asserts[4].EdnDataStableDisable_A	207952174	427066	0	0
gen_edn_if_asserts[4].EdnDataStable_A	207952174	4017	0	64
gen_edn_if_asserts[4].EdnEndPointOut_A	207952174	207827874	0	0
gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A	207952174	114819	0	0
gen_edn_if_asserts[5].EdnDataStableDisable_A	207952174	427066	0	0
gen_edn_if_asserts[5].EdnDataStable_A	207952174	3423	0	65
gen_edn_if_asserts[5].EdnEndPointOut_A	207952174	207827874	0	0
gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A	207952174	114819	0	0
gen_edn_if_asserts[6].EdnDataStableDisable_A	207952174	427066	0	0
gen_edn_if_asserts[6].EdnDataStable_A	207952174	1576	0	55
gen_edn_if_asserts[6].EdnEndPointOut_A	207952174	207827874	0	0
gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A	207952174	114819	0	0

AlertTxKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207952174	207827874	0	0
T1	1506	1439	0	0
T2	2725	2651	0	0
T3	1285	1232	0	0
T4	1539	1342	0	0
T5	593	471	0	0
T7	1065	980	0	0
T34	1109	1056	0	0
T35	1286	1236	0	0
T42	1689	1611	0	0
T63	1318	1232	0	0

CsrngAppIfOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207952174	207827874	0	0
T1	1506	1439	0	0
T2	2725	2651	0	0
T3	1285	1232	0	0
T4	1539	1342	0	0
T5	593	471	0	0
T7	1065	980	0	0
T34	1109	1056	0	0
T35	1286	1236	0	0
T42	1689	1611	0	0
T63	1318	1232	0	0

FpvSecCmCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207952174	98	0	0
T5	593	1	0	0
T6	1905	0	0	0
T15	0	1	0	0
T16	0	1	0	0
T17	1451	0	0	0
T30	0	10	0	0
T35	1286	0	0	0
T36	1766	0	0	0
T42	1689	0	0	0
T45	8070	0	0	0
T63	1318	0	0	0
T64	0	1	0	0
T65	0	1	0	0
T66	0	1	0	0
T67	0	1	0	0
T68	0	1	0	0
T69	0	1	0	0
T70	1776	0	0	0
T71	4049	0	0	0

FpvSecCmMainFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207952174	60	0	0
T30	16507	10	0	0
T31	0	10	0	0
T32	0	20	0	0
T64	2874	0	0	0
T72	0	10	0	0
T73	0	10	0	0
T74	1016	0	0	0
T75	1124	0	0	0
T76	847	0	0	0
T77	536679	0	0	0
T78	8411	0	0	0
T79	1401	0	0	0
T80	1137	0	0	0
T81	12848	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207952174	60	0	0
T30	16507	10	0	0
T31	0	10	0	0
T32	0	20	0	0
T64	2874	0	0	0
T72	0	10	0	0
T73	0	10	0	0
T74	1016	0	0	0
T75	1124	0	0	0
T76	847	0	0	0
T77	536679	0	0	0
T78	8411	0	0	0
T79	1401	0	0	0
T80	1137	0	0	0
T81	12848	0	0	0

IntrEdnCmdReqDoneKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207952174	207827874	0	0
T1	1506	1439	0	0
T2	2725	2651	0	0
T3	1285	1232	0	0
T4	1539	1342	0	0
T5	593	471	0	0
T7	1065	980	0	0
T34	1109	1056	0	0
T35	1286	1236	0	0
T42	1689	1611	0	0
T63	1318	1232	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207952174	207827874	0	0
T1	1506	1439	0	0
T2	2725	2651	0	0
T3	1285	1232	0	0
T4	1539	1342	0	0
T5	593	471	0	0
T7	1065	980	0	0
T34	1109	1056	0	0
T35	1286	1236	0	0
T42	1689	1611	0	0
T63	1318	1232	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207952174	207827874	0	0
T1	1506	1439	0	0
T2	2725	2651	0	0
T3	1285	1232	0	0
T4	1539	1342	0	0
T5	593	471	0	0
T7	1065	980	0	0
T34	1109	1056	0	0
T35	1286	1236	0	0
T42	1689	1611	0	0
T63	1318	1232	0	0

gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207952174	60	0	0
T30	16507	10	0	0
T31	0	10	0	0
T32	0	20	0	0
T64	2874	0	0	0
T72	0	10	0	0
T73	0	10	0	0
T74	1016	0	0	0
T75	1124	0	0	0
T76	847	0	0	0
T77	536679	0	0	0
T78	8411	0	0	0
T79	1401	0	0	0
T80	1137	0	0	0
T81	12848	0	0	0

gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207952174	60	0	0
T30	16507	10	0	0
T31	0	10	0	0
T32	0	20	0	0
T64	2874	0	0	0
T72	0	10	0	0
T73	0	10	0	0
T74	1016	0	0	0
T75	1124	0	0	0
T76	847	0	0	0
T77	536679	0	0	0
T78	8411	0	0	0
T79	1401	0	0	0
T80	1137	0	0	0
T81	12848	0	0	0

gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207952174	60	0	0
T30	16507	10	0	0
T31	0	10	0	0
T32	0	20	0	0
T64	2874	0	0	0
T72	0	10	0	0
T73	0	10	0	0
T74	1016	0	0	0
T75	1124	0	0	0
T76	847	0	0	0
T77	536679	0	0	0
T78	8411	0	0	0
T79	1401	0	0	0
T80	1137	0	0	0
T81	12848	0	0	0

gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207952174	60	0	0
T30	16507	10	0	0
T31	0	10	0	0
T32	0	20	0	0
T64	2874	0	0	0
T72	0	10	0	0
T73	0	10	0	0
T74	1016	0	0	0
T75	1124	0	0	0
T76	847	0	0	0
T77	536679	0	0	0
T78	8411	0	0	0
T79	1401	0	0	0
T80	1137	0	0	0
T81	12848	0	0	0

gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207952174	60	0	0
T30	16507	10	0	0
T31	0	10	0	0
T32	0	20	0	0
T64	2874	0	0	0
T72	0	10	0	0
T73	0	10	0	0
T74	1016	0	0	0
T75	1124	0	0	0
T76	847	0	0	0
T77	536679	0	0	0
T78	8411	0	0	0
T79	1401	0	0	0
T80	1137	0	0	0
T81	12848	0	0	0

gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207952174	60	0	0
T30	16507	10	0	0
T31	0	10	0	0
T32	0	20	0	0
T64	2874	0	0	0
T72	0	10	0	0
T73	0	10	0	0
T74	1016	0	0	0
T75	1124	0	0	0
T76	847	0	0	0
T77	536679	0	0	0
T78	8411	0	0	0
T79	1401	0	0	0
T80	1137	0	0	0
T81	12848	0	0	0

gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207952174	60	0	0
T30	16507	10	0	0
T31	0	10	0	0
T32	0	20	0	0
T64	2874	0	0	0
T72	0	10	0	0
T73	0	10	0	0
T74	1016	0	0	0
T75	1124	0	0	0
T76	847	0	0	0
T77	536679	0	0	0
T78	8411	0	0	0
T79	1401	0	0	0
T80	1137	0	0	0
T81	12848	0	0	0

gen_edn_if_asserts[0].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207952174	427066	0	0
T1	1506	62	0	0
T2	2725	1589	0	0
T3	1285	1231	0	0
T4	1539	150	0	0
T5	593	197	0	0
T7	1065	44	0	0
T34	1109	22	0	0
T35	1286	16	0	0
T42	1689	17	0	0
T63	1318	1231	0	0

gen_edn_if_asserts[0].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207952174	113914	0	304
T4	1539	0	0	0
T5	593	0	0	0
T6	1905	0	0	0
T7	1065	3	0	1
T18	0	4	0	1
T19	0	0	0	1
T34	1109	3	0	1
T35	1286	3	0	1
T42	1689	0	0	0
T44	0	0	0	1
T45	8070	13	0	1
T46	0	6	0	1
T47	0	140	0	0
T60	0	52	0	1
T63	1318	0	0	0
T70	1776	0	0	0
T82	0	167	0	0
T83	0	3	0	1

gen_edn_if_asserts[0].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207952174	207827874	0	0
T1	1506	1439	0	0
T2	2725	2651	0	0
T3	1285	1232	0	0
T4	1539	1342	0	0
T5	593	471	0	0
T7	1065	980	0	0
T34	1109	1056	0	0
T35	1286	1236	0	0
T42	1689	1611	0	0
T63	1318	1232	0	0

gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207952174	114819	0	0
T4	1539	208	0	0
T5	593	280	0	0
T6	1905	1036	0	0
T15	0	594	0	0
T35	1286	0	0	0
T36	1766	0	0	0
T37	0	692	0	0
T42	1689	0	0	0
T43	0	1082	0	0
T45	8070	0	0	0
T58	0	7	0	0
T63	1318	0	0	0
T70	1776	0	0	0
T71	4049	0	0	0
T84	0	1137	0	0
T85	0	660	0	0
T86	0	410	0	0

gen_edn_if_asserts[1].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207952174	427066	0	0
T1	1506	62	0	0
T2	2725	1589	0	0
T3	1285	1231	0	0
T4	1539	150	0	0
T5	593	197	0	0
T7	1065	44	0	0
T34	1109	22	0	0
T35	1286	16	0	0
T42	1689	17	0	0
T63	1318	1231	0	0

gen_edn_if_asserts[1].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207952174	4478	0	110
T1	1506	15	0	1
T2	2725	0	0	0
T3	1285	0	0	0
T4	1539	0	0	0
T5	593	0	0	0
T7	1065	0	0	0
T17	0	4	0	1
T34	1109	0	0	0
T35	1286	0	0	0
T36	0	3	0	1
T39	0	57	0	1
T41	0	3	0	0
T42	1689	0	0	0
T48	0	54	0	1
T54	0	3	0	1
T63	1318	0	0	0
T74	0	0	0	1
T87	0	27	0	1
T88	0	3	0	1
T89	0	3	0	1

gen_edn_if_asserts[1].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207952174	207827874	0	0
T1	1506	1439	0	0
T2	2725	2651	0	0
T3	1285	1232	0	0
T4	1539	1342	0	0
T5	593	471	0	0
T7	1065	980	0	0
T34	1109	1056	0	0
T35	1286	1236	0	0
T42	1689	1611	0	0
T63	1318	1232	0	0

gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207952174	114819	0	0
T4	1539	208	0	0
T5	593	280	0	0
T6	1905	1036	0	0
T15	0	594	0	0
T35	1286	0	0	0
T36	1766	0	0	0
T37	0	692	0	0
T42	1689	0	0	0
T43	0	1082	0	0
T45	8070	0	0	0
T58	0	7	0	0
T63	1318	0	0	0
T70	1776	0	0	0
T71	4049	0	0	0
T84	0	1137	0	0
T85	0	660	0	0
T86	0	410	0	0

gen_edn_if_asserts[2].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207952174	427066	0	0
T1	1506	62	0	0
T2	2725	1589	0	0
T3	1285	1231	0	0
T4	1539	150	0	0
T5	593	197	0	0
T7	1065	44	0	0
T34	1109	22	0	0
T35	1286	16	0	0
T42	1689	17	0	0
T63	1318	1231	0	0

gen_edn_if_asserts[2].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207952174	55372	0	86
T38	1635	4	0	1
T39	1921	78	0	1
T41	1809	0	0	0
T43	1736	0	0	0
T48	0	782	0	1
T49	0	667	0	1
T50	1696	0	0	0
T51	1763	0	0	0
T54	0	28	0	1
T87	0	3	0	1
T88	0	18	0	1
T89	0	3	0	1
T90	0	3	0	1
T91	0	19	0	1
T92	1167	0	0	0
T93	4274	0	0	0
T94	1057	0	0	0
T95	6733	0	0	0

gen_edn_if_asserts[2].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207952174	207827874	0	0
T1	1506	1439	0	0
T2	2725	2651	0	0
T3	1285	1232	0	0
T4	1539	1342	0	0
T5	593	471	0	0
T7	1065	980	0	0
T34	1109	1056	0	0
T35	1286	1236	0	0
T42	1689	1611	0	0
T63	1318	1232	0	0

gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207952174	114819	0	0
T4	1539	208	0	0
T5	593	280	0	0
T6	1905	1036	0	0
T15	0	594	0	0
T35	1286	0	0	0
T36	1766	0	0	0
T37	0	692	0	0
T42	1689	0	0	0
T43	0	1082	0	0
T45	8070	0	0	0
T58	0	7	0	0
T63	1318	0	0	0
T70	1776	0	0	0
T71	4049	0	0	0
T84	0	1137	0	0
T85	0	660	0	0
T86	0	410	0	0

gen_edn_if_asserts[3].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207952174	427066	0	0
T1	1506	62	0	0
T2	2725	1589	0	0
T3	1285	1231	0	0
T4	1539	150	0	0
T5	593	197	0	0
T7	1065	44	0	0
T34	1109	22	0	0
T35	1286	16	0	0
T42	1689	17	0	0
T63	1318	1231	0	0

gen_edn_if_asserts[3].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207952174	2679	0	71
T15	1037	0	0	0
T18	1961	0	0	0
T19	1672	0	0	0
T38	1635	0	0	0
T40	922	3	0	1
T44	4867	0	0	0
T50	0	4	0	1
T51	0	4	0	1
T52	0	59	0	1
T53	0	40	0	1
T54	0	56	0	1
T57	0	3	0	1
T60	1221	0	0	0
T79	0	0	0	1
T82	977117	0	0	0
T83	1362	0	0	0
T91	0	48	0	1
T96	0	3	0	0
T97	0	3	0	1
T98	1589	0	0	0

gen_edn_if_asserts[3].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207952174	207827874	0	0
T1	1506	1439	0	0
T2	2725	2651	0	0
T3	1285	1232	0	0
T4	1539	1342	0	0
T5	593	471	0	0
T7	1065	980	0	0
T34	1109	1056	0	0
T35	1286	1236	0	0
T42	1689	1611	0	0
T63	1318	1232	0	0

gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207952174	114819	0	0
T4	1539	208	0	0
T5	593	280	0	0
T6	1905	1036	0	0
T15	0	594	0	0
T35	1286	0	0	0
T36	1766	0	0	0
T37	0	692	0	0
T42	1689	0	0	0
T43	0	1082	0	0
T45	8070	0	0	0
T58	0	7	0	0
T63	1318	0	0	0
T70	1776	0	0	0
T71	4049	0	0	0
T84	0	1137	0	0
T85	0	660	0	0
T86	0	410	0	0

gen_edn_if_asserts[4].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207952174	427066	0	0
T1	1506	62	0	0
T2	2725	1589	0	0
T3	1285	1231	0	0
T4	1539	150	0	0
T5	593	197	0	0
T7	1065	44	0	0
T34	1109	22	0	0
T35	1286	16	0	0
T42	1689	17	0	0
T63	1318	1231	0	0

gen_edn_if_asserts[4].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207952174	4017	0	64
T6	1905	0	0	0
T17	1451	0	0	0
T35	1286	0	0	0
T36	1766	0	0	0
T39	0	30	0	1
T42	1689	3	0	1
T45	8070	0	0	0
T46	9728	0	0	0
T54	0	52	0	1
T55	0	3	0	1
T56	0	3	0	0
T57	0	603	0	1
T63	1318	0	0	0
T70	1776	0	0	0
T71	4049	0	0	0
T89	0	58	0	1
T91	0	79	0	1
T97	0	44	0	1
T99	0	3	0	1
T100	0	0	0	1

gen_edn_if_asserts[4].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207952174	207827874	0	0
T1	1506	1439	0	0
T2	2725	2651	0	0
T3	1285	1232	0	0
T4	1539	1342	0	0
T5	593	471	0	0
T7	1065	980	0	0
T34	1109	1056	0	0
T35	1286	1236	0	0
T42	1689	1611	0	0
T63	1318	1232	0	0

gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207952174	114819	0	0
T4	1539	208	0	0
T5	593	280	0	0
T6	1905	1036	0	0
T15	0	594	0	0
T35	1286	0	0	0
T36	1766	0	0	0
T37	0	692	0	0
T42	1689	0	0	0
T43	0	1082	0	0
T45	8070	0	0	0
T58	0	7	0	0
T63	1318	0	0	0
T70	1776	0	0	0
T71	4049	0	0	0
T84	0	1137	0	0
T85	0	660	0	0
T86	0	410	0	0

gen_edn_if_asserts[5].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207952174	427066	0	0
T1	1506	62	0	0
T2	2725	1589	0	0
T3	1285	1231	0	0
T4	1539	150	0	0
T5	593	197	0	0
T7	1065	44	0	0
T34	1109	22	0	0
T35	1286	16	0	0
T42	1689	17	0	0
T63	1318	1231	0	0

gen_edn_if_asserts[5].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207952174	3423	0	65
T2	2725	3	0	0
T3	1285	0	0	0
T4	1539	0	0	0
T5	593	0	0	0
T6	1905	0	0	0
T7	1065	0	0	0
T34	1109	0	0	0
T35	1286	0	0	0
T39	0	3	0	1
T42	1689	14	0	1
T44	0	793	0	1
T53	0	37	0	1
T55	0	46	0	1
T57	0	9	0	1
T63	1318	0	0	0
T91	0	33	0	1
T101	0	3	0	1
T102	0	24	0	1
T103	0	0	0	1

gen_edn_if_asserts[5].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207952174	207827874	0	0
T1	1506	1439	0	0
T2	2725	2651	0	0
T3	1285	1232	0	0
T4	1539	1342	0	0
T5	593	471	0	0
T7	1065	980	0	0
T34	1109	1056	0	0
T35	1286	1236	0	0
T42	1689	1611	0	0
T63	1318	1232	0	0

gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207952174	114819	0	0
T4	1539	208	0	0
T5	593	280	0	0
T6	1905	1036	0	0
T15	0	594	0	0
T35	1286	0	0	0
T36	1766	0	0	0
T37	0	692	0	0
T42	1689	0	0	0
T43	0	1082	0	0
T45	8070	0	0	0
T58	0	7	0	0
T63	1318	0	0	0
T70	1776	0	0	0
T71	4049	0	0	0
T84	0	1137	0	0
T85	0	660	0	0
T86	0	410	0	0

gen_edn_if_asserts[6].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207952174	427066	0	0
T1	1506	62	0	0
T2	2725	1589	0	0
T3	1285	1231	0	0
T4	1539	150	0	0
T5	593	197	0	0
T7	1065	44	0	0
T34	1109	22	0	0
T35	1286	16	0	0
T42	1689	17	0	0
T63	1318	1231	0	0

gen_edn_if_asserts[6].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207952174	1576	0	55
T11	2249	3	0	0
T15	1037	0	0	0
T19	1672	0	0	0
T38	1635	0	0	0
T41	1809	0	0	0
T43	1736	0	0	0
T44	4867	58	0	1
T47	445152	0	0	0
T53	0	14	0	1
T54	0	23	0	1
T57	0	3	0	1
T59	0	3	0	0
T84	1801	0	0	0
T89	0	3	0	1
T98	1589	0	0	0
T102	0	45	0	1
T104	0	3	0	0
T105	0	3	0	0
T106	0	0	0	1
T107	0	0	0	1
T108	0	0	0	1
T109	0	0	0	1

gen_edn_if_asserts[6].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207952174	207827874	0	0
T1	1506	1439	0	0
T2	2725	2651	0	0
T3	1285	1232	0	0
T4	1539	1342	0	0
T5	593	471	0	0
T7	1065	980	0	0
T34	1109	1056	0	0
T35	1286	1236	0	0
T42	1689	1611	0	0
T63	1318	1232	0	0

gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207952174	114819	0	0
T4	1539	208	0	0
T5	593	280	0	0
T6	1905	1036	0	0
T15	0	594	0	0
T35	1286	0	0	0
T36	1766	0	0	0
T37	0	692	0	0
T42	1689	0	0	0
T43	0	1082	0	0
T45	8070	0	0	0
T58	0	7	0	0
T63	1318	0	0	0
T70	1776	0	0	0
T71	4049	0	0	0
T84	0	1137	0	0
T85	0	660	0	0
T86	0	410	0	0