Unified Coverage Report :: Module :: edn_ack_sm

Module : edn_ack_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep	100.00	100.00	100.00		100.00	100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.18	100.00	85.54			100.00		u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.18	100.00	85.54			100.00		u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.18	100.00	85.54			100.00		u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.18	100.00	85.54			100.00		u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.18	100.00	85.54			100.00		u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.18	100.00	85.54			100.00		u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.18	100.00	85.54			100.00		u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_ack_sm

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T7,T11

---

FSM Coverage for Module : edn_ack_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T20
DataWait	75	Covered	T20
Disabled	107	Covered	T20
EndPointClear	63	Covered	T20
Error	99	Covered	T20
Idle	68	Covered	T20

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T20
AckPls->Error	99	Covered	T20
AckPls->Idle	85	Covered	T20
DataWait->AckPls	80	Covered	T20
DataWait->Disabled	107	Covered	T20
DataWait->Error	99	Covered	T20
Disabled->EndPointClear	63	Covered	T20
Disabled->Error	99	Covered	T20
EndPointClear->Disabled	107	Covered	T20
EndPointClear->Error	99	Covered	T20
EndPointClear->Idle	68	Covered	T20
Idle->DataWait	75	Covered	T20
Idle->Disabled	107	Covered	T20
Idle->Error	99	Covered	T20

---

Branch Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T7
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T7
Idle	-	1	1	-	Covered	T1,T7,T34
Idle	-	1	0	-	Covered	T1,T7,T34
Idle	-	0	-	-	Covered	T1,T2,T7
DataWait	-	-	-	1	Covered	T1,T7,T34
DataWait	-	-	-	0	Covered	T1,T7,T34
AckPls	-	-	-	-	Covered	T1,T7,T34
Error	-	-	-	-	Covered	T4,T5,T6
default	-	-	-	-	Covered	T84,T43,T86

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T2,T7,T11
0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_ack_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	1455665218	791687	0	0
FpvSecCmErrorStEscalate_A	1455665218	796286	0	0
u_state_regs_A	1455631587	1454761487	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1455665218	791687	0	0
T4	10773	1442	0	0
T5	4151	1946	0	0
T6	13335	7238	0	0
T15	0	4144	0	0
T35	9002	0	0	0
T36	12362	0	0	0
T37	0	4830	0	0
T42	11823	0	0	0
T43	0	7510	0	0
T45	56490	0	0	0
T63	9226	0	0	0
T70	12432	0	0	0
T71	28343	0	0	0
T84	0	7895	0	0
T85	0	4606	0	0
T86	0	2806	0	0
T142	0	8042	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1455665218	796286	0	0
T4	10773	1449	0	0
T5	4151	1953	0	0
T6	13335	7245	0	0
T15	0	4151	0	0
T35	9002	0	0	0
T36	12362	0	0	0
T37	0	4837	0	0
T42	11823	0	0	0
T43	0	7517	0	0
T45	56490	0	0	0
T63	9226	0	0	0
T70	12432	0	0	0
T71	28343	0	0	0
T84	0	7902	0	0
T85	0	4613	0	0
T86	0	2813	0	0
T142	0	8049	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1455631587	1454761487	0	0
T1	10542	10073	0	0
T2	19075	18557	0	0
T3	8995	8624	0	0
T4	9636	8257	0	0
T5	4039	3185	0	0
T7	7455	6860	0	0
T34	7763	7392	0	0
T35	9002	8652	0	0
T42	11823	11277	0	0
T63	9226	8624	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T7,T11

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T20
DataWait	75	Covered	T20
Disabled	107	Covered	T20
EndPointClear	63	Covered	T20
Error	99	Covered	T20
Idle	68	Covered	T20

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Covered	T20
AckPls->Idle	85	Covered	T20
DataWait->AckPls	80	Covered	T20
DataWait->Disabled	107	Not Covered
DataWait->Error	99	Covered	T20
Disabled->EndPointClear	63	Covered	T20
Disabled->Error	99	Covered	T20
EndPointClear->Disabled	107	Covered	T20
EndPointClear->Error	99	Covered	T20
EndPointClear->Idle	68	Covered	T20
Idle->DataWait	75	Covered	T20
Idle->Disabled	107	Covered	T20
Idle->Error	99	Covered	T20

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T7
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T7
Idle	-	1	1	-	Covered	T38,T39,T48
Idle	-	1	0	-	Covered	T37,T38,T39
Idle	-	0	-	-	Covered	T1,T2,T7
DataWait	-	-	-	1	Covered	T38,T39,T48
DataWait	-	-	-	0	Covered	T37,T38,T39
AckPls	-	-	-	-	Covered	T38,T39,T48
Error	-	-	-	-	Covered	T4,T5,T6
default	-	-	-	-	Covered	T30,T31,T32

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T2,T7,T11
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	207952174	113341	0	0
FpvSecCmErrorStEscalate_A	207952174	113998	0	0
u_state_regs_A	207952174	207827874	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207952174	113341	0	0
T4	1539	206	0	0
T5	593	278	0	0
T6	1905	1034	0	0
T15	0	592	0	0
T35	1286	0	0	0
T36	1766	0	0	0
T37	0	690	0	0
T42	1689	0	0	0
T43	0	1080	0	0
T45	8070	0	0	0
T63	1318	0	0	0
T70	1776	0	0	0
T71	4049	0	0	0
T84	0	1135	0	0
T85	0	658	0	0
T86	0	408	0	0
T142	0	1156	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207952174	113998	0	0
T4	1539	207	0	0
T5	593	279	0	0
T6	1905	1035	0	0
T15	0	593	0	0
T35	1286	0	0	0
T36	1766	0	0	0
T37	0	691	0	0
T42	1689	0	0	0
T43	0	1081	0	0
T45	8070	0	0	0
T63	1318	0	0	0
T70	1776	0	0	0
T71	4049	0	0	0
T84	0	1136	0	0
T85	0	659	0	0
T86	0	409	0	0
T142	0	1157	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207952174	207827874	0	0
T1	1506	1439	0	0
T2	2725	2651	0	0
T3	1285	1232	0	0
T4	1539	1342	0	0
T5	593	471	0	0
T7	1065	980	0	0
T34	1109	1056	0	0
T35	1286	1236	0	0
T42	1689	1611	0	0
T63	1318	1232	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T7,T11

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T20
DataWait	75	Covered	T20
Disabled	107	Covered	T20
EndPointClear	63	Covered	T20
Error	99	Covered	T20
Idle	68	Covered	T20

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T20
DataWait->AckPls	80	Covered	T20
DataWait->Disabled	107	Covered	T20
DataWait->Error	99	Covered	T20
Disabled->EndPointClear	63	Covered	T20
Disabled->Error	99	Covered	T20
EndPointClear->Disabled	107	Covered	T20
EndPointClear->Error	99	Covered	T20
EndPointClear->Idle	68	Covered	T20
Idle->DataWait	75	Covered	T20
Idle->Disabled	107	Covered	T20
Idle->Error	99	Covered	T20

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T7
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T7
Idle	-	1	1	-	Covered	T2,T42,T44
Idle	-	1	0	-	Covered	T2,T42,T44
Idle	-	0	-	-	Covered	T1,T2,T7
DataWait	-	-	-	1	Covered	T2,T42,T44
DataWait	-	-	-	0	Covered	T2,T42,T44
AckPls	-	-	-	-	Covered	T2,T42,T44
Error	-	-	-	-	Covered	T4,T5,T6
default	-	-	-	-	Covered	T30,T31,T32

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T2,T7,T11
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	207952174	113341	0	0
FpvSecCmErrorStEscalate_A	207952174	113998	0	0
u_state_regs_A	207952174	207827874	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207952174	113341	0	0
T4	1539	206	0	0
T5	593	278	0	0
T6	1905	1034	0	0
T15	0	592	0	0
T35	1286	0	0	0
T36	1766	0	0	0
T37	0	690	0	0
T42	1689	0	0	0
T43	0	1080	0	0
T45	8070	0	0	0
T63	1318	0	0	0
T70	1776	0	0	0
T71	4049	0	0	0
T84	0	1135	0	0
T85	0	658	0	0
T86	0	408	0	0
T142	0	1156	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207952174	113998	0	0
T4	1539	207	0	0
T5	593	279	0	0
T6	1905	1035	0	0
T15	0	593	0	0
T35	1286	0	0	0
T36	1766	0	0	0
T37	0	691	0	0
T42	1689	0	0	0
T43	0	1081	0	0
T45	8070	0	0	0
T63	1318	0	0	0
T70	1776	0	0	0
T71	4049	0	0	0
T84	0	1136	0	0
T85	0	659	0	0
T86	0	409	0	0
T142	0	1157	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207952174	207827874	0	0
T1	1506	1439	0	0
T2	2725	2651	0	0
T3	1285	1232	0	0
T4	1539	1342	0	0
T5	593	471	0	0
T7	1065	980	0	0
T34	1109	1056	0	0
T35	1286	1236	0	0
T42	1689	1611	0	0
T63	1318	1232	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T7,T11

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T20
DataWait	75	Covered	T20
Disabled	107	Covered	T20
EndPointClear	63	Covered	T20
Error	99	Covered	T20
Idle	68	Covered	T20

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Covered	T20
AckPls->Idle	85	Covered	T20
DataWait->AckPls	80	Covered	T20
DataWait->Disabled	107	Covered	T20
DataWait->Error	99	Covered	T20
Disabled->EndPointClear	63	Covered	T20
Disabled->Error	99	Covered	T20
EndPointClear->Disabled	107	Covered	T20
EndPointClear->Error	99	Covered	T20
EndPointClear->Idle	68	Covered	T20
Idle->DataWait	75	Covered	T20
Idle->Disabled	107	Covered	T20
Idle->Error	99	Covered	T20

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T7
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T7
Idle	-	1	1	-	Covered	T7,T34,T35
Idle	-	1	0	-	Covered	T7,T34,T35
Idle	-	0	-	-	Covered	T1,T2,T7
DataWait	-	-	-	1	Covered	T7,T34,T35
DataWait	-	-	-	0	Covered	T7,T34,T35
AckPls	-	-	-	-	Covered	T7,T34,T35
Error	-	-	-	-	Covered	T4,T5,T6
default	-	-	-	-	Covered	T84,T43,T86

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T2,T7,T11
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	207952174	111641	0	0
FpvSecCmErrorStEscalate_A	207952174	112298	0	0
u_state_regs_A	207918543	207794243	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207952174	111641	0	0
T4	1539	206	0	0
T5	593	278	0	0
T6	1905	1034	0	0
T15	0	592	0	0
T35	1286	0	0	0
T36	1766	0	0	0
T37	0	690	0	0
T42	1689	0	0	0
T43	0	1030	0	0
T45	8070	0	0	0
T63	1318	0	0	0
T70	1776	0	0	0
T71	4049	0	0	0
T84	0	1085	0	0
T85	0	658	0	0
T86	0	358	0	0
T142	0	1106	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207952174	112298	0	0
T4	1539	207	0	0
T5	593	279	0	0
T6	1905	1035	0	0
T15	0	593	0	0
T35	1286	0	0	0
T36	1766	0	0	0
T37	0	691	0	0
T42	1689	0	0	0
T43	0	1031	0	0
T45	8070	0	0	0
T63	1318	0	0	0
T70	1776	0	0	0
T71	4049	0	0	0
T84	0	1086	0	0
T85	0	659	0	0
T86	0	359	0	0
T142	0	1107	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207918543	207794243	0	0
T1	1506	1439	0	0
T2	2725	2651	0	0
T3	1285	1232	0	0
T4	402	205	0	0
T5	481	359	0	0
T7	1065	980	0	0
T34	1109	1056	0	0
T35	1286	1236	0	0
T42	1689	1611	0	0
T63	1318	1232	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T7,T11

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T20
DataWait	75	Covered	T20
Disabled	107	Covered	T20
EndPointClear	63	Covered	T20
Error	99	Covered	T20
Idle	68	Covered	T20

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Covered	T20
AckPls->Idle	85	Covered	T20
DataWait->AckPls	80	Covered	T20
DataWait->Disabled	107	Covered	T20
DataWait->Error	99	Covered	T20
Disabled->EndPointClear	63	Covered	T20
Disabled->Error	99	Covered	T20
EndPointClear->Disabled	107	Covered	T20
EndPointClear->Error	99	Covered	T20
EndPointClear->Idle	68	Covered	T20
Idle->DataWait	75	Covered	T20
Idle->Disabled	107	Covered	T20
Idle->Error	99	Covered	T20

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T7
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T7
Idle	-	1	1	-	Covered	T5,T40,T41
Idle	-	1	0	-	Covered	T5,T40,T41
Idle	-	0	-	-	Covered	T1,T2,T7
DataWait	-	-	-	1	Covered	T5,T40,T41
DataWait	-	-	-	0	Covered	T40,T41,T50
AckPls	-	-	-	-	Covered	T5,T40,T41
Error	-	-	-	-	Covered	T4,T5,T6
default	-	-	-	-	Covered	T30,T31,T32

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T2,T7,T11
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	207952174	113341	0	0
FpvSecCmErrorStEscalate_A	207952174	113998	0	0
u_state_regs_A	207952174	207827874	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207952174	113341	0	0
T4	1539	206	0	0
T5	593	278	0	0
T6	1905	1034	0	0
T15	0	592	0	0
T35	1286	0	0	0
T36	1766	0	0	0
T37	0	690	0	0
T42	1689	0	0	0
T43	0	1080	0	0
T45	8070	0	0	0
T63	1318	0	0	0
T70	1776	0	0	0
T71	4049	0	0	0
T84	0	1135	0	0
T85	0	658	0	0
T86	0	408	0	0
T142	0	1156	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207952174	113998	0	0
T4	1539	207	0	0
T5	593	279	0	0
T6	1905	1035	0	0
T15	0	593	0	0
T35	1286	0	0	0
T36	1766	0	0	0
T37	0	691	0	0
T42	1689	0	0	0
T43	0	1081	0	0
T45	8070	0	0	0
T63	1318	0	0	0
T70	1776	0	0	0
T71	4049	0	0	0
T84	0	1136	0	0
T85	0	659	0	0
T86	0	409	0	0
T142	0	1157	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207952174	207827874	0	0
T1	1506	1439	0	0
T2	2725	2651	0	0
T3	1285	1232	0	0
T4	1539	1342	0	0
T5	593	471	0	0
T7	1065	980	0	0
T34	1109	1056	0	0
T35	1286	1236	0	0
T42	1689	1611	0	0
T63	1318	1232	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T7,T11

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T20
DataWait	75	Covered	T20
Disabled	107	Covered	T20
EndPointClear	63	Covered	T20
Error	99	Covered	T20
Idle	68	Covered	T20

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T20
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T20
DataWait->AckPls	80	Covered	T20
DataWait->Disabled	107	Covered	T20
DataWait->Error	99	Covered	T20
Disabled->EndPointClear	63	Covered	T20
Disabled->Error	99	Covered	T20
EndPointClear->Disabled	107	Covered	T20
EndPointClear->Error	99	Covered	T20
EndPointClear->Idle	68	Covered	T20
Idle->DataWait	75	Covered	T20
Idle->Disabled	107	Covered	T20
Idle->Error	99	Covered	T20

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T7
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T7
Idle	-	1	1	-	Covered	T42,T39,T55
Idle	-	1	0	-	Covered	T42,T15,T43
Idle	-	0	-	-	Covered	T1,T2,T7
DataWait	-	-	-	1	Covered	T42,T39,T55
DataWait	-	-	-	0	Covered	T42,T15,T39
AckPls	-	-	-	-	Covered	T42,T39,T55
Error	-	-	-	-	Covered	T4,T5,T6
default	-	-	-	-	Covered	T30,T31,T32

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T2,T7,T11
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	207952174	113341	0	0
FpvSecCmErrorStEscalate_A	207952174	113998	0	0
u_state_regs_A	207952174	207827874	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207952174	113341	0	0
T4	1539	206	0	0
T5	593	278	0	0
T6	1905	1034	0	0
T15	0	592	0	0
T35	1286	0	0	0
T36	1766	0	0	0
T37	0	690	0	0
T42	1689	0	0	0
T43	0	1080	0	0
T45	8070	0	0	0
T63	1318	0	0	0
T70	1776	0	0	0
T71	4049	0	0	0
T84	0	1135	0	0
T85	0	658	0	0
T86	0	408	0	0
T142	0	1156	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207952174	113998	0	0
T4	1539	207	0	0
T5	593	279	0	0
T6	1905	1035	0	0
T15	0	593	0	0
T35	1286	0	0	0
T36	1766	0	0	0
T37	0	691	0	0
T42	1689	0	0	0
T43	0	1081	0	0
T45	8070	0	0	0
T63	1318	0	0	0
T70	1776	0	0	0
T71	4049	0	0	0
T84	0	1136	0	0
T85	0	659	0	0
T86	0	409	0	0
T142	0	1157	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207952174	207827874	0	0
T1	1506	1439	0	0
T2	2725	2651	0	0
T3	1285	1232	0	0
T4	1539	1342	0	0
T5	593	471	0	0
T7	1065	980	0	0
T34	1109	1056	0	0
T35	1286	1236	0	0
T42	1689	1611	0	0
T63	1318	1232	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T7,T11

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T20
DataWait	75	Covered	T20
Disabled	107	Covered	T20
EndPointClear	63	Covered	T20
Error	99	Covered	T20
Idle	68	Covered	T20

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T20
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T20
DataWait->AckPls	80	Covered	T20
DataWait->Disabled	107	Covered	T20
DataWait->Error	99	Covered	T20
Disabled->EndPointClear	63	Covered	T20
Disabled->Error	99	Covered	T20
EndPointClear->Disabled	107	Covered	T20
EndPointClear->Error	99	Covered	T20
EndPointClear->Idle	68	Covered	T20
Idle->DataWait	75	Covered	T20
Idle->Disabled	107	Covered	T20
Idle->Error	99	Covered	T20

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T7
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T7
Idle	-	1	1	-	Covered	T11,T44,T59
Idle	-	1	0	-	Covered	T4,T11,T44
Idle	-	0	-	-	Covered	T1,T2,T7
DataWait	-	-	-	1	Covered	T11,T44,T59
DataWait	-	-	-	0	Covered	T4,T11,T44
AckPls	-	-	-	-	Covered	T11,T44,T59
Error	-	-	-	-	Covered	T4,T5,T6
default	-	-	-	-	Covered	T30,T31,T32

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T2,T7,T11
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	207952174	113341	0	0
FpvSecCmErrorStEscalate_A	207952174	113998	0	0
u_state_regs_A	207952174	207827874	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207952174	113341	0	0
T4	1539	206	0	0
T5	593	278	0	0
T6	1905	1034	0	0
T15	0	592	0	0
T35	1286	0	0	0
T36	1766	0	0	0
T37	0	690	0	0
T42	1689	0	0	0
T43	0	1080	0	0
T45	8070	0	0	0
T63	1318	0	0	0
T70	1776	0	0	0
T71	4049	0	0	0
T84	0	1135	0	0
T85	0	658	0	0
T86	0	408	0	0
T142	0	1156	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207952174	113998	0	0
T4	1539	207	0	0
T5	593	279	0	0
T6	1905	1035	0	0
T15	0	593	0	0
T35	1286	0	0	0
T36	1766	0	0	0
T37	0	691	0	0
T42	1689	0	0	0
T43	0	1081	0	0
T45	8070	0	0	0
T63	1318	0	0	0
T70	1776	0	0	0
T71	4049	0	0	0
T84	0	1136	0	0
T85	0	659	0	0
T86	0	409	0	0
T142	0	1157	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207952174	207827874	0	0
T1	1506	1439	0	0
T2	2725	2651	0	0
T3	1285	1232	0	0
T4	1539	1342	0	0
T5	593	471	0	0
T7	1065	980	0	0
T34	1109	1056	0	0
T35	1286	1236	0	0
T42	1689	1611	0	0
T63	1318	1232	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T7,T11

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T20
DataWait	75	Covered	T20
Disabled	107	Covered	T20
EndPointClear	63	Covered	T20
Error	99	Covered	T20
Idle	68	Covered	T20

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T20
AckPls->Error	99	Covered	T20
AckPls->Idle	85	Covered	T20
DataWait->AckPls	80	Covered	T20
DataWait->Disabled	107	Covered	T20
DataWait->Error	99	Covered	T20
Disabled->EndPointClear	63	Covered	T20
Disabled->Error	99	Covered	T20
EndPointClear->Disabled	107	Covered	T20
EndPointClear->Error	99	Covered	T20
EndPointClear->Idle	68	Covered	T20
Idle->DataWait	75	Covered	T20
Idle->Disabled	107	Covered	T20
Idle->Error	99	Covered	T20

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T7
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T7
Idle	-	1	1	-	Covered	T1,T6,T36
Idle	-	1	0	-	Covered	T1,T6,T36
Idle	-	0	-	-	Covered	T1,T2,T7
DataWait	-	-	-	1	Covered	T1,T6,T36
DataWait	-	-	-	0	Covered	T1,T36,T17
AckPls	-	-	-	-	Covered	T1,T6,T36
Error	-	-	-	-	Covered	T4,T5,T6
default	-	-	-	-	Covered	T30,T31,T32

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T6
0	1	Covered	T2,T7,T11
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	207952174	113341	0	0
FpvSecCmErrorStEscalate_A	207952174	113998	0	0
u_state_regs_A	207952174	207827874	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207952174	113341	0	0
T4	1539	206	0	0
T5	593	278	0	0
T6	1905	1034	0	0
T15	0	592	0	0
T35	1286	0	0	0
T36	1766	0	0	0
T37	0	690	0	0
T42	1689	0	0	0
T43	0	1080	0	0
T45	8070	0	0	0
T63	1318	0	0	0
T70	1776	0	0	0
T71	4049	0	0	0
T84	0	1135	0	0
T85	0	658	0	0
T86	0	408	0	0
T142	0	1156	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207952174	113998	0	0
T4	1539	207	0	0
T5	593	279	0	0
T6	1905	1035	0	0
T15	0	593	0	0
T35	1286	0	0	0
T36	1766	0	0	0
T37	0	691	0	0
T42	1689	0	0	0
T43	0	1081	0	0
T45	8070	0	0	0
T63	1318	0	0	0
T70	1776	0	0	0
T71	4049	0	0	0
T84	0	1136	0	0
T85	0	659	0	0
T86	0	409	0	0
T142	0	1157	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207952174	207827874	0	0
T1	1506	1439	0	0
T2	2725	2651	0	0
T3	1285	1232	0	0
T4	1539	1342	0	0
T5	593	471	0	0
T7	1065	980	0	0
T34	1109	1056	0	0
T35	1286	1236	0	0
T42	1689	1611	0	0
T63	1318	1232	0	0