Unified Coverage Report :: Module :: edn_core

Module : edn_core

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.18	100.00	85.54			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_core.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core	95.18	100.00	85.54			100.00

---

Module Instance : tb.dut.u_edn_core

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.18	100.00	85.54			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.92	99.92	89.18	70.79	93.42	99.29	98.91

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44		83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_ep_blk[0].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
gen_ep_blk[0].u_prim_packer_fifo_ep	98.81	100.00	95.24			100.00	100.00
gen_ep_blk[1].u_edn_ack_sm_ep	100.00	100.00	100.00		100.00	100.00	100.00
gen_ep_blk[1].u_prim_packer_fifo_ep	98.81	100.00	95.24			100.00	100.00
gen_ep_blk[2].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
gen_ep_blk[2].u_prim_packer_fifo_ep	98.21	100.00	92.86			100.00	100.00
gen_ep_blk[3].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
gen_ep_blk[3].u_prim_packer_fifo_ep	98.81	100.00	95.24			100.00	100.00
gen_ep_blk[4].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
gen_ep_blk[4].u_prim_packer_fifo_ep	98.81	100.00	95.24			100.00	100.00
gen_ep_blk[5].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
gen_ep_blk[5].u_prim_packer_fifo_ep	98.21	100.00	92.86			100.00	100.00
gen_ep_blk[6].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
gen_ep_blk[6].u_prim_packer_fifo_ep	98.81	100.00	95.24			100.00	100.00
u_edn_main_sm	99.26	100.00	100.00		96.30	100.00	100.00
u_intr_hw_edn_cmd_req_done	100.00	100.00	100.00			100.00	100.00
u_intr_hw_edn_fatal_err	100.00	100.00	100.00			100.00	100.00
u_prim_arbiter_ppc_packer_arb	95.16	95.00	92.31			100.00	93.33
u_prim_count_max_reqs_cntr	70.79			70.79
u_prim_edge_detector_recov_alert	88.89	100.00	66.67			100.00
u_prim_fifo_sync_gencmd	96.15	100.00	84.62			100.00	100.00
u_prim_fifo_sync_output	91.06	100.00	69.23			95.00	100.00
u_prim_fifo_sync_rescmd	97.12	100.00	88.46			100.00	100.00
u_prim_mubi4_sync_auto_req_mode	100.00	100.00					100.00
u_prim_mubi4_sync_boot_req_mode	100.00	100.00					100.00
u_prim_mubi4_sync_cmd_fifo_rst	100.00	100.00					100.00
u_prim_mubi4_sync_edn_enable	100.00	100.00					100.00
u_prim_packer_fifo_cs	95.24	100.00	95.24			85.71	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : edn_core

	Line No.	Total	Covered	Percent
TOTAL		238	238	100.00
ALWAYS	225	29	29	100.00
CONT_ASSIGN	293	1	1	100.00
CONT_ASSIGN	298	1	1	100.00
CONT_ASSIGN	303	1	1	100.00
CONT_ASSIGN	310	1	1	100.00
CONT_ASSIGN	312	1	1	100.00
CONT_ASSIGN	314	1	1	100.00
CONT_ASSIGN	316	1	1	100.00
CONT_ASSIGN	318	1	1	100.00
CONT_ASSIGN	320	1	1	100.00
CONT_ASSIGN	323	1	1	100.00
CONT_ASSIGN	328	1	1	100.00
CONT_ASSIGN	333	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	345	1	1	100.00
CONT_ASSIGN	348	1	1	100.00
CONT_ASSIGN	351	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	357	1	1	100.00
CONT_ASSIGN	359	1	1	100.00
CONT_ASSIGN	360	1	1	100.00
CONT_ASSIGN	365	1	1	100.00
CONT_ASSIGN	368	1	1	100.00
CONT_ASSIGN	371	1	1	100.00
CONT_ASSIGN	376	1	1	100.00
CONT_ASSIGN	376	1	1	100.00
CONT_ASSIGN	376	1	1	100.00
CONT_ASSIGN	376	1	1	100.00
CONT_ASSIGN	376	1	1	100.00
CONT_ASSIGN	376	1	1	100.00
CONT_ASSIGN	376	1	1	100.00
CONT_ASSIGN	376	1	1	100.00
CONT_ASSIGN	376	1	1	100.00
CONT_ASSIGN	376	1	1	100.00
CONT_ASSIGN	376	1	1	100.00
CONT_ASSIGN	376	1	1	100.00
CONT_ASSIGN	376	1	1	100.00
CONT_ASSIGN	376	1	1	100.00
CONT_ASSIGN	376	1	1	100.00
CONT_ASSIGN	376	1	1	100.00
CONT_ASSIGN	376	1	1	100.00
CONT_ASSIGN	376	1	1	100.00
CONT_ASSIGN	376	1	1	100.00
CONT_ASSIGN	376	1	1	100.00
CONT_ASSIGN	376	1	1	100.00
CONT_ASSIGN	376	1	1	100.00
CONT_ASSIGN	376	1	1	100.00
CONT_ASSIGN	376	1	1	100.00
CONT_ASSIGN	376	1	1	100.00
CONT_ASSIGN	376	1	1	100.00
CONT_ASSIGN	376	1	1	100.00
CONT_ASSIGN	376	1	1	100.00
CONT_ASSIGN	376	1	1	100.00
CONT_ASSIGN	376	1	1	100.00
CONT_ASSIGN	376	1	1	100.00
CONT_ASSIGN	381	1	1	100.00
CONT_ASSIGN	384	1	1	100.00
CONT_ASSIGN	388	1	1	100.00
CONT_ASSIGN	397	1	1	100.00
CONT_ASSIGN	398	1	1	100.00
CONT_ASSIGN	399	1	1	100.00
CONT_ASSIGN	400	1	1	100.00
CONT_ASSIGN	403	1	1	100.00
CONT_ASSIGN	403	1	1	100.00
CONT_ASSIGN	403	1	1	100.00
CONT_ASSIGN	403	1	1	100.00
CONT_ASSIGN	403	1	1	100.00
CONT_ASSIGN	403	1	1	100.00
CONT_ASSIGN	403	1	1	100.00
CONT_ASSIGN	403	1	1	100.00
CONT_ASSIGN	403	1	1	100.00
CONT_ASSIGN	403	1	1	100.00
CONT_ASSIGN	403	1	1	100.00
CONT_ASSIGN	403	1	1	100.00
CONT_ASSIGN	403	1	1	100.00
CONT_ASSIGN	403	1	1	100.00
CONT_ASSIGN	403	1	1	100.00
CONT_ASSIGN	403	1	1	100.00
CONT_ASSIGN	403	1	1	100.00
CONT_ASSIGN	403	1	1	100.00
CONT_ASSIGN	403	1	1	100.00
CONT_ASSIGN	403	1	1	100.00
CONT_ASSIGN	403	1	1	100.00
CONT_ASSIGN	403	1	1	100.00
CONT_ASSIGN	418	1	1	100.00
CONT_ASSIGN	419	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	421	1	1	100.00
CONT_ASSIGN	424	1	1	100.00
CONT_ASSIGN	424	1	1	100.00
CONT_ASSIGN	424	1	1	100.00
CONT_ASSIGN	438	1	1	100.00
CONT_ASSIGN	445	1	1	100.00
CONT_ASSIGN	446	1	1	100.00
CONT_ASSIGN	447	1	1	100.00
CONT_ASSIGN	448	1	1	100.00
CONT_ASSIGN	449	1	1	100.00
CONT_ASSIGN	464	1	1	100.00
CONT_ASSIGN	465	1	1	100.00
CONT_ASSIGN	467	1	1	100.00
CONT_ASSIGN	468	1	1	100.00
CONT_ASSIGN	470	1	1	100.00
CONT_ASSIGN	471	1	1	100.00
CONT_ASSIGN	473	1	1	100.00
CONT_ASSIGN	474	1	1	100.00
CONT_ASSIGN	476	1	1	100.00
CONT_ASSIGN	482	1	1	100.00
CONT_ASSIGN	486	1	1	100.00
CONT_ASSIGN	492	1	1	100.00
CONT_ASSIGN	500	1	1	100.00
CONT_ASSIGN	501	1	1	100.00
CONT_ASSIGN	502	1	1	100.00
CONT_ASSIGN	510	1	1	100.00
CONT_ASSIGN	513	1	1	100.00
CONT_ASSIGN	514	1	1	100.00
CONT_ASSIGN	515	1	1	100.00
CONT_ASSIGN	516	1	1	100.00
CONT_ASSIGN	518	1	1	100.00
CONT_ASSIGN	546	1	1	100.00
CONT_ASSIGN	548	1	1	100.00
CONT_ASSIGN	552	1	1	100.00
CONT_ASSIGN	556	1	1	100.00
CONT_ASSIGN	558	1	1	100.00
CONT_ASSIGN	560	1	1	100.00
CONT_ASSIGN	586	1	1	100.00
CONT_ASSIGN	588	1	1	100.00
CONT_ASSIGN	593	1	1	100.00
CONT_ASSIGN	598	1	1	100.00
CONT_ASSIGN	600	1	1	100.00
CONT_ASSIGN	602	1	1	100.00
CONT_ASSIGN	628	1	1	100.00
CONT_ASSIGN	629	1	1	100.00
CONT_ASSIGN	631	1	1	100.00
CONT_ASSIGN	632	1	1	100.00
CONT_ASSIGN	633	1	1	100.00
CONT_ASSIGN	634	1	1	100.00
CONT_ASSIGN	636	1	1	100.00
CONT_ASSIGN	695	1	1	100.00
CONT_ASSIGN	699	1	1	100.00
CONT_ASSIGN	702	1	1	100.00
CONT_ASSIGN	710	1	1	100.00
CONT_ASSIGN	714	1	1	100.00
CONT_ASSIGN	715	1	1	100.00
CONT_ASSIGN	716	1	1	100.00
CONT_ASSIGN	717	1	1	100.00
CONT_ASSIGN	720	1	1	100.00
CONT_ASSIGN	756	1	1	100.00
CONT_ASSIGN	756	1	1	100.00
CONT_ASSIGN	756	1	1	100.00
CONT_ASSIGN	756	1	1	100.00
CONT_ASSIGN	756	1	1	100.00
CONT_ASSIGN	756	1	1	100.00
CONT_ASSIGN	756	1	1	100.00
CONT_ASSIGN	780	1	1	100.00
CONT_ASSIGN	781	1	1	100.00
CONT_ASSIGN	782	1	1	100.00
CONT_ASSIGN	783	1	1	100.00
CONT_ASSIGN	784	1	1	100.00
CONT_ASSIGN	785	1	1	100.00
CONT_ASSIGN	787	1	1	100.00
CONT_ASSIGN	802	1	1	100.00
CONT_ASSIGN	804	1	1	100.00
CONT_ASSIGN	806	1	1	100.00
CONT_ASSIGN	812	1	1	100.00
CONT_ASSIGN	830	1	1	100.00
CONT_ASSIGN	831	1	1	100.00
CONT_ASSIGN	855	1	1	100.00
CONT_ASSIGN	855	1	1	100.00
CONT_ASSIGN	855	1	1	100.00
CONT_ASSIGN	855	1	1	100.00
CONT_ASSIGN	855	1	1	100.00
CONT_ASSIGN	855	1	1	100.00
CONT_ASSIGN	855	1	1	100.00
CONT_ASSIGN	856	1	1	100.00
CONT_ASSIGN	856	1	1	100.00
CONT_ASSIGN	856	1	1	100.00
CONT_ASSIGN	856	1	1	100.00
CONT_ASSIGN	856	1	1	100.00
CONT_ASSIGN	856	1	1	100.00
CONT_ASSIGN	856	1	1	100.00
CONT_ASSIGN	859	1	1	100.00
CONT_ASSIGN	859	1	1	100.00
CONT_ASSIGN	859	1	1	100.00
CONT_ASSIGN	859	1	1	100.00
CONT_ASSIGN	859	1	1	100.00
CONT_ASSIGN	859	1	1	100.00
CONT_ASSIGN	859	1	1	100.00
CONT_ASSIGN	862	1	1	100.00
CONT_ASSIGN	862	1	1	100.00
CONT_ASSIGN	862	1	1	100.00
CONT_ASSIGN	862	1	1	100.00
CONT_ASSIGN	862	1	1	100.00
CONT_ASSIGN	862	1	1	100.00
CONT_ASSIGN	862	1	1	100.00
CONT_ASSIGN	865	1	1	100.00
CONT_ASSIGN	865	1	1	100.00
CONT_ASSIGN	865	1	1	100.00
CONT_ASSIGN	865	1	1	100.00
CONT_ASSIGN	865	1	1	100.00
CONT_ASSIGN	865	1	1	100.00
CONT_ASSIGN	865	1	1	100.00
CONT_ASSIGN	866	1	1	100.00
CONT_ASSIGN	866	1	1	100.00
CONT_ASSIGN	866	1	1	100.00
CONT_ASSIGN	866	1	1	100.00
CONT_ASSIGN	866	1	1	100.00
CONT_ASSIGN	866	1	1	100.00
CONT_ASSIGN	866	1	1	100.00
CONT_ASSIGN	886	1	1	100.00
CONT_ASSIGN	892	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_core.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_core.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
238	1	1
239	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
253	1	1
254	1	1
293	1	1
298	1	1
303	1	1
310	1	1
312	1	1
314	1	1
316	1	1
318	1	1
320	1	1
323	1	1
328	1	1
333	1	1
342	1	1
345	1	1
348	1	1
351	1	1
354	1	1
357	1	1
359	1	1
360	1	1
365	1	1
368	1	1
371	1	1
376	31	31
381	1	1
384	1	1
388	1	1
397	1	1
398	1	1
399	1	1
400	1	1
403	22	22
418	1	1
419	1	1
420	1	1
421	1	1
424	3	3
438	1	1
445	1	1
446	1	1
447	1	1
448	1	1
449	1	1
464	1	1
465	1	1
467	1	1
468	1	1
470	1	1
471	1	1
473	1	1
474	1	1
476	1	1
482	1	1
486	1	1
492	1	1
500	1	1
501	1	1
502	1	1
510	1	1
513	1	1
514	1	1
515	1	1
516	1	1
518	1	1
546	1	1
548	1	1
552	1	1
556	1	1
558	1	1
560	1	1
586	1	1
588	1	1
593	1	1
598	1	1
600	1	1
602	1	1
628	1	1
629	1	1
631	1	1
632	1	1
633	1	1
634	1	1
636	1	1
695	1	1
699	1	1
702	1	1
710	1	1
714	1	1
715	1	1
716	1	1
717	1	1
720	1	1
756	7	7
780	1	1
781	1	1
782	1	1
783	1	1
784	1	1
785	1	1
787	1	1
802	1	1
804	1	1
806	1	1
812	1	1
830	1	1
831	1	1
855	7	7
856	7	7
859	7	7
862	7	7
865	7	7
866	7	7
886	1	1
892	1	1

---

Cond Coverage for Module : edn_core

	Total	Covered	Percent
Conditions	498	426	85.54
Logical	498	426	85.54
Non-Logical	0	0
Event	0	0

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.

Line numbers	Percent
298-859	85.56
859-892	85.29

---

Branch Coverage for Module : edn_core

	Line No.	Total	Covered	Percent
Branches		71	71	100.00
TERNARY	476	4	4	100.00
TERNARY	482	2	2	100.00
TERNARY	486	4	4	100.00
TERNARY	492	3	3	100.00
TERNARY	502	6	6	100.00
TERNARY	518	5	5	100.00
TERNARY	548	2	2	100.00
TERNARY	552	2	2	100.00
TERNARY	588	3	3	100.00
TERNARY	593	3	3	100.00
TERNARY	702	6	6	100.00
TERNARY	787	3	3	100.00
TERNARY	804	2	2	100.00
TERNARY	806	3	3	100.00
TERNARY	859	3	3	100.00
TERNARY	859	3	3	100.00
TERNARY	859	3	3	100.00
TERNARY	859	3	3	100.00
TERNARY	859	3	3	100.00
TERNARY	859	3	3	100.00
TERNARY	859	3	3	100.00
IF	225	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_core.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_core.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	476	((!edn_enable_fo[CsrngCmdReq])) ? 
-2-:	476	(boot_wr_cmd_reg) ? 
-3-:	476	(sw_cmd_req_load) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T7,T4,T37
0	0	1	Covered	T1,T2,T34
0	0	0	Covered	T1,T2,T7

	LineNo.	Expression
-1-:	482	((!edn_enable_fo[CsrngCmdReqValid])) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T7

	LineNo.	Expression
-1-:	486	((!edn_enable_fo[CsrngCmdReqOut])) ? 
-2-:	486	(send_rescmd) ? 
-3-:	486	((send_gencmd || boot_send_gencmd)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T11
0	0	1	Covered	T1,T2,T7
0	0	0	Covered	T1,T2,T7

	LineNo.	Expression
-1-:	492	((!edn_enable_fo[CsrngCmdReqValidOut])) ? 
-2-:	492	(((send_rescmd || send_gencmd) || (boot_send_gencmd && cmd_sent))) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
0	0	Covered	T1,T2,T7

	LineNo.	Expression
-1-:	502	((!edn_enable_q)) ? 
-2-:	502	(sw_cmd_req_load) ? 
-3-:	502	(auto_first_ack_wait) ? 
-4-:	502	(main_sm_busy) ? 
-5-:	502	(csrng_cmd_i.csrng_req_ready) ? 

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T1,T2,T34
0	0	1	-	-	Covered	T1,T2,T11
0	0	0	1	-	Covered	T1,T2,T7
0	0	0	0	1	Covered	T1,T7,T34
0	0	0	0	0	Covered	T1,T7,T34

	LineNo.	Expression
-1-:	518	((!edn_enable_fo[IntrStatus])) ? 
-2-:	518	(main_sm_done_pulse) ? 
-3-:	518	(auto_set_intr_gate) ? 
-4-:	518	(auto_clr_intr_gate) ? 

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Covered	T1,T7,T34
0	0	1	-	Covered	T1,T2,T11
0	0	0	1	Covered	T1,T2,T11
0	0	0	0	Covered	T1,T2,T7

	LineNo.	Expression
-1-:	548	((send_rescmd_q & edn_enable_fo[SendReseedCmd])) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	552	(auto_req_mode_busy) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T11
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	588	((boot_wr_cmd_genfifo & edn_enable_fo[SendGenCmd])) ? 
-2-:	588	((send_gencmd_q & edn_enable_fo[SendGenCmd])) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T7,T4,T37
0	1	Covered	T1,T2,T11
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	593	(boot_wr_cmd_genfifo) ? 
-2-:	593	(auto_req_mode_busy) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T7,T4,T37
0	1	Covered	T1,T2,T11
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	702	((!edn_enable_fo[CmdFifoCnt])) ? 
-2-:	702	((cmd_fifo_rst_fo[3] || main_sm_done_pulse)) ? 
-3-:	702	(capt_gencmd_fifo_cnt) ? 
-4-:	702	(capt_rescmd_fifo_cnt) ? 
-5-:	702	(((send_gencmd || boot_send_gencmd) || send_rescmd)) ? 

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T1,T7,T34
0	0	1	-	-	Covered	T1,T2,T7
0	0	0	1	-	Covered	T1,T2,T11
0	0	0	0	1	Covered	T1,T2,T7
0	0	0	0	0	Covered	T1,T2,T7

	LineNo.	Expression
-1-:	787	((!edn_enable_fo[CsrngFipsEn])) ? 
-2-:	787	((packer_cs_push && packer_cs_wready)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
0	0	Covered	T1,T2,T7

	LineNo.	Expression
-1-:	804	(cs_rdata_capt_vld) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	806	((!edn_enable_fo[CsrngDataVld])) ? 
-2-:	806	(cs_rdata_capt_vld) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
0	0	Covered	T1,T2,T7

	LineNo.	Expression
-1-:	859	(packer_ep_clr[0]) ? 
-2-:	859	((packer_ep_push[0] && packer_ep_wready[0])) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T7
0	1	Covered	T7,T34,T35
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	859	(packer_ep_clr[1]) ? 
-2-:	859	((packer_ep_push[1] && packer_ep_wready[1])) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T7
0	1	Covered	T1,T6,T36
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	859	(packer_ep_clr[2]) ? 
-2-:	859	((packer_ep_push[2] && packer_ep_wready[2])) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T7
0	1	Covered	T38,T39,T48
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	859	(packer_ep_clr[3]) ? 
-2-:	859	((packer_ep_push[3] && packer_ep_wready[3])) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T7
0	1	Covered	T5,T40,T41
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	859	(packer_ep_clr[4]) ? 
-2-:	859	((packer_ep_push[4] && packer_ep_wready[4])) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T7
0	1	Covered	T42,T39,T55
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	859	(packer_ep_clr[5]) ? 
-2-:	859	((packer_ep_push[5] && packer_ep_wready[5])) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T7
0	1	Covered	T2,T42,T44
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	859	(packer_ep_clr[6]) ? 
-2-:	859	((packer_ep_push[6] && packer_ep_wready[6])) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T7
0	1	Covered	T11,T44,T59
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	225	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3