Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44		83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	211018839	10102798	0	0
boot_gen_cmd_rd_A	211018839	54205	0	0
boot_ins_cmd_rd_A	211018839	60848	0	0
ctrl_rd_A	211018839	54077	0	0
err_code_test_rd_A	211018839	54222	0	0
intr_enable_rd_A	211018839	59513	0	0
max_num_reqs_between_reseeds_rd_A	211018839	61927	0	0
regwen_rd_A	211018839	62137	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211018839	10102798	0	0
T26	4153	6	0	0
T27	4213	3	0	0
T28	2706	47	0	0
T134	5098	310	0	0
T135	8919	686	0	0
T184	7577	12	0	0
T185	0	574	0	0
T186	0	4	0	0
T187	0	4	0	0
T188	0	746	0	0
T189	1012	0	0	0
T190	1576	0	0	0
T191	962	0	0	0
T192	1161	0	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211018839	54205	0	0
T27	4213	0	0	0
T28	2706	6	0	0
T41	776	0	0	0
T134	5098	0	0	0
T135	0	17	0	0
T183	2793	43	0	0
T185	0	7	0	0
T189	1012	0	0	0
T190	0	6	0	0
T193	1783	14	0	0
T194	2836	28	0	0
T195	0	20	0	0
T196	0	32	0	0
T197	0	6	0	0
T198	1647	0	0	0
T199	1362	0	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211018839	60848	0	0
T27	4213	0	0	0
T28	2706	9	0	0
T41	776	0	0	0
T134	5098	0	0	0
T135	0	4	0	0
T183	2793	31	0	0
T185	0	16	0	0
T189	1012	0	0	0
T190	0	28	0	0
T193	1783	25	0	0
T194	2836	17	0	0
T195	0	6	0	0
T196	0	42	0	0
T197	0	12	0	0
T198	1647	0	0	0
T199	1362	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211018839	54077	0	0
T27	4213	0	0	0
T28	2706	8	0	0
T41	776	0	0	0
T134	5098	0	0	0
T183	2793	25	0	0
T185	0	22	0	0
T189	1012	0	0	0
T193	1783	23	0	0
T194	2836	23	0	0
T195	0	25	0	0
T196	0	29	0	0
T197	0	6	0	0
T198	1647	0	0	0
T199	1362	0	0	0
T200	0	14	0	0
T201	0	2	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211018839	54222	0	0
T27	4213	0	0	0
T28	2706	3	0	0
T41	776	0	0	0
T134	5098	0	0	0
T183	2793	44	0	0
T185	0	34	0	0
T189	1012	0	0	0
T190	0	15	0	0
T193	1783	11	0	0
T194	2836	28	0	0
T195	0	8	0	0
T196	0	81	0	0
T197	0	20	0	0
T198	1647	0	0	0
T199	1362	0	0	0
T200	0	8	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211018839	59513	0	0
T26	4153	31	0	0
T27	4213	31	0	0
T28	0	26	0	0
T40	919	8	0	0
T41	776	0	0	0
T114	1265	3	0	0
T135	0	6	0	0
T183	2793	24	0	0
T190	0	14	0	0
T193	1783	19	0	0
T194	2836	11	0	0
T198	1647	0	0	0
T199	1362	0	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211018839	61927	0	0
T26	4153	35	0	0
T27	4213	18	0	0
T28	2706	27	0	0
T41	776	0	0	0
T114	1265	1	0	0
T135	0	12	0	0
T183	2793	55	0	0
T190	0	22	0	0
T193	1783	17	0	0
T194	2836	41	0	0
T195	0	4	0	0
T198	1647	0	0	0
T199	1362	0	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	211018839	62137	0	0
T26	4153	18	0	0
T27	4213	23	0	0
T28	2706	10	0	0
T41	776	0	0	0
T114	1265	2	0	0
T135	0	27	0	0
T183	2793	51	0	0
T185	0	12	0	0
T190	0	15	0	0
T193	1783	37	0	0
T194	2836	32	0	0
T198	1647	0	0	0
T199	1362	0	0	0