Unified Coverage Report :: Module :: edn

Module : edn

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	94.44		83.33	100.00			100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.68	99.02	92.46	96.79	93.42	98.62	99.77

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
edn_csr_assert	100.00						100.00
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_edn_core	92.02	99.92	89.78	70.79	93.42	99.29	98.91
u_edn_cov_if	25.00	50.00	0.00
u_reg	98.63	96.98	98.92	100.00		97.26	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Cond Coverage for Module : edn

	Total	Covered	Percent
Conditions	6	5	83.33
Logical	6	5	83.33
Non-Logical	0	0
Event	0	0

 LINE       99
 EXPRESSION (alert[0] || intg_err_alert[0])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T17,T18,T19

 LINE       99
 EXPRESSION (alert[1] || intg_err_alert[1])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T15,T23,T24
1	0	Covered	T4,T5,T25

---

Toggle Coverage for Module : edn

	Total	Covered	Percent
Totals	69	69	100.00
Total Bits	1168	1168	100.00
Total Bits 0->1	584	584	100.00
Total Bits 1->0	584	584	100.00

Ports	69	69	100.00
Port Bits	1168	1168	100.00
Port Bits 0->1	584	584	100.00
Port Bits 1->0	584	584	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T4,T5,T6	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T2,T3,T20	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T21	Yes	T1,T2,T21	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T17	Yes	T1,T2,T3	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T26,T27,T28	Yes	T26,T27,T28	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T2,T3,T17	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i[0].edn_req	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
edn_i[1].edn_req	Yes	Yes	T3,T22,T29	Yes	T3,T22,T29	INPUT
edn_i[2].edn_req	Yes	Yes	T22,T29,T30	Yes	T22,T29,T30	INPUT
edn_i[3].edn_req	Yes	Yes	T1,T17,T29	Yes	T1,T17,T29	INPUT
edn_i[4].edn_req	Yes	Yes	T1,T22,T30	Yes	T1,T22,T30	INPUT
edn_i[5].edn_req	Yes	Yes	T1,T22,T30	Yes	T1,T22,T30	INPUT
edn_i[6].edn_req	Yes	Yes	T1,T18,T31	Yes	T1,T18,T31	INPUT
edn_o[0].edn_bus[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_o[0].edn_fips	Yes	Yes	T21,T5,T22	Yes	T1,T2,T3	OUTPUT
edn_o[0].edn_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_o[1].edn_bus[31:0]	Yes	Yes	T29,T30,T32	Yes	T3,T22,T29	OUTPUT
edn_o[1].edn_fips	Yes	Yes	T29,T33,T34	Yes	T3,T29,T32	OUTPUT
edn_o[1].edn_ack	Yes	Yes	T3,T22,T29	Yes	T3,T22,T29	OUTPUT
edn_o[2].edn_bus[31:0]	Yes	Yes	T22,T29,T30	Yes	T22,T29,T30	OUTPUT
edn_o[2].edn_fips	Yes	Yes	T29,T32,T35	Yes	T29,T19,T32	OUTPUT
edn_o[2].edn_ack	Yes	Yes	T22,T29,T30	Yes	T22,T29,T30	OUTPUT
edn_o[3].edn_bus[31:0]	Yes	Yes	T1,T17,T29	Yes	T1,T17,T29	OUTPUT
edn_o[3].edn_fips	Yes	Yes	T1,T30,T36	Yes	T1,T17,T29	OUTPUT
edn_o[3].edn_ack	Yes	Yes	T1,T17,T29	Yes	T1,T17,T29	OUTPUT
edn_o[4].edn_bus[31:0]	Yes	Yes	T1,T22,T30	Yes	T1,T22,T30	OUTPUT
edn_o[4].edn_fips	Yes	Yes	T1,T22,T31	Yes	T1,T22,T31	OUTPUT
edn_o[4].edn_ack	Yes	Yes	T1,T22,T30	Yes	T1,T22,T30	OUTPUT
edn_o[5].edn_bus[31:0]	Yes	Yes	T1,T22,T30	Yes	T1,T22,T30	OUTPUT
edn_o[5].edn_fips	Yes	Yes	T32,T37,T38	Yes	T22,T31,T32	OUTPUT
edn_o[5].edn_ack	Yes	Yes	T1,T22,T30	Yes	T1,T22,T30	OUTPUT
edn_o[6].edn_bus[31:0]	Yes	Yes	T1,T18,T31	Yes	T1,T18,T31	OUTPUT
edn_o[6].edn_fips	Yes	Yes	T39,T32,T10	Yes	T1,T31,T39	OUTPUT
edn_o[6].edn_ack	Yes	Yes	T1,T18,T31	Yes	T1,T18,T31	OUTPUT
csrng_cmd_o.genbits_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_i.genbits_bus[127:0]	Yes	Yes	T1,T22,T6	Yes	T1,T22,T29	INPUT
csrng_cmd_i.genbits_fips	Yes	Yes	T1,T21,T22	Yes	T1,T22,T6	INPUT
csrng_cmd_i.genbits_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_rsp_sts	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_rsp_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_req_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T17,T18,T26	Yes	T17,T18,T26	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T4,T5,T26	Yes	T4,T5,T26	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T17,T18,T26	Yes	T17,T18,T26	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T4,T5,T26	Yes	T4,T5,T26	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T6,T40,T41	Yes	T6,T40,T41	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T6,T40,T42	Yes	T6,T40,T42	OUTPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Module : edn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	43	43	100.00	43	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	43	43	100.00	43	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnownO_A	210531341	210393452	0	0
CsrngAppIfOut_A	210531341	210393452	0	0
FpvSecCmCntAlertCheck_A	210531341	102	0	0
FpvSecCmMainFsmCheck_A	210531341	60	0	0
FpvSecCmRegWeOnehotCheck_A	210531341	60	0	0
IntrEdnCmdReqDoneKnownO_A	210531341	210393452	0	0
TlAReadyKnownO_A	210531341	210393452	0	0
TlDValidKnownO_A	210531341	210393452	0	0
gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A	210531341	60	0	0
gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A	210531341	60	0	0
gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A	210531341	60	0	0
gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A	210531341	60	0	0
gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A	210531341	60	0	0
gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A	210531341	60	0	0
gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A	210531341	60	0	0
gen_edn_if_asserts[0].EdnDataStableDisable_A	210531341	474479	0	0
gen_edn_if_asserts[0].EdnDataStable_A	210531341	23867	0	335
gen_edn_if_asserts[0].EdnEndPointOut_A	210531341	210393452	0	0
gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A	210531341	124807	0	0
gen_edn_if_asserts[1].EdnDataStableDisable_A	210531341	474479	0	0
gen_edn_if_asserts[1].EdnDataStable_A	210531341	3129	0	113
gen_edn_if_asserts[1].EdnEndPointOut_A	210531341	210393452	0	0
gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A	210531341	124807	0	0
gen_edn_if_asserts[2].EdnDataStableDisable_A	210531341	474479	0	0
gen_edn_if_asserts[2].EdnDataStable_A	210531341	2685	0	105
gen_edn_if_asserts[2].EdnEndPointOut_A	210531341	210393452	0	0
gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A	210531341	124807	0	0
gen_edn_if_asserts[3].EdnDataStableDisable_A	210531341	474479	0	0
gen_edn_if_asserts[3].EdnDataStable_A	210531341	3930	0	100
gen_edn_if_asserts[3].EdnEndPointOut_A	210531341	210393452	0	0
gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A	210531341	124807	0	0
gen_edn_if_asserts[4].EdnDataStableDisable_A	210531341	474479	0	0
gen_edn_if_asserts[4].EdnDataStable_A	210531341	4864	0	103
gen_edn_if_asserts[4].EdnEndPointOut_A	210531341	210393452	0	0
gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A	210531341	124807	0	0
gen_edn_if_asserts[5].EdnDataStableDisable_A	210531341	474479	0	0
gen_edn_if_asserts[5].EdnDataStable_A	210531341	1973	0	92
gen_edn_if_asserts[5].EdnEndPointOut_A	210531341	210393452	0	0
gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A	210531341	124807	0	0
gen_edn_if_asserts[6].EdnDataStableDisable_A	210531341	474479	0	0
gen_edn_if_asserts[6].EdnDataStable_A	210531341	2508	0	84
gen_edn_if_asserts[6].EdnEndPointOut_A	210531341	210393452	0	0
gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A	210531341	124807	0	0

AlertTxKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210531341	210393452	0	0
T1	2424	2364	0	0
T2	1804	1707	0	0
T3	1369	1282	0	0
T4	769	635	0	0
T5	1924	1758	0	0
T17	1459	1360	0	0
T18	1543	1488	0	0
T20	1241	1165	0	0
T21	1044	967	0	0
T22	2135	2053	0	0

CsrngAppIfOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210531341	210393452	0	0
T1	2424	2364	0	0
T2	1804	1707	0	0
T3	1369	1282	0	0
T4	769	635	0	0
T5	1924	1758	0	0
T17	1459	1360	0	0
T18	1543	1488	0	0
T20	1241	1165	0	0
T21	1044	967	0	0
T22	2135	2053	0	0

FpvSecCmCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210531341	102	0	0
T10	2007	0	0	0
T14	1093	1	0	0
T15	0	20	0	0
T16	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	597	0	0	0
T51	1285	0	0	0
T52	6032	0	0	0
T53	984	0	0	0
T54	1426	0	0	0
T55	1759	0	0	0
T56	1171	0	0	0
T57	1277	0	0	0

FpvSecCmMainFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210531341	60	0	0
T15	34355	20	0	0
T16	1306	0	0	0
T23	0	10	0	0
T24	0	10	0	0
T58	0	10	0	0
T59	0	10	0	0
T60	2736	0	0	0
T61	1227	0	0	0
T62	1101	0	0	0
T63	1274	0	0	0
T64	1065	0	0	0
T65	1327	0	0	0
T66	1403	0	0	0
T67	2164	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210531341	60	0	0
T15	34355	20	0	0
T16	1306	0	0	0
T23	0	10	0	0
T24	0	10	0	0
T58	0	10	0	0
T59	0	10	0	0
T60	2736	0	0	0
T61	1227	0	0	0
T62	1101	0	0	0
T63	1274	0	0	0
T64	1065	0	0	0
T65	1327	0	0	0
T66	1403	0	0	0
T67	2164	0	0	0

IntrEdnCmdReqDoneKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210531341	210393452	0	0
T1	2424	2364	0	0
T2	1804	1707	0	0
T3	1369	1282	0	0
T4	769	635	0	0
T5	1924	1758	0	0
T17	1459	1360	0	0
T18	1543	1488	0	0
T20	1241	1165	0	0
T21	1044	967	0	0
T22	2135	2053	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210531341	210393452	0	0
T1	2424	2364	0	0
T2	1804	1707	0	0
T3	1369	1282	0	0
T4	769	635	0	0
T5	1924	1758	0	0
T17	1459	1360	0	0
T18	1543	1488	0	0
T20	1241	1165	0	0
T21	1044	967	0	0
T22	2135	2053	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210531341	210393452	0	0
T1	2424	2364	0	0
T2	1804	1707	0	0
T3	1369	1282	0	0
T4	769	635	0	0
T5	1924	1758	0	0
T17	1459	1360	0	0
T18	1543	1488	0	0
T20	1241	1165	0	0
T21	1044	967	0	0
T22	2135	2053	0	0

gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210531341	60	0	0
T15	34355	20	0	0
T16	1306	0	0	0
T23	0	10	0	0
T24	0	10	0	0
T58	0	10	0	0
T59	0	10	0	0
T60	2736	0	0	0
T61	1227	0	0	0
T62	1101	0	0	0
T63	1274	0	0	0
T64	1065	0	0	0
T65	1327	0	0	0
T66	1403	0	0	0
T67	2164	0	0	0

gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210531341	60	0	0
T15	34355	20	0	0
T16	1306	0	0	0
T23	0	10	0	0
T24	0	10	0	0
T58	0	10	0	0
T59	0	10	0	0
T60	2736	0	0	0
T61	1227	0	0	0
T62	1101	0	0	0
T63	1274	0	0	0
T64	1065	0	0	0
T65	1327	0	0	0
T66	1403	0	0	0
T67	2164	0	0	0

gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210531341	60	0	0
T15	34355	20	0	0
T16	1306	0	0	0
T23	0	10	0	0
T24	0	10	0	0
T58	0	10	0	0
T59	0	10	0	0
T60	2736	0	0	0
T61	1227	0	0	0
T62	1101	0	0	0
T63	1274	0	0	0
T64	1065	0	0	0
T65	1327	0	0	0
T66	1403	0	0	0
T67	2164	0	0	0

gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210531341	60	0	0
T15	34355	20	0	0
T16	1306	0	0	0
T23	0	10	0	0
T24	0	10	0	0
T58	0	10	0	0
T59	0	10	0	0
T60	2736	0	0	0
T61	1227	0	0	0
T62	1101	0	0	0
T63	1274	0	0	0
T64	1065	0	0	0
T65	1327	0	0	0
T66	1403	0	0	0
T67	2164	0	0	0

gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210531341	60	0	0
T15	34355	20	0	0
T16	1306	0	0	0
T23	0	10	0	0
T24	0	10	0	0
T58	0	10	0	0
T59	0	10	0	0
T60	2736	0	0	0
T61	1227	0	0	0
T62	1101	0	0	0
T63	1274	0	0	0
T64	1065	0	0	0
T65	1327	0	0	0
T66	1403	0	0	0
T67	2164	0	0	0

gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210531341	60	0	0
T15	34355	20	0	0
T16	1306	0	0	0
T23	0	10	0	0
T24	0	10	0	0
T58	0	10	0	0
T59	0	10	0	0
T60	2736	0	0	0
T61	1227	0	0	0
T62	1101	0	0	0
T63	1274	0	0	0
T64	1065	0	0	0
T65	1327	0	0	0
T66	1403	0	0	0
T67	2164	0	0	0

gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210531341	60	0	0
T15	34355	20	0	0
T16	1306	0	0	0
T23	0	10	0	0
T24	0	10	0	0
T58	0	10	0	0
T59	0	10	0	0
T60	2736	0	0	0
T61	1227	0	0	0
T62	1101	0	0	0
T63	1274	0	0	0
T64	1065	0	0	0
T65	1327	0	0	0
T66	1403	0	0	0
T67	2164	0	0	0

gen_edn_if_asserts[0].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210531341	474479	0	0
T1	2424	71	0	0
T2	1804	24	0	0
T3	1369	18	0	0
T4	769	396	0	0
T5	1924	1093	0	0
T17	1459	21	0	0
T18	1543	127	0	0
T20	1241	51	0	0
T21	1044	102	0	0
T22	2135	13	0	0

gen_edn_if_asserts[0].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210531341	23867	0	335
T1	2424	20	0	1
T2	1804	3	0	1
T3	1369	3	0	1
T4	769	0	0	0
T5	1924	0	0	0
T6	0	12	0	1
T9	0	15	0	1
T17	1459	0	0	0
T18	1543	0	0	0
T20	1241	3	0	1
T21	1044	3	0	0
T22	2135	43	0	1
T30	0	45	0	1
T68	0	3	0	1
T69	0	0	0	1

gen_edn_if_asserts[0].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210531341	210393452	0	0
T1	2424	2364	0	0
T2	1804	1707	0	0
T3	1369	1282	0	0
T4	769	635	0	0
T5	1924	1758	0	0
T17	1459	1360	0	0
T18	1543	1488	0	0
T20	1241	1165	0	0
T21	1044	967	0	0
T22	2135	2053	0	0

gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210531341	124807	0	0
T4	769	376	0	0
T5	1924	1112	0	0
T6	9940	0	0	0
T7	0	1112	0	0
T9	1628	0	0	0
T21	1044	0	0	0
T22	2135	0	0	0
T25	1876	1124	0	0
T29	1671	0	0	0
T30	1295	0	0	0
T31	1077	0	0	0
T36	0	330	0	0
T39	0	7	0	0
T70	0	1166	0	0
T71	0	592	0	0
T72	0	600	0	0
T73	0	38	0	0

gen_edn_if_asserts[1].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210531341	474479	0	0
T1	2424	71	0	0
T2	1804	24	0	0
T3	1369	18	0	0
T4	769	396	0	0
T5	1924	1093	0	0
T17	1459	21	0	0
T18	1543	127	0	0
T20	1241	51	0	0
T21	1044	102	0	0
T22	2135	13	0	0

gen_edn_if_asserts[1].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210531341	3129	0	113
T3	1369	3	0	1
T4	769	0	0	0
T5	1924	0	0	0
T6	9940	0	0	0
T17	1459	0	0	0
T18	1543	0	0	0
T20	1241	0	0	0
T21	1044	0	0	0
T22	2135	3	0	1
T29	1671	42	0	1
T30	0	3	0	1
T32	0	3	0	1
T33	0	58	0	1
T34	0	40	0	1
T37	0	47	0	1
T74	0	19	0	1
T75	0	45	0	1

gen_edn_if_asserts[1].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210531341	210393452	0	0
T1	2424	2364	0	0
T2	1804	1707	0	0
T3	1369	1282	0	0
T4	769	635	0	0
T5	1924	1758	0	0
T17	1459	1360	0	0
T18	1543	1488	0	0
T20	1241	1165	0	0
T21	1044	967	0	0
T22	2135	2053	0	0

gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210531341	124807	0	0
T4	769	376	0	0
T5	1924	1112	0	0
T6	9940	0	0	0
T7	0	1112	0	0
T9	1628	0	0	0
T21	1044	0	0	0
T22	2135	0	0	0
T25	1876	1124	0	0
T29	1671	0	0	0
T30	1295	0	0	0
T31	1077	0	0	0
T36	0	330	0	0
T39	0	7	0	0
T70	0	1166	0	0
T71	0	592	0	0
T72	0	600	0	0
T73	0	38	0	0

gen_edn_if_asserts[2].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210531341	474479	0	0
T1	2424	71	0	0
T2	1804	24	0	0
T3	1369	18	0	0
T4	769	396	0	0
T5	1924	1093	0	0
T17	1459	21	0	0
T18	1543	127	0	0
T20	1241	51	0	0
T21	1044	102	0	0
T22	2135	13	0	0

gen_edn_if_asserts[2].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210531341	2685	0	105
T6	9940	0	0	0
T9	1628	0	0	0
T19	1570	4	0	1
T22	2135	3	0	1
T29	1671	29	0	1
T30	1295	3	0	1
T32	0	9	0	1
T34	0	3	0	1
T35	0	17	0	1
T50	0	0	0	1
T69	1239	0	0	0
T74	0	3	0	1
T75	0	0	0	1
T76	0	3	0	0
T77	0	3	0	0
T78	1212	0	0	0
T79	293193	0	0	0
T80	595512	0	0	0

gen_edn_if_asserts[2].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210531341	210393452	0	0
T1	2424	2364	0	0
T2	1804	1707	0	0
T3	1369	1282	0	0
T4	769	635	0	0
T5	1924	1758	0	0
T17	1459	1360	0	0
T18	1543	1488	0	0
T20	1241	1165	0	0
T21	1044	967	0	0
T22	2135	2053	0	0

gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210531341	124807	0	0
T4	769	376	0	0
T5	1924	1112	0	0
T6	9940	0	0	0
T7	0	1112	0	0
T9	1628	0	0	0
T21	1044	0	0	0
T22	2135	0	0	0
T25	1876	1124	0	0
T29	1671	0	0	0
T30	1295	0	0	0
T31	1077	0	0	0
T36	0	330	0	0
T39	0	7	0	0
T70	0	1166	0	0
T71	0	592	0	0
T72	0	600	0	0
T73	0	38	0	0

gen_edn_if_asserts[3].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210531341	474479	0	0
T1	2424	71	0	0
T2	1804	24	0	0
T3	1369	18	0	0
T4	769	396	0	0
T5	1924	1093	0	0
T17	1459	21	0	0
T18	1543	127	0	0
T20	1241	51	0	0
T21	1044	102	0	0
T22	2135	13	0	0

gen_edn_if_asserts[3].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210531341	3930	0	100
T1	2424	51	0	1
T2	1804	0	0	0
T3	1369	0	0	0
T4	769	0	0	0
T5	1924	0	0	0
T13	0	15	0	1
T17	1459	4	0	1
T18	1543	0	0	0
T20	1241	0	0	0
T21	1044	0	0	0
T22	2135	0	0	0
T29	0	7	0	1
T30	0	21	0	1
T32	0	9	0	1
T34	0	3	0	1
T54	0	0	0	1
T74	0	55	0	1
T81	0	3	0	0
T82	0	3	0	0
T83	0	0	0	1

gen_edn_if_asserts[3].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210531341	210393452	0	0
T1	2424	2364	0	0
T2	1804	1707	0	0
T3	1369	1282	0	0
T4	769	635	0	0
T5	1924	1758	0	0
T17	1459	1360	0	0
T18	1543	1488	0	0
T20	1241	1165	0	0
T21	1044	967	0	0
T22	2135	2053	0	0

gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210531341	124807	0	0
T4	769	376	0	0
T5	1924	1112	0	0
T6	9940	0	0	0
T7	0	1112	0	0
T9	1628	0	0	0
T21	1044	0	0	0
T22	2135	0	0	0
T25	1876	1124	0	0
T29	1671	0	0	0
T30	1295	0	0	0
T31	1077	0	0	0
T36	0	330	0	0
T39	0	7	0	0
T70	0	1166	0	0
T71	0	592	0	0
T72	0	600	0	0
T73	0	38	0	0

gen_edn_if_asserts[4].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210531341	474479	0	0
T1	2424	71	0	0
T2	1804	24	0	0
T3	1369	18	0	0
T4	769	396	0	0
T5	1924	1093	0	0
T17	1459	21	0	0
T18	1543	127	0	0
T20	1241	51	0	0
T21	1044	102	0	0
T22	2135	13	0	0

gen_edn_if_asserts[4].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210531341	4864	0	103
T1	2424	52	0	1
T2	1804	0	0	0
T3	1369	0	0	0
T4	769	0	0	0
T5	1924	0	0	0
T10	0	0	0	1
T17	1459	0	0	0
T18	1543	0	0	0
T20	1241	0	0	0
T21	1044	0	0	0
T22	2135	43	0	1
T30	0	3	0	1
T31	0	8	0	1
T32	0	3	0	1
T35	0	19	0	1
T37	0	543	0	1
T84	0	3	0	0
T85	0	4	0	1
T86	0	3	0	1

gen_edn_if_asserts[4].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210531341	210393452	0	0
T1	2424	2364	0	0
T2	1804	1707	0	0
T3	1369	1282	0	0
T4	769	635	0	0
T5	1924	1758	0	0
T17	1459	1360	0	0
T18	1543	1488	0	0
T20	1241	1165	0	0
T21	1044	967	0	0
T22	2135	2053	0	0

gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210531341	124807	0	0
T4	769	376	0	0
T5	1924	1112	0	0
T6	9940	0	0	0
T7	0	1112	0	0
T9	1628	0	0	0
T21	1044	0	0	0
T22	2135	0	0	0
T25	1876	1124	0	0
T29	1671	0	0	0
T30	1295	0	0	0
T31	1077	0	0	0
T36	0	330	0	0
T39	0	7	0	0
T70	0	1166	0	0
T71	0	592	0	0
T72	0	600	0	0
T73	0	38	0	0

gen_edn_if_asserts[5].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210531341	474479	0	0
T1	2424	71	0	0
T2	1804	24	0	0
T3	1369	18	0	0
T4	769	396	0	0
T5	1924	1093	0	0
T17	1459	21	0	0
T18	1543	127	0	0
T20	1241	51	0	0
T21	1044	102	0	0
T22	2135	13	0	0

gen_edn_if_asserts[5].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210531341	1973	0	92
T1	2424	3	0	1
T2	1804	0	0	0
T3	1369	0	0	0
T4	769	0	0	0
T5	1924	0	0	0
T10	0	10	0	1
T17	1459	0	0	0
T18	1543	0	0	0
T20	1241	0	0	0
T21	1044	0	0	0
T22	2135	3	0	1
T30	0	3	0	1
T31	0	3	0	1
T32	0	14	0	1
T37	0	56	0	1
T38	0	32	0	1
T86	0	3	0	1
T87	0	4	0	1

gen_edn_if_asserts[5].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210531341	210393452	0	0
T1	2424	2364	0	0
T2	1804	1707	0	0
T3	1369	1282	0	0
T4	769	635	0	0
T5	1924	1758	0	0
T17	1459	1360	0	0
T18	1543	1488	0	0
T20	1241	1165	0	0
T21	1044	967	0	0
T22	2135	2053	0	0

gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210531341	124807	0	0
T4	769	376	0	0
T5	1924	1112	0	0
T6	9940	0	0	0
T7	0	1112	0	0
T9	1628	0	0	0
T21	1044	0	0	0
T22	2135	0	0	0
T25	1876	1124	0	0
T29	1671	0	0	0
T30	1295	0	0	0
T31	1077	0	0	0
T36	0	330	0	0
T39	0	7	0	0
T70	0	1166	0	0
T71	0	592	0	0
T72	0	600	0	0
T73	0	38	0	0

gen_edn_if_asserts[6].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210531341	474479	0	0
T1	2424	71	0	0
T2	1804	24	0	0
T3	1369	18	0	0
T4	769	396	0	0
T5	1924	1093	0	0
T17	1459	21	0	0
T18	1543	127	0	0
T20	1241	51	0	0
T21	1044	102	0	0
T22	2135	13	0	0

gen_edn_if_asserts[6].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210531341	2508	0	84
T1	2424	15	0	1
T2	1804	0	0	0
T3	1369	0	0	0
T4	769	0	0	0
T5	1924	0	0	0
T10	0	7	0	1
T17	1459	0	0	0
T18	1543	4	0	1
T20	1241	0	0	0
T21	1044	0	0	0
T22	2135	0	0	0
T31	0	3	0	1
T32	0	27	0	1
T33	0	3	0	1
T34	0	3	0	1
T38	0	3	0	1
T74	0	3	0	1
T86	0	3	0	1

gen_edn_if_asserts[6].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210531341	210393452	0	0
T1	2424	2364	0	0
T2	1804	1707	0	0
T3	1369	1282	0	0
T4	769	635	0	0
T5	1924	1758	0	0
T17	1459	1360	0	0
T18	1543	1488	0	0
T20	1241	1165	0	0
T21	1044	967	0	0
T22	2135	2053	0	0

gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	210531341	124807	0	0
T4	769	376	0	0
T5	1924	1112	0	0
T6	9940	0	0	0
T7	0	1112	0	0
T9	1628	0	0	0
T21	1044	0	0	0
T22	2135	0	0	0
T25	1876	1124	0	0
T29	1671	0	0	0
T30	1295	0	0	0
T31	1077	0	0	0
T36	0	330	0	0
T39	0	7	0	0
T70	0	1166	0	0
T71	0	592	0	0
T72	0	600	0	0
T73	0	38	0	0