Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44		83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	207368427	9763082	0	0
boot_gen_cmd_rd_A	207368427	45690	0	0
boot_ins_cmd_rd_A	207368427	52122	0	0
ctrl_rd_A	207368427	45982	0	0
err_code_test_rd_A	207368427	46533	0	0
intr_enable_rd_A	207368427	51894	0	0
max_num_reqs_between_reseeds_rd_A	207368427	54175	0	0
regwen_rd_A	207368427	54404	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207368427	9763082	0	0
T17	1963	0	0	0
T22	583039	249356	0	0
T23	1038	0	0	0
T24	1201	0	0	0
T25	1156	0	0	0
T29	1981	181	0	0
T30	4066	1158	0	0
T171	4935	7	0	0
T172	6113	7	0	0
T173	5757	8	0	0
T174	0	234	0	0
T175	0	6	0	0
T176	0	3	0	0
T177	0	107	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207368427	45690	0	0
T43	2859	27	0	0
T178	1802	10	0	0
T179	1919	24	0	0
T180	3630	63	0	0
T181	0	5	0	0
T182	0	8	0	0
T183	0	25	0	0
T184	0	8	0	0
T185	0	55	0	0
T186	0	7	0	0
T187	1573	0	0	0
T188	1885	0	0	0
T189	3262	0	0	0
T190	735	0	0	0
T191	799	0	0	0
T192	2217	0	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207368427	52122	0	0
T43	2859	24	0	0
T178	1802	8	0	0
T179	1919	21	0	0
T180	3630	83	0	0
T181	0	4	0	0
T182	0	3	0	0
T183	0	37	0	0
T185	0	11	0	0
T186	0	12	0	0
T187	1573	0	0	0
T188	1885	0	0	0
T189	3262	0	0	0
T190	735	0	0	0
T191	799	0	0	0
T192	2217	27	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207368427	45982	0	0
T43	2859	26	0	0
T46	933	0	0	0
T176	4984	2	0	0
T177	1372	0	0	0
T178	1802	2	0	0
T179	1919	17	0	0
T180	3630	59	0	0
T181	0	7	0	0
T182	0	6	0	0
T183	0	33	0	0
T185	0	60	0	0
T187	1573	0	0	0
T188	1885	0	0	0
T192	0	16	0	0
T193	822	0	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207368427	46533	0	0
T43	2859	30	0	0
T178	1802	7	0	0
T179	1919	10	0	0
T180	3630	31	0	0
T181	0	7	0	0
T182	0	8	0	0
T183	0	51	0	0
T185	0	19	0	0
T186	0	6	0	0
T187	1573	0	0	0
T188	1885	0	0	0
T189	3262	0	0	0
T190	735	0	0	0
T191	799	0	0	0
T192	2217	33	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207368427	51894	0	0
T43	2859	2	0	0
T46	933	0	0	0
T175	4447	28	0	0
T176	4984	43	0	0
T177	1372	0	0	0
T178	1802	11	0	0
T179	0	15	0	0
T180	0	98	0	0
T181	0	6	0	0
T187	1573	0	0	0
T188	1885	32	0	0
T193	822	0	0	0
T194	1466	6	0	0
T195	0	17	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207368427	54175	0	0
T43	2859	36	0	0
T46	933	0	0	0
T175	4447	13	0	0
T176	4984	11	0	0
T177	1372	0	0	0
T178	1802	14	0	0
T179	1919	24	0	0
T180	0	42	0	0
T181	0	24	0	0
T183	0	32	0	0
T187	1573	0	0	0
T188	1885	0	0	0
T192	0	8	0	0
T193	822	0	0	0
T196	0	477	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207368427	54404	0	0
T43	2859	43	0	0
T46	933	0	0	0
T175	4447	18	0	0
T176	4984	13	0	0
T177	1372	0	0	0
T178	1802	3	0	0
T179	1919	50	0	0
T180	0	36	0	0
T181	0	9	0	0
T183	0	32	0	0
T187	1573	0	0	0
T188	1885	0	0	0
T192	0	24	0	0
T193	822	0	0	0
T196	0	432	0	0