Unified Coverage Report :: Module :: edn

Module : edn

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	94.44		83.33	100.00			100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.45	99.02	92.39	96.79	92.11	98.62	99.77

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
edn_csr_assert	100.00						100.00
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_edn_core	91.78	99.92	89.68	70.79	92.11	99.29	98.91
u_edn_cov_if	25.00	50.00	0.00
u_reg	98.63	96.98	98.92	100.00		97.26	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Cond Coverage for Module : edn

	Total	Covered	Percent
Conditions	6	5	83.33
Logical	6	5	83.33
Non-Logical	0	0
Event	0	0

 LINE       99
 EXPRESSION (alert[0] || intg_err_alert[0])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T17,T18,T19

 LINE       99
 EXPRESSION (alert[1] || intg_err_alert[1])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T26,T27,T28
1	0	Covered	T2,T3,T4

---

Toggle Coverage for Module : edn

	Total	Covered	Percent
Totals	69	69	100.00
Total Bits	1168	1168	100.00
Total Bits 0->1	584	584	100.00
Total Bits 1->0	584	584	100.00

Ports	69	69	100.00
Port Bits	1168	1168	100.00
Port Bits 0->1	584	584	100.00
Port Bits 1->0	584	584	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T22,T17	Yes	T1,T22,T17	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T4	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T4,T21	Yes	T1,T2,T4	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T20	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T22,T29,T30	Yes	T22,T29,T30	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i[0].edn_req	Yes	Yes	T1,T3,T21	Yes	T1,T3,T21	INPUT
edn_i[1].edn_req	Yes	Yes	T31,T14,T32	Yes	T31,T14,T32	INPUT
edn_i[2].edn_req	Yes	Yes	T20,T24,T33	Yes	T20,T24,T33	INPUT
edn_i[3].edn_req	Yes	Yes	T2,T33,T34	Yes	T2,T33,T34	INPUT
edn_i[4].edn_req	Yes	Yes	T4,T17,T31	Yes	T4,T17,T31	INPUT
edn_i[5].edn_req	Yes	Yes	T31,T9,T13	Yes	T31,T9,T13	INPUT
edn_i[6].edn_req	Yes	Yes	T33,T31,T9	Yes	T33,T31,T9	INPUT
edn_o[0].edn_bus[31:0]	Yes	Yes	T1,T3,T21	Yes	T1,T3,T21	OUTPUT
edn_o[0].edn_fips	Yes	Yes	T21,T22,T23	Yes	T21,T22,T23	OUTPUT
edn_o[0].edn_ack	Yes	Yes	T1,T3,T21	Yes	T1,T3,T21	OUTPUT
edn_o[1].edn_bus[31:0]	Yes	Yes	T31,T32,T35	Yes	T31,T32,T35	OUTPUT
edn_o[1].edn_fips	Yes	Yes	T31,T35,T36	Yes	T31,T35,T36	OUTPUT
edn_o[1].edn_ack	Yes	Yes	T31,T32,T35	Yes	T31,T32,T35	OUTPUT
edn_o[2].edn_bus[31:0]	Yes	Yes	T24,T33,T31	Yes	T24,T33,T31	OUTPUT
edn_o[2].edn_fips	Yes	Yes	T9,T32,T36	Yes	T24,T33,T9	OUTPUT
edn_o[2].edn_ack	Yes	Yes	T20,T24,T33	Yes	T20,T24,T33	OUTPUT
edn_o[3].edn_bus[31:0]	Yes	Yes	T33,T37,T36	Yes	T33,T37,T36	OUTPUT
edn_o[3].edn_fips	Yes	Yes	T33,T37,T36	Yes	T33,T37,T36	OUTPUT
edn_o[3].edn_ack	Yes	Yes	T2,T33,T34	Yes	T2,T33,T34	OUTPUT
edn_o[4].edn_bus[31:0]	Yes	Yes	T17,T31,T9	Yes	T17,T31,T9	OUTPUT
edn_o[4].edn_fips	Yes	Yes	T31,T9,T38	Yes	T31,T9,T36	OUTPUT
edn_o[4].edn_ack	Yes	Yes	T17,T31,T9	Yes	T17,T31,T9	OUTPUT
edn_o[5].edn_bus[31:0]	Yes	Yes	T31,T36,T39	Yes	T31,T9,T36	OUTPUT
edn_o[5].edn_fips	Yes	Yes	T31,T36,T39	Yes	T31,T9,T36	OUTPUT
edn_o[5].edn_ack	Yes	Yes	T31,T9,T13	Yes	T31,T9,T13	OUTPUT
edn_o[6].edn_bus[31:0]	Yes	Yes	T33,T31,T9	Yes	T33,T31,T9	OUTPUT
edn_o[6].edn_fips	Yes	Yes	T10,T40,T41	Yes	T9,T42,T36	OUTPUT
edn_o[6].edn_ack	Yes	Yes	T33,T31,T9	Yes	T33,T31,T9	OUTPUT
csrng_cmd_o.genbits_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_i.genbits_bus[127:0]	Yes	Yes	T21,T22,T23	Yes	T21,T22,T23	INPUT
csrng_cmd_i.genbits_fips	Yes	Yes	T21,T22,T23	Yes	T21,T22,T23	INPUT
csrng_cmd_i.genbits_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_rsp_sts	Yes	Yes	T3,T20,T4	Yes	T3,T20,T4	INPUT
csrng_cmd_i.csrng_rsp_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_req_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T17,T43,T44	Yes	T17,T43,T44	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T17,T43,T44	Yes	T17,T43,T44	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T22,T45,T46	Yes	T22,T45,T46	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	OUTPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Module : edn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	43	43	100.00	43	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	43	43	100.00	43	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnownO_A	206834390	206687791	0	0
CsrngAppIfOut_A	206834390	206687791	0	0
FpvSecCmCntAlertCheck_A	206834390	110	0	0
FpvSecCmMainFsmCheck_A	206834390	70	0	0
FpvSecCmRegWeOnehotCheck_A	206834390	70	0	0
IntrEdnCmdReqDoneKnownO_A	206834390	206687791	0	0
TlAReadyKnownO_A	206834390	206687791	0	0
TlDValidKnownO_A	206834390	206687791	0	0
gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A	206834390	70	0	0
gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A	206834390	70	0	0
gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A	206834390	70	0	0
gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A	206834390	70	0	0
gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A	206834390	70	0	0
gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A	206834390	70	0	0
gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A	206834390	70	0	0
gen_edn_if_asserts[0].EdnDataStableDisable_A	206834390	568311	0	0
gen_edn_if_asserts[0].EdnDataStable_A	206834390	19237	0	350
gen_edn_if_asserts[0].EdnEndPointOut_A	206834390	206687791	0	0
gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A	206834390	123390	0	0
gen_edn_if_asserts[1].EdnDataStableDisable_A	206834390	568311	0	0
gen_edn_if_asserts[1].EdnDataStable_A	206834390	4372	0	124
gen_edn_if_asserts[1].EdnEndPointOut_A	206834390	206687791	0	0
gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A	206834390	123390	0	0
gen_edn_if_asserts[2].EdnDataStableDisable_A	206834390	568311	0	0
gen_edn_if_asserts[2].EdnDataStable_A	206834390	55646	0	129
gen_edn_if_asserts[2].EdnEndPointOut_A	206834390	206687791	0	0
gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A	206834390	123390	0	0
gen_edn_if_asserts[3].EdnDataStableDisable_A	206834390	568311	0	0
gen_edn_if_asserts[3].EdnDataStable_A	206834390	5744	0	91
gen_edn_if_asserts[3].EdnEndPointOut_A	206834390	206687791	0	0
gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A	206834390	123390	0	0
gen_edn_if_asserts[4].EdnDataStableDisable_A	206834390	568311	0	0
gen_edn_if_asserts[4].EdnDataStable_A	206834390	3312	0	105
gen_edn_if_asserts[4].EdnEndPointOut_A	206834390	206687791	0	0
gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A	206834390	123390	0	0
gen_edn_if_asserts[5].EdnDataStableDisable_A	206834390	568311	0	0
gen_edn_if_asserts[5].EdnDataStable_A	206834390	3103	0	87
gen_edn_if_asserts[5].EdnEndPointOut_A	206834390	206687791	0	0
gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A	206834390	123390	0	0
gen_edn_if_asserts[6].EdnDataStableDisable_A	206834390	568311	0	0
gen_edn_if_asserts[6].EdnDataStable_A	206834390	1316	0	79
gen_edn_if_asserts[6].EdnEndPointOut_A	206834390	206687791	0	0
gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A	206834390	123390	0	0

AlertTxKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206834390	206687791	0	0
T1	1104	1019	0	0
T2	869	726	0	0
T3	882	764	0	0
T4	883	733	0	0
T20	1110	1032	0	0
T21	1318	1237	0	0
T22	583039	583028	0	0
T23	1038	956	0	0
T24	1201	1111	0	0
T25	1156	1105	0	0

CsrngAppIfOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206834390	206687791	0	0
T1	1104	1019	0	0
T2	869	726	0	0
T3	882	764	0	0
T4	883	733	0	0
T20	1110	1032	0	0
T21	1318	1237	0	0
T22	583039	583028	0	0
T23	1038	956	0	0
T24	1201	1111	0	0
T25	1156	1105	0	0

FpvSecCmCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206834390	110	0	0
T9	2500	0	0	0
T13	1803	0	0	0
T14	614	1	0	0
T15	0	1	0	0
T16	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	1458	0	0	0
T55	945	0	0	0
T56	623	0	0	0
T57	1203	0	0	0
T58	13863	0	0	0
T59	1454	0	0	0
T60	1241	0	0	0

FpvSecCmMainFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206834390	70	0	0
T26	15396	10	0	0
T27	0	10	0	0
T28	0	20	0	0
T61	0	10	0	0
T62	0	20	0	0
T63	2909	0	0	0
T64	1149	0	0	0
T65	16408	0	0	0
T66	1992	0	0	0
T67	6630	0	0	0
T68	582043	0	0	0
T69	4674	0	0	0
T70	2265	0	0	0
T71	503255	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206834390	70	0	0
T26	15396	10	0	0
T27	0	10	0	0
T28	0	20	0	0
T61	0	10	0	0
T62	0	20	0	0
T63	2909	0	0	0
T64	1149	0	0	0
T65	16408	0	0	0
T66	1992	0	0	0
T67	6630	0	0	0
T68	582043	0	0	0
T69	4674	0	0	0
T70	2265	0	0	0
T71	503255	0	0	0

IntrEdnCmdReqDoneKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206834390	206687791	0	0
T1	1104	1019	0	0
T2	869	726	0	0
T3	882	764	0	0
T4	883	733	0	0
T20	1110	1032	0	0
T21	1318	1237	0	0
T22	583039	583028	0	0
T23	1038	956	0	0
T24	1201	1111	0	0
T25	1156	1105	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206834390	206687791	0	0
T1	1104	1019	0	0
T2	869	726	0	0
T3	882	764	0	0
T4	883	733	0	0
T20	1110	1032	0	0
T21	1318	1237	0	0
T22	583039	583028	0	0
T23	1038	956	0	0
T24	1201	1111	0	0
T25	1156	1105	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206834390	206687791	0	0
T1	1104	1019	0	0
T2	869	726	0	0
T3	882	764	0	0
T4	883	733	0	0
T20	1110	1032	0	0
T21	1318	1237	0	0
T22	583039	583028	0	0
T23	1038	956	0	0
T24	1201	1111	0	0
T25	1156	1105	0	0

gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206834390	70	0	0
T26	15396	10	0	0
T27	0	10	0	0
T28	0	20	0	0
T61	0	10	0	0
T62	0	20	0	0
T63	2909	0	0	0
T64	1149	0	0	0
T65	16408	0	0	0
T66	1992	0	0	0
T67	6630	0	0	0
T68	582043	0	0	0
T69	4674	0	0	0
T70	2265	0	0	0
T71	503255	0	0	0

gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206834390	70	0	0
T26	15396	10	0	0
T27	0	10	0	0
T28	0	20	0	0
T61	0	10	0	0
T62	0	20	0	0
T63	2909	0	0	0
T64	1149	0	0	0
T65	16408	0	0	0
T66	1992	0	0	0
T67	6630	0	0	0
T68	582043	0	0	0
T69	4674	0	0	0
T70	2265	0	0	0
T71	503255	0	0	0

gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206834390	70	0	0
T26	15396	10	0	0
T27	0	10	0	0
T28	0	20	0	0
T61	0	10	0	0
T62	0	20	0	0
T63	2909	0	0	0
T64	1149	0	0	0
T65	16408	0	0	0
T66	1992	0	0	0
T67	6630	0	0	0
T68	582043	0	0	0
T69	4674	0	0	0
T70	2265	0	0	0
T71	503255	0	0	0

gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206834390	70	0	0
T26	15396	10	0	0
T27	0	10	0	0
T28	0	20	0	0
T61	0	10	0	0
T62	0	20	0	0
T63	2909	0	0	0
T64	1149	0	0	0
T65	16408	0	0	0
T66	1992	0	0	0
T67	6630	0	0	0
T68	582043	0	0	0
T69	4674	0	0	0
T70	2265	0	0	0
T71	503255	0	0	0

gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206834390	70	0	0
T26	15396	10	0	0
T27	0	10	0	0
T28	0	20	0	0
T61	0	10	0	0
T62	0	20	0	0
T63	2909	0	0	0
T64	1149	0	0	0
T65	16408	0	0	0
T66	1992	0	0	0
T67	6630	0	0	0
T68	582043	0	0	0
T69	4674	0	0	0
T70	2265	0	0	0
T71	503255	0	0	0

gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206834390	70	0	0
T26	15396	10	0	0
T27	0	10	0	0
T28	0	20	0	0
T61	0	10	0	0
T62	0	20	0	0
T63	2909	0	0	0
T64	1149	0	0	0
T65	16408	0	0	0
T66	1992	0	0	0
T67	6630	0	0	0
T68	582043	0	0	0
T69	4674	0	0	0
T70	2265	0	0	0
T71	503255	0	0	0

gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206834390	70	0	0
T26	15396	10	0	0
T27	0	10	0	0
T28	0	20	0	0
T61	0	10	0	0
T62	0	20	0	0
T63	2909	0	0	0
T64	1149	0	0	0
T65	16408	0	0	0
T66	1992	0	0	0
T67	6630	0	0	0
T68	582043	0	0	0
T69	4674	0	0	0
T70	2265	0	0	0
T71	503255	0	0	0

gen_edn_if_asserts[0].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206834390	568311	0	0
T1	1104	17	0	0
T2	869	403	0	0
T3	882	415	0	0
T4	883	403	0	0
T20	1110	44	0	0
T21	1318	21	0	0
T22	583039	2467	0	0
T23	1038	38	0	0
T24	1201	48	0	0
T25	1156	63	0	0

gen_edn_if_asserts[0].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206834390	19237	0	350
T1	1104	3	0	1
T2	869	0	0	0
T3	882	0	0	0
T4	883	0	0	0
T8	0	188	0	1
T9	0	27	0	1
T20	1110	0	0	0
T21	1318	22	0	1
T22	583039	51	0	0
T23	1038	50	0	1
T24	1201	0	0	0
T25	1156	3	0	1
T31	0	46	0	1
T33	0	3	0	1
T55	0	0	0	1
T72	0	3	0	1

gen_edn_if_asserts[0].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206834390	206687791	0	0
T1	1104	1019	0	0
T2	869	726	0	0
T3	882	764	0	0
T4	883	733	0	0
T20	1110	1032	0	0
T21	1318	1237	0	0
T22	583039	583028	0	0
T23	1038	956	0	0
T24	1201	1111	0	0
T25	1156	1105	0	0

gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206834390	123390	0	0
T2	869	450	0	0
T3	882	31	0	0
T4	883	453	0	0
T5	0	627	0	0
T6	0	420	0	0
T14	0	324	0	0
T15	0	1114	0	0
T16	0	1147	0	0
T17	1963	0	0	0
T20	1110	0	0	0
T21	1318	0	0	0
T22	583039	0	0	0
T23	1038	0	0	0
T24	1201	0	0	0
T25	1156	0	0	0
T56	0	7	0	0
T73	0	376	0	0

gen_edn_if_asserts[1].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206834390	568311	0	0
T1	1104	17	0	0
T2	869	403	0	0
T3	882	415	0	0
T4	883	403	0	0
T20	1110	44	0	0
T21	1318	21	0	0
T22	583039	2467	0	0
T23	1038	38	0	0
T24	1201	48	0	0
T25	1156	63	0	0

gen_edn_if_asserts[1].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206834390	4372	0	124
T9	2500	0	0	0
T10	0	13	0	1
T13	1803	0	0	0
T14	614	0	0	0
T31	1878	23	0	1
T32	0	3	0	1
T35	0	31	0	1
T36	0	40	0	1
T38	0	3	0	1
T39	0	3	0	1
T54	1458	0	0	0
T55	945	0	0	0
T56	623	0	0	0
T57	1203	0	0	0
T58	13863	0	0	0
T59	1454	0	0	0
T74	0	591	0	1
T75	0	30	0	1
T76	0	57	0	1

gen_edn_if_asserts[1].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206834390	206687791	0	0
T1	1104	1019	0	0
T2	869	726	0	0
T3	882	764	0	0
T4	883	733	0	0
T20	1110	1032	0	0
T21	1318	1237	0	0
T22	583039	583028	0	0
T23	1038	956	0	0
T24	1201	1111	0	0
T25	1156	1105	0	0

gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206834390	123390	0	0
T2	869	450	0	0
T3	882	31	0	0
T4	883	453	0	0
T5	0	627	0	0
T6	0	420	0	0
T14	0	324	0	0
T15	0	1114	0	0
T16	0	1147	0	0
T17	1963	0	0	0
T20	1110	0	0	0
T21	1318	0	0	0
T22	583039	0	0	0
T23	1038	0	0	0
T24	1201	0	0	0
T25	1156	0	0	0
T56	0	7	0	0
T73	0	376	0	0

gen_edn_if_asserts[2].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206834390	568311	0	0
T1	1104	17	0	0
T2	869	403	0	0
T3	882	415	0	0
T4	883	403	0	0
T20	1110	44	0	0
T21	1318	21	0	0
T22	583039	2467	0	0
T23	1038	38	0	0
T24	1201	48	0	0
T25	1156	63	0	0

gen_edn_if_asserts[2].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206834390	55646	0	129
T4	883	0	0	0
T5	1481	0	0	0
T9	0	63	0	1
T17	1963	0	0	0
T20	1110	3	0	1
T21	1318	0	0	0
T22	583039	0	0	0
T23	1038	0	0	0
T24	1201	3	0	1
T25	1156	0	0	0
T31	0	3	0	1
T32	0	648	0	1
T33	1766	31	0	1
T36	0	60	0	1
T37	0	11	0	1
T38	0	3	0	1
T74	0	3	0	1

gen_edn_if_asserts[2].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206834390	206687791	0	0
T1	1104	1019	0	0
T2	869	726	0	0
T3	882	764	0	0
T4	883	733	0	0
T20	1110	1032	0	0
T21	1318	1237	0	0
T22	583039	583028	0	0
T23	1038	956	0	0
T24	1201	1111	0	0
T25	1156	1105	0	0

gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206834390	123390	0	0
T2	869	450	0	0
T3	882	31	0	0
T4	883	453	0	0
T5	0	627	0	0
T6	0	420	0	0
T14	0	324	0	0
T15	0	1114	0	0
T16	0	1147	0	0
T17	1963	0	0	0
T20	1110	0	0	0
T21	1318	0	0	0
T22	583039	0	0	0
T23	1038	0	0	0
T24	1201	0	0	0
T25	1156	0	0	0
T56	0	7	0	0
T73	0	376	0	0

gen_edn_if_asserts[3].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206834390	568311	0	0
T1	1104	17	0	0
T2	869	403	0	0
T3	882	415	0	0
T4	883	403	0	0
T20	1110	44	0	0
T21	1318	21	0	0
T22	583039	2467	0	0
T23	1038	38	0	0
T24	1201	48	0	0
T25	1156	63	0	0

gen_edn_if_asserts[3].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206834390	5744	0	91
T5	1481	0	0	0
T9	2500	0	0	0
T13	1803	0	0	0
T14	614	0	0	0
T31	1878	0	0	0
T33	1766	24	0	1
T34	0	3	0	1
T36	0	22	0	1
T37	0	18	0	1
T38	0	1011	0	1
T41	0	35	0	1
T54	1458	0	0	0
T55	945	0	0	0
T56	623	0	0	0
T57	1203	0	0	0
T74	0	3	0	1
T77	0	3	0	1
T78	0	25	0	1
T79	0	3	0	1

gen_edn_if_asserts[3].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206834390	206687791	0	0
T1	1104	1019	0	0
T2	869	726	0	0
T3	882	764	0	0
T4	883	733	0	0
T20	1110	1032	0	0
T21	1318	1237	0	0
T22	583039	583028	0	0
T23	1038	956	0	0
T24	1201	1111	0	0
T25	1156	1105	0	0

gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206834390	123390	0	0
T2	869	450	0	0
T3	882	31	0	0
T4	883	453	0	0
T5	0	627	0	0
T6	0	420	0	0
T14	0	324	0	0
T15	0	1114	0	0
T16	0	1147	0	0
T17	1963	0	0	0
T20	1110	0	0	0
T21	1318	0	0	0
T22	583039	0	0	0
T23	1038	0	0	0
T24	1201	0	0	0
T25	1156	0	0	0
T56	0	7	0	0
T73	0	376	0	0

gen_edn_if_asserts[4].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206834390	568311	0	0
T1	1104	17	0	0
T2	869	403	0	0
T3	882	415	0	0
T4	883	403	0	0
T20	1110	44	0	0
T21	1318	21	0	0
T22	583039	2467	0	0
T23	1038	38	0	0
T24	1201	48	0	0
T25	1156	63	0	0

gen_edn_if_asserts[4].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206834390	3312	0	105
T9	2500	45	0	1
T13	1803	0	0	0
T14	614	0	0	0
T17	1963	4	0	1
T31	1878	5	0	1
T36	0	15	0	1
T38	0	45	0	1
T39	0	60	0	1
T41	0	0	0	1
T54	1458	0	0	0
T55	945	0	0	0
T56	623	0	0	0
T57	1203	0	0	0
T58	13863	0	0	0
T76	0	16	0	1
T77	0	23	0	1
T78	0	0	0	1
T80	0	3	0	0
T81	0	3	0	0

gen_edn_if_asserts[4].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206834390	206687791	0	0
T1	1104	1019	0	0
T2	869	726	0	0
T3	882	764	0	0
T4	883	733	0	0
T20	1110	1032	0	0
T21	1318	1237	0	0
T22	583039	583028	0	0
T23	1038	956	0	0
T24	1201	1111	0	0
T25	1156	1105	0	0

gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206834390	123390	0	0
T2	869	450	0	0
T3	882	31	0	0
T4	883	453	0	0
T5	0	627	0	0
T6	0	420	0	0
T14	0	324	0	0
T15	0	1114	0	0
T16	0	1147	0	0
T17	1963	0	0	0
T20	1110	0	0	0
T21	1318	0	0	0
T22	583039	0	0	0
T23	1038	0	0	0
T24	1201	0	0	0
T25	1156	0	0	0
T56	0	7	0	0
T73	0	376	0	0

gen_edn_if_asserts[5].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206834390	568311	0	0
T1	1104	17	0	0
T2	869	403	0	0
T3	882	415	0	0
T4	883	403	0	0
T20	1110	44	0	0
T21	1318	21	0	0
T22	583039	2467	0	0
T23	1038	38	0	0
T24	1201	48	0	0
T25	1156	63	0	0

gen_edn_if_asserts[5].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206834390	3103	0	87
T9	2500	3	0	1
T11	0	3	0	1
T13	1803	0	0	0
T14	614	0	0	0
T31	1878	55	0	1
T36	0	56	0	1
T39	0	639	0	1
T54	1458	0	0	0
T55	945	0	0	0
T56	623	0	0	0
T57	1203	0	0	0
T58	13863	0	0	0
T59	1454	0	0	0
T76	0	3	0	1
T82	0	3	0	0
T83	0	3	0	1
T84	0	12	0	1
T85	0	46	0	1
T86	0	0	0	1

gen_edn_if_asserts[5].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206834390	206687791	0	0
T1	1104	1019	0	0
T2	869	726	0	0
T3	882	764	0	0
T4	883	733	0	0
T20	1110	1032	0	0
T21	1318	1237	0	0
T22	583039	583028	0	0
T23	1038	956	0	0
T24	1201	1111	0	0
T25	1156	1105	0	0

gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206834390	123390	0	0
T2	869	450	0	0
T3	882	31	0	0
T4	883	453	0	0
T5	0	627	0	0
T6	0	420	0	0
T14	0	324	0	0
T15	0	1114	0	0
T16	0	1147	0	0
T17	1963	0	0	0
T20	1110	0	0	0
T21	1318	0	0	0
T22	583039	0	0	0
T23	1038	0	0	0
T24	1201	0	0	0
T25	1156	0	0	0
T56	0	7	0	0
T73	0	376	0	0

gen_edn_if_asserts[6].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206834390	568311	0	0
T1	1104	17	0	0
T2	869	403	0	0
T3	882	415	0	0
T4	883	403	0	0
T20	1110	44	0	0
T21	1318	21	0	0
T22	583039	2467	0	0
T23	1038	38	0	0
T24	1201	48	0	0
T25	1156	63	0	0

gen_edn_if_asserts[6].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206834390	1316	0	79
T5	1481	0	0	0
T9	2500	3	0	1
T10	0	24	0	1
T13	1803	3	0	0
T14	614	0	0	0
T31	1878	3	0	1
T33	1766	3	0	1
T36	0	3	0	1
T39	0	3	0	1
T40	0	15	0	1
T42	0	3	0	1
T54	1458	0	0	0
T55	945	0	0	0
T56	623	0	0	0
T57	1203	0	0	0
T74	0	3	0	1
T76	0	0	0	1

gen_edn_if_asserts[6].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206834390	206687791	0	0
T1	1104	1019	0	0
T2	869	726	0	0
T3	882	764	0	0
T4	883	733	0	0
T20	1110	1032	0	0
T21	1318	1237	0	0
T22	583039	583028	0	0
T23	1038	956	0	0
T24	1201	1111	0	0
T25	1156	1105	0	0

gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	206834390	123390	0	0
T2	869	450	0	0
T3	882	31	0	0
T4	883	453	0	0
T5	0	627	0	0
T6	0	420	0	0
T14	0	324	0	0
T15	0	1114	0	0
T16	0	1147	0	0
T17	1963	0	0	0
T20	1110	0	0	0
T21	1318	0	0	0
T22	583039	0	0	0
T23	1038	0	0	0
T24	1201	0	0	0
T25	1156	0	0	0
T56	0	7	0	0
T73	0	376	0	0