Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44		83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	233562173	11304923	0	0
boot_gen_cmd_rd_A	233562173	50192	0	0
boot_ins_cmd_rd_A	233562173	57312	0	0
ctrl_rd_A	233562173	50761	0	0
err_code_test_rd_A	233562173	50683	0	0
intr_enable_rd_A	233562173	58035	0	0
max_num_reqs_between_reseeds_rd_A	233562173	58887	0	0
regwen_rd_A	233562173	59946	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233562173	11304923	0	0
T2	173192	99673	0	0
T3	2196	0	0	0
T4	840	0	0	0
T13	1783	0	0	0
T14	1385	0	0	0
T16	1759	0	0	0
T17	1087	0	0	0
T18	937	0	0	0
T19	918	0	0	0
T23	0	55	0	0
T24	0	5	0	0
T44	1558	0	0	0
T150	0	41	0	0
T151	0	557	0	0
T152	0	7	0	0
T187	0	68	0	0
T188	0	68	0	0
T189	0	11	0	0
T190	0	272	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233562173	50192	0	0
T152	4014	0	0	0
T188	2898	6	0	0
T189	8057	0	0	0
T190	1974	0	0	0
T191	0	6	0	0
T192	0	69	0	0
T193	0	51	0	0
T194	0	37	0	0
T195	0	30	0	0
T196	0	1	0	0
T197	0	2	0	0
T198	0	17	0	0
T199	0	7	0	0
T200	1601	0	0	0
T201	886	0	0	0
T202	6250	0	0	0
T203	839	0	0	0
T204	1887	0	0	0
T205	2070	0	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233562173	57312	0	0
T191	6270	2	0	0
T192	3307	37	0	0
T193	0	32	0	0
T194	0	19	0	0
T195	0	66	0	0
T197	0	23	0	0
T198	0	39	0	0
T199	0	29	0	0
T206	0	3	0	0
T207	0	2	0	0
T208	1620	0	0	0
T209	3064	0	0	0
T210	873	0	0	0
T211	50208	0	0	0
T212	1081	0	0	0
T213	1413	0	0	0
T214	1128	0	0	0
T215	1951	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233562173	50761	0	0
T152	4014	0	0	0
T188	2898	10	0	0
T189	8057	0	0	0
T190	1974	0	0	0
T191	0	7	0	0
T192	0	51	0	0
T193	0	18	0	0
T194	0	7	0	0
T195	0	31	0	0
T196	0	4	0	0
T197	0	5	0	0
T198	0	32	0	0
T200	1601	0	0	0
T201	886	0	0	0
T202	6250	0	0	0
T203	839	0	0	0
T204	1887	0	0	0
T205	2070	0	0	0
T206	0	3	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233562173	50683	0	0
T152	4014	0	0	0
T188	2898	4	0	0
T189	8057	0	0	0
T190	1974	0	0	0
T192	0	39	0	0
T193	0	5	0	0
T194	0	18	0	0
T195	0	53	0	0
T196	0	8	0	0
T197	0	6	0	0
T198	0	3	0	0
T199	0	26	0	0
T200	1601	0	0	0
T201	886	0	0	0
T202	6250	0	0	0
T203	839	0	0	0
T204	1887	0	0	0
T205	2070	0	0	0
T206	0	7	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233562173	58035	0	0
T24	4237	90	0	0
T37	1252	12	0	0
T152	4014	0	0	0
T188	2898	6	0	0
T189	8057	79	0	0
T191	0	6	0	0
T200	1601	0	0	0
T216	971	19	0	0
T217	1254	6	0	0
T218	1247	18	0	0
T219	0	451	0	0
T220	0	5	0	0
T221	725	0	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233562173	58887	0	0
T24	4237	25	0	0
T152	4014	0	0	0
T188	2898	19	0	0
T189	8057	41	0	0
T190	1974	0	0	0
T191	0	29	0	0
T192	0	47	0	0
T193	0	24	0	0
T200	1601	0	0	0
T201	886	0	0	0
T206	0	10	0	0
T211	0	95	0	0
T217	1254	5	0	0
T218	1247	0	0	0
T219	0	455	0	0
T221	725	0	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	233562173	59946	0	0
T24	4237	52	0	0
T152	4014	0	0	0
T188	2898	25	0	0
T189	8057	50	0	0
T190	1974	0	0	0
T192	0	40	0	0
T193	0	11	0	0
T194	0	24	0	0
T200	1601	0	0	0
T201	886	0	0	0
T206	0	3	0	0
T211	0	75	0	0
T217	1254	6	0	0
T218	1247	0	0	0
T219	0	447	0	0
T221	725	0	0	0