Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : edn
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.44 83.33 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut 94.44 83.33 100.00 100.00



Module Instance : tb.dut

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.44 83.33 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.33 99.02 92.32 96.79 91.45 98.62 99.77


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
tb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
edn_csr_assert 100.00 100.00
gen_alert_tx[0].u_prim_alert_sender 100.00 100.00
gen_alert_tx[1].u_prim_alert_sender 100.00 100.00
tlul_assert_device 100.00 100.00 100.00 100.00
u_edn_core 91.66 99.92 89.58 70.79 91.45 99.29 98.91
u_edn_cov_if 25.00 50.00 0.00
u_reg 98.63 96.98 98.92 100.00 97.26 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Cond Coverage for Module : edn
TotalCoveredPercent
Conditions6583.33
Logical6583.33
Non-Logical00
Event00

 LINE       99
 EXPRESSION (alert[0] || intg_err_alert[0])
             ----1---    --------2--------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT13,T14,T15

 LINE       99
 EXPRESSION (alert[1] || intg_err_alert[1])
             ----1---    --------2--------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT20,T21,T22
10CoveredT4,T6,T12

Toggle Coverage for Module : edn
TotalCoveredPercent
Totals 69 69 100.00
Total Bits 1168 1168 100.00
Total Bits 0->1 584 584 100.00
Total Bits 1->0 584 584 100.00

Ports 69 69 100.00
Port Bits 1168 1168 100.00
Port Bits 0->1 584 584 100.00
Port Bits 1->0 584 584 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T4,T23 Yes T1,T2,T3 INPUT
tl_i.d_ready Yes Yes T2,T3,T17 Yes T1,T2,T3 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T2,T3,T16 Yes T2,T3,T16 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_source[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_error Yes Yes T2,T23,T24 Yes T2,T23,T24 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_user.rsp_intg[5:0] Yes Yes *T1,T2,*T3 Yes T1,T2,T3 OUTPUT
tl_o.d_user.rsp_intg[6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_sink Unreachable Unreachable Unreachable OUTPUT
tl_o.d_source[7:0] Yes Yes T1,T2,T16 Yes T1,T2,T16 OUTPUT
tl_o.d_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_i[0].edn_req Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
edn_i[1].edn_req Yes Yes T18,T25,T8 Yes T18,T25,T8 INPUT
edn_i[2].edn_req Yes Yes T14,T19,T25 Yes T14,T19,T25 INPUT
edn_i[3].edn_req Yes Yes T3,T13,T25 Yes T3,T13,T25 INPUT
edn_i[4].edn_req Yes Yes T3,T25,T8 Yes T3,T25,T8 INPUT
edn_i[5].edn_req Yes Yes T25,T8,T26 Yes T25,T8,T26 INPUT
edn_i[6].edn_req Yes Yes T4,T25,T8 Yes T4,T25,T8 INPUT
edn_o[0].edn_bus[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[0].edn_fips Yes Yes T2,T18,T27 Yes T2,T17,T18 OUTPUT
edn_o[0].edn_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[1].edn_bus[31:0] Yes Yes T18,T25,T8 Yes T18,T25,T8 OUTPUT
edn_o[1].edn_fips Yes Yes T8,T26,T28 Yes T8,T26,T28 OUTPUT
edn_o[1].edn_ack Yes Yes T18,T25,T8 Yes T18,T25,T8 OUTPUT
edn_o[2].edn_bus[31:0] Yes Yes T19,T25,T8 Yes T19,T25,T8 OUTPUT
edn_o[2].edn_fips Yes Yes T29,T30,T31 Yes T14,T32,T29 OUTPUT
edn_o[2].edn_ack Yes Yes T14,T19,T25 Yes T14,T19,T25 OUTPUT
edn_o[3].edn_bus[31:0] Yes Yes T3,T13,T25 Yes T3,T13,T25 OUTPUT
edn_o[3].edn_fips Yes Yes T3,T8,T33 Yes T3,T13,T8 OUTPUT
edn_o[3].edn_ack Yes Yes T3,T13,T25 Yes T3,T13,T25 OUTPUT
edn_o[4].edn_bus[31:0] Yes Yes T3,T25,T8 Yes T3,T25,T8 OUTPUT
edn_o[4].edn_fips Yes Yes T3,T25,T26 Yes T3,T25,T8 OUTPUT
edn_o[4].edn_ack Yes Yes T3,T25,T8 Yes T3,T25,T8 OUTPUT
edn_o[5].edn_bus[31:0] Yes Yes T25,T8,T26 Yes T25,T8,T26 OUTPUT
edn_o[5].edn_fips Yes Yes T25,T10,T34 Yes T25,T8,T35 OUTPUT
edn_o[5].edn_ack Yes Yes T25,T8,T26 Yes T25,T8,T26 OUTPUT
edn_o[6].edn_bus[31:0] Yes Yes T25,T8,T26 Yes T25,T8,T26 OUTPUT
edn_o[6].edn_fips Yes Yes T8,T33,T36 Yes T25,T8,T26 OUTPUT
edn_o[6].edn_ack Yes Yes T25,T8,T26 Yes T25,T8,T26 OUTPUT
csrng_cmd_o.genbits_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
csrng_cmd_o.csrng_req_bus[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
csrng_cmd_o.csrng_req_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
csrng_cmd_i.genbits_bus[127:0] Yes Yes T2,T3,T18 Yes T2,T3,T18 INPUT
csrng_cmd_i.genbits_fips Yes Yes T2,T3,T18 Yes T2,T3,T18 INPUT
csrng_cmd_i.genbits_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
csrng_cmd_i.csrng_rsp_sts Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
csrng_cmd_i.csrng_rsp_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
csrng_cmd_i.csrng_req_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T16,T13,T14 Yes T16,T13,T14 INPUT
alert_rx_i[0].ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i[0].ping_p Unreachable Unreachable Unreachable INPUT
alert_rx_i[1].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[1].ack_p Yes Yes T16,T4,T23 Yes T16,T4,T23 INPUT
alert_rx_i[1].ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i[1].ping_p Unreachable Unreachable Unreachable INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T16,T13,T14 Yes T16,T13,T14 OUTPUT
alert_tx_o[1].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[1].alert_p Yes Yes T16,T4,T23 Yes T16,T4,T23 OUTPUT
intr_edn_cmd_req_done_o Yes Yes T2,T37,T38 Yes T2,T37,T38 OUTPUT
intr_edn_fatal_err_o Yes Yes T2,T37,T38 Yes T2,T37,T38 OUTPUT

*Tests covering at least one bit in the range

Assert Coverage for Module : edn
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 43 43 100.00 43 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 43 43 100.00 43 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AlertTxKnownO_A 233039250 232884449 0 0
CsrngAppIfOut_A 233039250 232884449 0 0
FpvSecCmCntAlertCheck_A 233039250 132 0 0
FpvSecCmMainFsmCheck_A 233039250 80 0 0
FpvSecCmRegWeOnehotCheck_A 233039250 80 0 0
IntrEdnCmdReqDoneKnownO_A 233039250 232884449 0 0
TlAReadyKnownO_A 233039250 232884449 0 0
TlDValidKnownO_A 233039250 232884449 0 0
gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A 233039250 80 0 0
gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A 233039250 80 0 0
gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A 233039250 80 0 0
gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A 233039250 80 0 0
gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A 233039250 80 0 0
gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A 233039250 80 0 0
gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A 233039250 80 0 0
gen_edn_if_asserts[0].EdnDataStableDisable_A 233039250 521219 0 0
gen_edn_if_asserts[0].EdnDataStable_A 233039250 130289 0 360
gen_edn_if_asserts[0].EdnEndPointOut_A 233039250 232884449 0 0
gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A 233039250 135336 0 0
gen_edn_if_asserts[1].EdnDataStableDisable_A 233039250 521219 0 0
gen_edn_if_asserts[1].EdnDataStable_A 233039250 6147 0 98
gen_edn_if_asserts[1].EdnEndPointOut_A 233039250 232884449 0 0
gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A 233039250 135336 0 0
gen_edn_if_asserts[2].EdnDataStableDisable_A 233039250 521219 0 0
gen_edn_if_asserts[2].EdnDataStable_A 233039250 1910 0 105
gen_edn_if_asserts[2].EdnEndPointOut_A 233039250 232884449 0 0
gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A 233039250 135336 0 0
gen_edn_if_asserts[3].EdnDataStableDisable_A 233039250 521219 0 0
gen_edn_if_asserts[3].EdnDataStable_A 233039250 2961 0 93
gen_edn_if_asserts[3].EdnEndPointOut_A 233039250 232884449 0 0
gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A 233039250 135336 0 0
gen_edn_if_asserts[4].EdnDataStableDisable_A 233039250 521219 0 0
gen_edn_if_asserts[4].EdnDataStable_A 233039250 1529 0 87
gen_edn_if_asserts[4].EdnEndPointOut_A 233039250 232884449 0 0
gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A 233039250 135336 0 0
gen_edn_if_asserts[5].EdnDataStableDisable_A 233039250 521219 0 0
gen_edn_if_asserts[5].EdnDataStable_A 233039250 1337 0 79
gen_edn_if_asserts[5].EdnEndPointOut_A 233039250 232884449 0 0
gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A 233039250 135336 0 0
gen_edn_if_asserts[6].EdnDataStableDisable_A 233039250 521219 0 0
gen_edn_if_asserts[6].EdnDataStable_A 233039250 2636 0 71
gen_edn_if_asserts[6].EdnEndPointOut_A 233039250 232884449 0 0
gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A 233039250 135336 0 0


AlertTxKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 233039250 232884449 0 0
T1 680 626 0 0
T2 173192 173180 0 0
T3 2196 2111 0 0
T4 840 675 0 0
T13 1783 1706 0 0
T14 1385 1326 0 0
T16 1759 1680 0 0
T17 1087 1000 0 0
T18 937 853 0 0
T19 918 818 0 0

CsrngAppIfOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 233039250 232884449 0 0
T1 680 626 0 0
T2 173192 173180 0 0
T3 2196 2111 0 0
T4 840 675 0 0
T13 1783 1706 0 0
T14 1385 1326 0 0
T16 1759 1680 0 0
T17 1087 1000 0 0
T18 937 853 0 0
T19 918 818 0 0

FpvSecCmCntAlertCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 233039250 132 0 0
T4 840 1 0 0
T6 1900 1 0 0
T7 0 1 0 0
T12 701 1 0 0
T25 2179 0 0 0
T27 1154 0 0 0
T34 0 1 0 0
T39 0 1 0 0
T40 0 1 0 0
T41 0 1 0 0
T42 0 1 0 0
T43 0 1 0 0
T44 1558 0 0 0
T45 1491 0 0 0
T46 1274 0 0 0
T47 1444 0 0 0
T48 1783 0 0 0

FpvSecCmMainFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 233039250 80 0 0
T20 40827 20 0 0
T21 0 10 0 0
T22 0 20 0 0
T49 0 10 0 0
T50 0 20 0 0
T51 486354 0 0 0
T52 1284 0 0 0
T53 1866 0 0 0
T54 1963 0 0 0
T55 845 0 0 0
T56 1397 0 0 0
T57 1009 0 0 0
T58 966 0 0 0
T59 1719 0 0 0

FpvSecCmRegWeOnehotCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 233039250 80 0 0
T20 40827 20 0 0
T21 0 10 0 0
T22 0 20 0 0
T49 0 10 0 0
T50 0 20 0 0
T51 486354 0 0 0
T52 1284 0 0 0
T53 1866 0 0 0
T54 1963 0 0 0
T55 845 0 0 0
T56 1397 0 0 0
T57 1009 0 0 0
T58 966 0 0 0
T59 1719 0 0 0

IntrEdnCmdReqDoneKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 233039250 232884449 0 0
T1 680 626 0 0
T2 173192 173180 0 0
T3 2196 2111 0 0
T4 840 675 0 0
T13 1783 1706 0 0
T14 1385 1326 0 0
T16 1759 1680 0 0
T17 1087 1000 0 0
T18 937 853 0 0
T19 918 818 0 0

TlAReadyKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 233039250 232884449 0 0
T1 680 626 0 0
T2 173192 173180 0 0
T3 2196 2111 0 0
T4 840 675 0 0
T13 1783 1706 0 0
T14 1385 1326 0 0
T16 1759 1680 0 0
T17 1087 1000 0 0
T18 937 853 0 0
T19 918 818 0 0

TlDValidKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 233039250 232884449 0 0
T1 680 626 0 0
T2 173192 173180 0 0
T3 2196 2111 0 0
T4 840 675 0 0
T13 1783 1706 0 0
T14 1385 1326 0 0
T16 1759 1680 0 0
T17 1087 1000 0 0
T18 937 853 0 0
T19 918 818 0 0

gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 233039250 80 0 0
T20 40827 20 0 0
T21 0 10 0 0
T22 0 20 0 0
T49 0 10 0 0
T50 0 20 0 0
T51 486354 0 0 0
T52 1284 0 0 0
T53 1866 0 0 0
T54 1963 0 0 0
T55 845 0 0 0
T56 1397 0 0 0
T57 1009 0 0 0
T58 966 0 0 0
T59 1719 0 0 0

gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 233039250 80 0 0
T20 40827 20 0 0
T21 0 10 0 0
T22 0 20 0 0
T49 0 10 0 0
T50 0 20 0 0
T51 486354 0 0 0
T52 1284 0 0 0
T53 1866 0 0 0
T54 1963 0 0 0
T55 845 0 0 0
T56 1397 0 0 0
T57 1009 0 0 0
T58 966 0 0 0
T59 1719 0 0 0

gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 233039250 80 0 0
T20 40827 20 0 0
T21 0 10 0 0
T22 0 20 0 0
T49 0 10 0 0
T50 0 20 0 0
T51 486354 0 0 0
T52 1284 0 0 0
T53 1866 0 0 0
T54 1963 0 0 0
T55 845 0 0 0
T56 1397 0 0 0
T57 1009 0 0 0
T58 966 0 0 0
T59 1719 0 0 0

gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 233039250 80 0 0
T20 40827 20 0 0
T21 0 10 0 0
T22 0 20 0 0
T49 0 10 0 0
T50 0 20 0 0
T51 486354 0 0 0
T52 1284 0 0 0
T53 1866 0 0 0
T54 1963 0 0 0
T55 845 0 0 0
T56 1397 0 0 0
T57 1009 0 0 0
T58 966 0 0 0
T59 1719 0 0 0

gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 233039250 80 0 0
T20 40827 20 0 0
T21 0 10 0 0
T22 0 20 0 0
T49 0 10 0 0
T50 0 20 0 0
T51 486354 0 0 0
T52 1284 0 0 0
T53 1866 0 0 0
T54 1963 0 0 0
T55 845 0 0 0
T56 1397 0 0 0
T57 1009 0 0 0
T58 966 0 0 0
T59 1719 0 0 0

gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 233039250 80 0 0
T20 40827 20 0 0
T21 0 10 0 0
T22 0 20 0 0
T49 0 10 0 0
T50 0 20 0 0
T51 486354 0 0 0
T52 1284 0 0 0
T53 1866 0 0 0
T54 1963 0 0 0
T55 845 0 0 0
T56 1397 0 0 0
T57 1009 0 0 0
T58 966 0 0 0
T59 1719 0 0 0

gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 233039250 80 0 0
T20 40827 20 0 0
T21 0 10 0 0
T22 0 20 0 0
T49 0 10 0 0
T50 0 20 0 0
T51 486354 0 0 0
T52 1284 0 0 0
T53 1866 0 0 0
T54 1963 0 0 0
T55 845 0 0 0
T56 1397 0 0 0
T57 1009 0 0 0
T58 966 0 0 0
T59 1719 0 0 0

gen_edn_if_asserts[0].EdnDataStableDisable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 233039250 521219 0 0
T1 680 13 0 0
T2 173192 223 0 0
T3 2196 225 0 0
T4 840 501 0 0
T13 1783 16 0 0
T14 1385 121 0 0
T16 1759 1679 0 0
T17 1087 13 0 0
T18 937 12 0 0
T19 918 79 0 0

gen_edn_if_asserts[0].EdnDataStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 233039250 130289 0 360
T1 680 3 0 1
T2 173192 17 0 0
T3 2196 3 0 1
T4 840 0 0 0
T13 1783 0 0 0
T14 1385 0 0 0
T16 1759 0 0 0
T17 1087 3 0 1
T18 937 22 0 1
T19 918 0 0 0
T25 0 13 0 1
T27 0 19 0 1
T44 0 3 0 1
T45 0 3 0 1
T46 0 0 0 1
T60 0 3 0 1

gen_edn_if_asserts[0].EdnEndPointOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 233039250 232884449 0 0
T1 680 626 0 0
T2 173192 173180 0 0
T3 2196 2111 0 0
T4 840 675 0 0
T13 1783 1706 0 0
T14 1385 1326 0 0
T16 1759 1680 0 0
T17 1087 1000 0 0
T18 937 853 0 0
T19 918 818 0 0

gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 233039250 135336 0 0
T4 840 211 0 0
T6 1900 1074 0 0
T7 0 1114 0 0
T12 701 302 0 0
T25 2179 0 0 0
T27 1154 0 0 0
T39 0 1090 0 0
T44 1558 0 0 0
T45 1491 0 0 0
T46 1274 0 0 0
T47 1444 0 0 0
T48 1783 0 0 0
T61 0 7 0 0
T62 0 399 0 0
T63 0 530 0 0
T64 0 352 0 0
T65 0 702 0 0

gen_edn_if_asserts[1].EdnDataStableDisable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 233039250 521219 0 0
T1 680 13 0 0
T2 173192 223 0 0
T3 2196 225 0 0
T4 840 501 0 0
T13 1783 16 0 0
T14 1385 121 0 0
T16 1759 1679 0 0
T17 1087 13 0 0
T18 937 12 0 0
T19 918 79 0 0

gen_edn_if_asserts[1].EdnDataStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 233039250 6147 0 98
T4 840 0 0 0
T8 4163 52 0 1
T14 1385 0 0 0
T18 937 3 0 1
T19 918 0 0 0
T25 2179 5 0 1
T26 0 54 0 1
T27 1154 0 0 0
T28 0 53 0 1
T29 0 63 0 1
T31 0 16 0 1
T32 0 7 0 1
T33 0 3 0 1
T36 0 61 0 1
T44 1558 0 0 0
T45 1491 0 0 0
T66 1060 0 0 0

gen_edn_if_asserts[1].EdnEndPointOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 233039250 232884449 0 0
T1 680 626 0 0
T2 173192 173180 0 0
T3 2196 2111 0 0
T4 840 675 0 0
T13 1783 1706 0 0
T14 1385 1326 0 0
T16 1759 1680 0 0
T17 1087 1000 0 0
T18 937 853 0 0
T19 918 818 0 0

gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 233039250 135336 0 0
T4 840 211 0 0
T6 1900 1074 0 0
T7 0 1114 0 0
T12 701 302 0 0
T25 2179 0 0 0
T27 1154 0 0 0
T39 0 1090 0 0
T44 1558 0 0 0
T45 1491 0 0 0
T46 1274 0 0 0
T47 1444 0 0 0
T48 1783 0 0 0
T61 0 7 0 0
T62 0 399 0 0
T63 0 530 0 0
T64 0 352 0 0
T65 0 702 0 0

gen_edn_if_asserts[2].EdnDataStableDisable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 233039250 521219 0 0
T1 680 13 0 0
T2 173192 223 0 0
T3 2196 225 0 0
T4 840 501 0 0
T13 1783 16 0 0
T14 1385 121 0 0
T16 1759 1679 0 0
T17 1087 13 0 0
T18 937 12 0 0
T19 918 79 0 0

gen_edn_if_asserts[2].EdnDataStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 233039250 1910 0 105
T4 840 0 0 0
T7 2270 0 0 0
T8 4163 7 0 1
T14 1385 4 0 1
T19 918 3 0 1
T25 2179 3 0 1
T26 0 3 0 1
T27 1154 0 0 0
T29 0 51 0 1
T30 0 15 0 1
T31 0 60 0 1
T32 0 3 0 1
T44 1558 0 0 0
T45 1491 0 0 0
T66 1060 0 0 0
T67 0 3 0 1

gen_edn_if_asserts[2].EdnEndPointOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 233039250 232884449 0 0
T1 680 626 0 0
T2 173192 173180 0 0
T3 2196 2111 0 0
T4 840 675 0 0
T13 1783 1706 0 0
T14 1385 1326 0 0
T16 1759 1680 0 0
T17 1087 1000 0 0
T18 937 853 0 0
T19 918 818 0 0

gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 233039250 135336 0 0
T4 840 211 0 0
T6 1900 1074 0 0
T7 0 1114 0 0
T12 701 302 0 0
T25 2179 0 0 0
T27 1154 0 0 0
T39 0 1090 0 0
T44 1558 0 0 0
T45 1491 0 0 0
T46 1274 0 0 0
T47 1444 0 0 0
T48 1783 0 0 0
T61 0 7 0 0
T62 0 399 0 0
T63 0 530 0 0
T64 0 352 0 0
T65 0 702 0 0

gen_edn_if_asserts[3].EdnDataStableDisable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 233039250 521219 0 0
T1 680 13 0 0
T2 173192 223 0 0
T3 2196 225 0 0
T4 840 501 0 0
T13 1783 16 0 0
T14 1385 121 0 0
T16 1759 1679 0 0
T17 1087 13 0 0
T18 937 12 0 0
T19 918 79 0 0

gen_edn_if_asserts[3].EdnDataStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 233039250 2961 0 93
T3 2196 12 0 1
T4 840 0 0 0
T8 0 459 0 1
T13 1783 4 0 1
T14 1385 0 0 0
T16 1759 0 0 0
T17 1087 0 0 0
T18 937 0 0 0
T19 918 0 0 0
T25 2179 3 0 1
T26 0 3 0 1
T28 0 3 0 1
T29 0 37 0 1
T32 0 42 0 1
T33 0 20 0 1
T36 0 19 0 1
T44 1558 0 0 0

gen_edn_if_asserts[3].EdnEndPointOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 233039250 232884449 0 0
T1 680 626 0 0
T2 173192 173180 0 0
T3 2196 2111 0 0
T4 840 675 0 0
T13 1783 1706 0 0
T14 1385 1326 0 0
T16 1759 1680 0 0
T17 1087 1000 0 0
T18 937 853 0 0
T19 918 818 0 0

gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 233039250 135336 0 0
T4 840 211 0 0
T6 1900 1074 0 0
T7 0 1114 0 0
T12 701 302 0 0
T25 2179 0 0 0
T27 1154 0 0 0
T39 0 1090 0 0
T44 1558 0 0 0
T45 1491 0 0 0
T46 1274 0 0 0
T47 1444 0 0 0
T48 1783 0 0 0
T61 0 7 0 0
T62 0 399 0 0
T63 0 530 0 0
T64 0 352 0 0
T65 0 702 0 0

gen_edn_if_asserts[4].EdnDataStableDisable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 233039250 521219 0 0
T1 680 13 0 0
T2 173192 223 0 0
T3 2196 225 0 0
T4 840 501 0 0
T13 1783 16 0 0
T14 1385 121 0 0
T16 1759 1679 0 0
T17 1087 13 0 0
T18 937 12 0 0
T19 918 79 0 0

gen_edn_if_asserts[4].EdnDataStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 233039250 1529 0 87
T3 2196 69 0 1
T4 840 0 0 0
T8 0 6 0 1
T13 1783 0 0 0
T14 1385 0 0 0
T16 1759 0 0 0
T17 1087 0 0 0
T18 937 0 0 0
T19 918 0 0 0
T25 2179 25 0 1
T26 0 29 0 1
T28 0 34 0 1
T29 0 3 0 1
T31 0 3 0 1
T32 0 3 0 1
T36 0 6 0 1
T44 1558 0 0 0
T68 0 3 0 0
T69 0 0 0 1

gen_edn_if_asserts[4].EdnEndPointOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 233039250 232884449 0 0
T1 680 626 0 0
T2 173192 173180 0 0
T3 2196 2111 0 0
T4 840 675 0 0
T13 1783 1706 0 0
T14 1385 1326 0 0
T16 1759 1680 0 0
T17 1087 1000 0 0
T18 937 853 0 0
T19 918 818 0 0

gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 233039250 135336 0 0
T4 840 211 0 0
T6 1900 1074 0 0
T7 0 1114 0 0
T12 701 302 0 0
T25 2179 0 0 0
T27 1154 0 0 0
T39 0 1090 0 0
T44 1558 0 0 0
T45 1491 0 0 0
T46 1274 0 0 0
T47 1444 0 0 0
T48 1783 0 0 0
T61 0 7 0 0
T62 0 399 0 0
T63 0 530 0 0
T64 0 352 0 0
T65 0 702 0 0

gen_edn_if_asserts[5].EdnDataStableDisable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 233039250 521219 0 0
T1 680 13 0 0
T2 173192 223 0 0
T3 2196 225 0 0
T4 840 501 0 0
T13 1783 16 0 0
T14 1385 121 0 0
T16 1759 1679 0 0
T17 1087 13 0 0
T18 937 12 0 0
T19 918 79 0 0

gen_edn_if_asserts[5].EdnDataStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 233039250 1337 0 79
T7 2270 0 0 0
T8 4163 3 0 1
T10 0 57 0 1
T15 1874 0 0 0
T25 2179 24 0 1
T26 1873 3 0 1
T27 1154 0 0 0
T35 0 3 0 1
T36 0 3 0 1
T45 1491 0 0 0
T61 906 0 0 0
T62 782 0 0 0
T66 1060 0 0 0
T70 0 3 0 0
T71 0 3 0 1
T72 0 3 0 1
T73 0 3 0 1
T74 0 0 0 1

gen_edn_if_asserts[5].EdnEndPointOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 233039250 232884449 0 0
T1 680 626 0 0
T2 173192 173180 0 0
T3 2196 2111 0 0
T4 840 675 0 0
T13 1783 1706 0 0
T14 1385 1326 0 0
T16 1759 1680 0 0
T17 1087 1000 0 0
T18 937 853 0 0
T19 918 818 0 0

gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 233039250 135336 0 0
T4 840 211 0 0
T6 1900 1074 0 0
T7 0 1114 0 0
T12 701 302 0 0
T25 2179 0 0 0
T27 1154 0 0 0
T39 0 1090 0 0
T44 1558 0 0 0
T45 1491 0 0 0
T46 1274 0 0 0
T47 1444 0 0 0
T48 1783 0 0 0
T61 0 7 0 0
T62 0 399 0 0
T63 0 530 0 0
T64 0 352 0 0
T65 0 702 0 0

gen_edn_if_asserts[6].EdnDataStableDisable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 233039250 521219 0 0
T1 680 13 0 0
T2 173192 223 0 0
T3 2196 225 0 0
T4 840 501 0 0
T13 1783 16 0 0
T14 1385 121 0 0
T16 1759 1679 0 0
T17 1087 13 0 0
T18 937 12 0 0
T19 918 79 0 0

gen_edn_if_asserts[6].EdnDataStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 233039250 2636 0 71
T7 2270 0 0 0
T8 4163 24 0 1
T10 0 0 0 1
T15 1874 0 0 0
T25 2179 3 0 1
T26 1873 3 0 1
T27 1154 0 0 0
T29 0 3 0 1
T33 0 51 0 1
T36 0 53 0 1
T45 1491 0 0 0
T61 906 0 0 0
T62 782 0 0 0
T66 1060 0 0 0
T72 0 41 0 1
T75 0 11 0 1
T76 0 3 0 1
T77 0 3 0 0

gen_edn_if_asserts[6].EdnEndPointOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 233039250 232884449 0 0
T1 680 626 0 0
T2 173192 173180 0 0
T3 2196 2111 0 0
T4 840 675 0 0
T13 1783 1706 0 0
T14 1385 1326 0 0
T16 1759 1680 0 0
T17 1087 1000 0 0
T18 937 853 0 0
T19 918 818 0 0

gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 233039250 135336 0 0
T4 840 211 0 0
T6 1900 1074 0 0
T7 0 1114 0 0
T12 701 302 0 0
T25 2179 0 0 0
T27 1154 0 0 0
T39 0 1090 0 0
T44 1558 0 0 0
T45 1491 0 0 0
T46 1274 0 0 0
T47 1444 0 0 0
T48 1783 0 0 0
T61 0 7 0 0
T62 0 399 0 0
T63 0 530 0 0
T64 0 352 0 0
T65 0 702 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%