Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44		83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	181954457	8559691	0	0
boot_gen_cmd_rd_A	181954457	54521	0	0
boot_ins_cmd_rd_A	181954457	62734	0	0
ctrl_rd_A	181954457	54662	0	0
err_code_test_rd_A	181954457	55693	0	0
intr_enable_rd_A	181954457	60379	0	0
max_num_reqs_between_reseeds_rd_A	181954457	63930	0	0
regwen_rd_A	181954457	63132	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181954457	8559691	0	0
T23	1390	50	0	0
T24	4313	5	0	0
T25	2075	74	0	0
T26	1278	0	0	0
T134	1983	44	0	0
T135	4472	7	0	0
T136	14971	8	0	0
T137	0	14	0	0
T138	0	20	0	0
T139	0	344	0	0
T140	0	825	0	0
T141	1796	0	0	0
T142	1596	0	0	0
T143	1382	0	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181954457	54521	0	0
T134	1983	10	0	0
T135	4472	0	0	0
T136	14971	0	0	0
T137	13407	0	0	0
T138	1591	2	0	0
T141	1796	5	0	0
T142	1596	0	0	0
T143	1382	0	0	0
T144	0	7	0	0
T145	0	71	0	0
T146	0	18	0	0
T147	0	1	0	0
T148	0	6	0	0
T149	0	8	0	0
T150	0	10	0	0
T151	1265	0	0	0
T152	1596	0	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181954457	62734	0	0
T134	1983	11	0	0
T135	4472	2	0	0
T136	14971	0	0	0
T137	13407	0	0	0
T138	1591	7	0	0
T141	1796	25	0	0
T142	1596	0	0	0
T143	1382	0	0	0
T144	0	4	0	0
T145	0	84	0	0
T146	0	7	0	0
T147	0	3	0	0
T148	0	7	0	0
T149	0	6	0	0
T151	1265	0	0	0
T152	1596	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181954457	54662	0	0
T134	1983	3	0	0
T135	4472	0	0	0
T136	14971	0	0	0
T137	13407	0	0	0
T138	1591	9	0	0
T141	1796	45	0	0
T142	1596	0	0	0
T143	1382	0	0	0
T144	0	4	0	0
T145	0	75	0	0
T146	0	8	0	0
T147	0	8	0	0
T148	0	8	0	0
T149	0	2	0	0
T151	1265	0	0	0
T152	1596	0	0	0
T153	0	8	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181954457	55693	0	0
T134	1983	8	0	0
T135	4472	2	0	0
T136	14971	0	0	0
T137	13407	0	0	0
T138	1591	0	0	0
T141	1796	54	0	0
T142	1596	0	0	0
T143	1382	0	0	0
T144	0	11	0	0
T145	0	81	0	0
T146	0	4	0	0
T147	0	23	0	0
T148	0	9	0	0
T149	0	11	0	0
T150	0	5	0	0
T151	1265	0	0	0
T152	1596	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181954457	60379	0	0
T17	1241	11	0	0
T18	708	0	0	0
T19	1149	10	0	0
T20	1562	0	0	0
T21	1016	0	0	0
T22	1051	0	0	0
T23	1390	0	0	0
T24	4313	0	0	0
T25	2075	0	0	0
T26	1278	0	0	0
T134	0	6	0	0
T135	0	71	0	0
T138	0	9	0	0
T141	0	13	0	0
T144	0	15	0	0
T154	0	9	0	0
T155	0	30	0	0
T156	0	13	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181954457	63930	0	0
T134	1983	13	0	0
T135	4472	45	0	0
T136	14971	0	0	0
T137	13407	0	0	0
T138	1591	13	0	0
T141	1796	59	0	0
T142	1596	0	0	0
T143	1382	0	0	0
T144	0	10	0	0
T145	0	75	0	0
T146	0	9	0	0
T147	0	28	0	0
T151	1265	0	0	0
T152	1596	0	0	0
T155	0	17	0	0
T157	0	211	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181954457	63132	0	0
T134	1983	29	0	0
T135	4472	23	0	0
T136	14971	0	0	0
T137	13407	0	0	0
T138	1591	20	0	0
T141	1796	59	0	0
T142	1596	0	0	0
T143	1382	0	0	0
T144	0	10	0	0
T145	0	85	0	0
T146	0	8	0	0
T147	0	27	0	0
T151	1265	0	0	0
T152	1596	0	0	0
T155	0	16	0	0
T157	0	238	0	0