Unified Coverage Report :: Module :: edn

Module : edn

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	94.44		83.33	100.00			100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.61	99.02	92.31	96.74	87.34	98.48	99.77

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
edn_csr_assert	100.00						100.00
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_edn_core	90.85	99.92	89.58	70.30	87.34	99.07	98.91
u_edn_cov_if	25.00	50.00	0.00
u_reg	98.63	96.98	98.92	100.00		97.26	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Cond Coverage for Module : edn

	Total	Covered	Percent
Conditions	6	5	83.33
Logical	6	5	83.33
Non-Logical	0	0
Event	0	0

 LINE       98
 EXPRESSION (alert[0] || intg_err_alert[0])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T2,T15,T16

 LINE       98
 EXPRESSION (alert[1] || intg_err_alert[1])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T27,T28
1	0	Covered	T4,T6,T7

---

Toggle Coverage for Module : edn

	Total	Covered	Percent
Totals	69	69	100.00
Total Bits	1168	1168	100.00
Total Bits 0->1	584	584	100.00
Total Bits 1->0	584	584	100.00

Ports	69	69	100.00
Port Bits	1168	1168	100.00
Port Bits 0->1	584	584	100.00
Port Bits 1->0	584	584	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
rst_ni	Yes	Yes	T20,T23,T24	Yes	T17,T18,T19	INPUT
tl_i.d_ready	Yes	Yes	T17,T19,T20	Yes	T17,T18,T19	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
tl_i.a_address[31:0]	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
tl_i.a_source[7:0]	Yes	Yes	T17,T18,T20	Yes	T17,T18,T20	INPUT
tl_i.a_size[1:0]	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
tl_i.a_valid	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
tl_o.a_ready	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	OUTPUT
tl_o.d_error	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T17,*T18,*T19	Yes	T17,T18,T19	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T17,T18,T20	Yes	T17,T18,T20	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T17,*T18,*T19	Yes	T17,T18,T19	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	OUTPUT
edn_i[0].edn_req	Yes	Yes	T1,T3,T5	Yes	T1,T3,T5	INPUT
edn_i[1].edn_req	Yes	Yes	T2,T4,T29	Yes	T2,T4,T29	INPUT
edn_i[2].edn_req	Yes	Yes	T10,T30,T31	Yes	T10,T30,T31	INPUT
edn_i[3].edn_req	Yes	Yes	T32,T33,T34	Yes	T32,T33,T34	INPUT
edn_i[4].edn_req	Yes	Yes	T35,T9,T36	Yes	T35,T9,T36	INPUT
edn_i[5].edn_req	Yes	Yes	T37,T33,T34	Yes	T37,T33,T34	INPUT
edn_i[6].edn_req	Yes	Yes	T30,T35,T38	Yes	T30,T35,T38	INPUT
edn_o[0].edn_bus[31:0]	Yes	Yes	T1,T3,T5	Yes	T1,T3,T5	OUTPUT
edn_o[0].edn_fips	Yes	Yes	T1,T3,T5	Yes	T1,T3,T5	OUTPUT
edn_o[0].edn_ack	Yes	Yes	T1,T3,T5	Yes	T1,T3,T5	OUTPUT
edn_o[1].edn_bus[31:0]	Yes	Yes	T29,T34,T39	Yes	T2,T29,T34	OUTPUT
edn_o[1].edn_fips	Yes	Yes	T34,T39,T35	Yes	T29,T34,T39	OUTPUT
edn_o[1].edn_ack	Yes	Yes	T2,T29,T34	Yes	T2,T29,T34	OUTPUT
edn_o[2].edn_bus[31:0]	Yes	Yes	T10,T30,T34	Yes	T10,T30,T34	OUTPUT
edn_o[2].edn_fips	Yes	Yes	T10,T30,T34	Yes	T10,T30,T34	OUTPUT
edn_o[2].edn_ack	Yes	Yes	T10,T30,T31	Yes	T10,T30,T31	OUTPUT
edn_o[3].edn_bus[31:0]	Yes	Yes	T32,T33,T34	Yes	T32,T33,T34	OUTPUT
edn_o[3].edn_fips	Yes	Yes	T34,T40,T41	Yes	T33,T34,T35	OUTPUT
edn_o[3].edn_ack	Yes	Yes	T32,T33,T34	Yes	T32,T33,T34	OUTPUT
edn_o[4].edn_bus[31:0]	Yes	Yes	T35,T36,T42	Yes	T35,T36,T42	OUTPUT
edn_o[4].edn_fips	Yes	Yes	T36,T43,T44	Yes	T35,T36,T43	OUTPUT
edn_o[4].edn_ack	Yes	Yes	T35,T36,T45	Yes	T35,T36,T45	OUTPUT
edn_o[5].edn_bus[31:0]	Yes	Yes	T33,T34,T39	Yes	T37,T33,T34	OUTPUT
edn_o[5].edn_fips	Yes	Yes	T39,T35,T46	Yes	T39,T35,T46	OUTPUT
edn_o[5].edn_ack	Yes	Yes	T37,T33,T34	Yes	T37,T33,T34	OUTPUT
edn_o[6].edn_bus[31:0]	Yes	Yes	T30,T35,T38	Yes	T30,T35,T38	OUTPUT
edn_o[6].edn_fips	Yes	Yes	T30,T12,T47	Yes	T30,T35,T12	OUTPUT
edn_o[6].edn_ack	Yes	Yes	T30,T35,T38	Yes	T30,T35,T38	OUTPUT
csrng_cmd_o.genbits_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_i.genbits_bus[127:0]	Yes	Yes	T1,T3,T10	Yes	T1,T3,T10	INPUT
csrng_cmd_i.genbits_fips	Yes	Yes	T1,T3,T10	Yes	T1,T3,T10	INPUT
csrng_cmd_i.genbits_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_rsp_sts	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_rsp_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_req_ready	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T20,T23,T24	Yes	T20,T23,T24	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T20,T22,T24	Yes	T20,T22,T24	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T20,T23,T24	Yes	T20,T23,T24	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T20,T22,T24	Yes	T20,T22,T24	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T17,T19,T21	Yes	T17,T19,T21	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T21,T26,T48	Yes	T21,T26,T48	OUTPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Module : edn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	43	43	100.00	43	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	43	43	100.00	43	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnownO_A	181491217	181350117	0	0
CsrngAppIfOut_A	181491217	181350117	0	0
FpvSecCmCntAlertCheck_A	181491217	106	0	0
FpvSecCmMainFsmCheck_A	181491217	70	0	0
FpvSecCmRegWeOnehotCheck_A	181491217	70	0	0
IntrEdnCmdReqDoneKnownO_A	181491217	181350117	0	0
TlAReadyKnownO_A	181491217	181350117	0	0
TlDValidKnownO_A	181491217	181350117	0	0
gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A	181491217	70	0	0
gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A	181491217	70	0	0
gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A	181491217	70	0	0
gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A	181491217	70	0	0
gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A	181491217	70	0	0
gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A	181491217	70	0	0
gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A	181491217	70	0	0
gen_edn_if_asserts[0].EdnDataStableDisable_A	181491217	470168	0	0
gen_edn_if_asserts[0].EdnDataStable_A	181491217	73100	0	322
gen_edn_if_asserts[0].EdnEndPointOut_A	181491217	181350117	0	0
gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A	181491217	114023	0	0
gen_edn_if_asserts[1].EdnDataStableDisable_A	181491217	470168	0	0
gen_edn_if_asserts[1].EdnDataStable_A	181491217	4977	0	94
gen_edn_if_asserts[1].EdnEndPointOut_A	181491217	181350117	0	0
gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A	181491217	114023	0	0
gen_edn_if_asserts[2].EdnDataStableDisable_A	181491217	470168	0	0
gen_edn_if_asserts[2].EdnDataStable_A	181491217	1863	0	92
gen_edn_if_asserts[2].EdnEndPointOut_A	181491217	181350117	0	0
gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A	181491217	114023	0	0
gen_edn_if_asserts[3].EdnDataStableDisable_A	181491217	470168	0	0
gen_edn_if_asserts[3].EdnDataStable_A	181491217	52010	0	91
gen_edn_if_asserts[3].EdnEndPointOut_A	181491217	181350117	0	0
gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A	181491217	114023	0	0
gen_edn_if_asserts[4].EdnDataStableDisable_A	181491217	470168	0	0
gen_edn_if_asserts[4].EdnDataStable_A	181491217	5755	0	75
gen_edn_if_asserts[4].EdnEndPointOut_A	181491217	181350117	0	0
gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A	181491217	114023	0	0
gen_edn_if_asserts[5].EdnDataStableDisable_A	181491217	470168	0	0
gen_edn_if_asserts[5].EdnDataStable_A	181491217	2605	0	69
gen_edn_if_asserts[5].EdnEndPointOut_A	181491217	181350117	0	0
gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A	181491217	114023	0	0
gen_edn_if_asserts[6].EdnDataStableDisable_A	181491217	470168	0	0
gen_edn_if_asserts[6].EdnDataStable_A	181491217	2687	0	64
gen_edn_if_asserts[6].EdnEndPointOut_A	181491217	181350117	0	0
gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A	181491217	114023	0	0

AlertTxKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181491217	181350117	0	0
T1	1679	1600	0	0
T2	1555	1497	0	0
T3	218919	218859	0	0
T4	480	332	0	0
T5	190062	190050	0	0
T10	3601	3507	0	0
T29	1195	1111	0	0
T32	996	923	0	0
T37	1888	1807	0	0
T49	1136	1066	0	0

CsrngAppIfOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181491217	181350117	0	0
T1	1679	1600	0	0
T2	1555	1497	0	0
T3	218919	218859	0	0
T4	480	332	0	0
T5	190062	190050	0	0
T10	3601	3507	0	0
T29	1195	1111	0	0
T32	996	923	0	0
T37	1888	1807	0	0
T49	1136	1066	0	0

FpvSecCmCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181491217	106	0	0
T7	1011	1	0	0
T9	1139	0	0	0
T13	2082	1	0	0
T14	0	10	0	0
T27	0	10	0	0
T28	0	10	0	0
T30	1909	0	0	0
T31	1511	0	0	0
T46	1774	0	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	894	0	0	0
T56	1520	0	0	0
T57	1870	0	0	0
T58	3721	0	0	0

FpvSecCmMainFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181491217	70	0	0
T14	15305	10	0	0
T27	0	10	0	0
T28	0	10	0	0
T59	0	20	0	0
T60	0	20	0	0
T61	227501	0	0	0
T62	1243	0	0	0
T63	1324	0	0	0
T64	584	0	0	0
T65	1726	0	0	0
T66	303245	0	0	0
T67	1342	0	0	0
T68	1476	0	0	0
T69	748	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181491217	70	0	0
T14	15305	10	0	0
T27	0	10	0	0
T28	0	10	0	0
T59	0	20	0	0
T60	0	20	0	0
T61	227501	0	0	0
T62	1243	0	0	0
T63	1324	0	0	0
T64	584	0	0	0
T65	1726	0	0	0
T66	303245	0	0	0
T67	1342	0	0	0
T68	1476	0	0	0
T69	748	0	0	0

IntrEdnCmdReqDoneKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181491217	181350117	0	0
T1	1679	1600	0	0
T2	1555	1497	0	0
T3	218919	218859	0	0
T4	480	332	0	0
T5	190062	190050	0	0
T10	3601	3507	0	0
T29	1195	1111	0	0
T32	996	923	0	0
T37	1888	1807	0	0
T49	1136	1066	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181491217	181350117	0	0
T1	1679	1600	0	0
T2	1555	1497	0	0
T3	218919	218859	0	0
T4	480	332	0	0
T5	190062	190050	0	0
T10	3601	3507	0	0
T29	1195	1111	0	0
T32	996	923	0	0
T37	1888	1807	0	0
T49	1136	1066	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181491217	181350117	0	0
T1	1679	1600	0	0
T2	1555	1497	0	0
T3	218919	218859	0	0
T4	480	332	0	0
T5	190062	190050	0	0
T10	3601	3507	0	0
T29	1195	1111	0	0
T32	996	923	0	0
T37	1888	1807	0	0
T49	1136	1066	0	0

gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181491217	70	0	0
T14	15305	10	0	0
T27	0	10	0	0
T28	0	10	0	0
T59	0	20	0	0
T60	0	20	0	0
T61	227501	0	0	0
T62	1243	0	0	0
T63	1324	0	0	0
T64	584	0	0	0
T65	1726	0	0	0
T66	303245	0	0	0
T67	1342	0	0	0
T68	1476	0	0	0
T69	748	0	0	0

gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181491217	70	0	0
T14	15305	10	0	0
T27	0	10	0	0
T28	0	10	0	0
T59	0	20	0	0
T60	0	20	0	0
T61	227501	0	0	0
T62	1243	0	0	0
T63	1324	0	0	0
T64	584	0	0	0
T65	1726	0	0	0
T66	303245	0	0	0
T67	1342	0	0	0
T68	1476	0	0	0
T69	748	0	0	0

gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181491217	70	0	0
T14	15305	10	0	0
T27	0	10	0	0
T28	0	10	0	0
T59	0	20	0	0
T60	0	20	0	0
T61	227501	0	0	0
T62	1243	0	0	0
T63	1324	0	0	0
T64	584	0	0	0
T65	1726	0	0	0
T66	303245	0	0	0
T67	1342	0	0	0
T68	1476	0	0	0
T69	748	0	0	0

gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181491217	70	0	0
T14	15305	10	0	0
T27	0	10	0	0
T28	0	10	0	0
T59	0	20	0	0
T60	0	20	0	0
T61	227501	0	0	0
T62	1243	0	0	0
T63	1324	0	0	0
T64	584	0	0	0
T65	1726	0	0	0
T66	303245	0	0	0
T67	1342	0	0	0
T68	1476	0	0	0
T69	748	0	0	0

gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181491217	70	0	0
T14	15305	10	0	0
T27	0	10	0	0
T28	0	10	0	0
T59	0	20	0	0
T60	0	20	0	0
T61	227501	0	0	0
T62	1243	0	0	0
T63	1324	0	0	0
T64	584	0	0	0
T65	1726	0	0	0
T66	303245	0	0	0
T67	1342	0	0	0
T68	1476	0	0	0
T69	748	0	0	0

gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181491217	70	0	0
T14	15305	10	0	0
T27	0	10	0	0
T28	0	10	0	0
T59	0	20	0	0
T60	0	20	0	0
T61	227501	0	0	0
T62	1243	0	0	0
T63	1324	0	0	0
T64	584	0	0	0
T65	1726	0	0	0
T66	303245	0	0	0
T67	1342	0	0	0
T68	1476	0	0	0
T69	748	0	0	0

gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181491217	70	0	0
T14	15305	10	0	0
T27	0	10	0	0
T28	0	10	0	0
T59	0	20	0	0
T60	0	20	0	0
T61	227501	0	0	0
T62	1243	0	0	0
T63	1324	0	0	0
T64	584	0	0	0
T65	1726	0	0	0
T66	303245	0	0	0
T67	1342	0	0	0
T68	1476	0	0	0
T69	748	0	0	0

gen_edn_if_asserts[0].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181491217	470168	0	0
T1	1679	72	0	0
T2	1555	23	0	0
T3	218919	68	0	0
T4	480	132	0	0
T5	190062	1275	0	0
T10	3601	414	0	0
T29	1195	17	0	0
T32	996	96	0	0
T37	1888	1079	0	0
T49	1136	77	0	0

gen_edn_if_asserts[0].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181491217	73100	0	322
T1	1679	65	0	1
T2	1555	0	0	0
T3	218919	49143	0	1
T4	480	0	0	0
T5	190062	69	0	0
T10	3601	0	0	0
T15	0	4	0	1
T29	1195	0	0	0
T30	0	14	0	1
T32	996	0	0	0
T33	0	3	0	1
T34	0	26	0	1
T37	1888	0	0	0
T49	1136	19	0	1
T56	0	3	0	1
T70	0	3	0	1
T71	0	0	0	1

gen_edn_if_asserts[0].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181491217	181350117	0	0
T1	1679	1600	0	0
T2	1555	1497	0	0
T3	218919	218859	0	0
T4	480	332	0	0
T5	190062	190050	0	0
T10	3601	3507	0	0
T29	1195	1111	0	0
T32	996	923	0	0
T37	1888	1807	0	0
T49	1136	1066	0	0

gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181491217	114023	0	0
T4	480	202	0	0
T5	190062	0	0	0
T6	1843	37	0	0
T7	1011	268	0	0
T8	0	426	0	0
T9	0	377	0	0
T13	0	1154	0	0
T15	1783	0	0	0
T29	1195	0	0	0
T33	1521	0	0	0
T49	1136	0	0	0
T70	1458	0	0	0
T72	0	352	0	0
T73	0	362	0	0
T74	0	649	0	0
T75	0	642	0	0
T76	1223	0	0	0

gen_edn_if_asserts[1].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181491217	470168	0	0
T1	1679	72	0	0
T2	1555	23	0	0
T3	218919	68	0	0
T4	480	132	0	0
T5	190062	1275	0	0
T10	3601	414	0	0
T29	1195	17	0	0
T32	996	96	0	0
T37	1888	1079	0	0
T49	1136	77	0	0

gen_edn_if_asserts[1].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181491217	4977	0	94
T2	1555	4	0	1
T3	218919	0	0	0
T4	480	0	0	0
T5	190062	0	0	0
T10	3601	0	0	0
T11	0	3	0	1
T29	1195	14	0	1
T32	996	0	0	0
T34	0	34	0	1
T35	0	37	0	1
T36	0	33	0	1
T37	1888	0	0	0
T39	0	53	0	1
T40	0	1155	0	1
T46	0	5	0	1
T49	1136	0	0	0
T58	0	51	0	1
T70	1458	0	0	0

gen_edn_if_asserts[1].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181491217	181350117	0	0
T1	1679	1600	0	0
T2	1555	1497	0	0
T3	218919	218859	0	0
T4	480	332	0	0
T5	190062	190050	0	0
T10	3601	3507	0	0
T29	1195	1111	0	0
T32	996	923	0	0
T37	1888	1807	0	0
T49	1136	1066	0	0

gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181491217	114023	0	0
T4	480	202	0	0
T5	190062	0	0	0
T6	1843	37	0	0
T7	1011	268	0	0
T8	0	426	0	0
T9	0	377	0	0
T13	0	1154	0	0
T15	1783	0	0	0
T29	1195	0	0	0
T33	1521	0	0	0
T49	1136	0	0	0
T70	1458	0	0	0
T72	0	352	0	0
T73	0	362	0	0
T74	0	649	0	0
T75	0	642	0	0
T76	1223	0	0	0

gen_edn_if_asserts[2].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181491217	470168	0	0
T1	1679	72	0	0
T2	1555	23	0	0
T3	218919	68	0	0
T4	480	132	0	0
T5	190062	1275	0	0
T10	3601	414	0	0
T29	1195	17	0	0
T32	996	96	0	0
T37	1888	1079	0	0
T49	1136	77	0	0

gen_edn_if_asserts[2].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181491217	1863	0	92
T4	480	0	0	0
T5	190062	0	0	0
T10	3601	315	0	1
T12	0	0	0	1
T15	1783	0	0	0
T29	1195	0	0	0
T30	0	19	0	1
T31	0	3	0	0
T32	996	0	0	0
T34	0	32	0	1
T35	0	58	0	1
T36	0	33	0	1
T37	1888	0	0	0
T39	0	57	0	1
T43	0	3	0	1
T49	1136	0	0	0
T58	0	3	0	1
T70	1458	0	0	0
T76	1223	0	0	0
T77	0	3	0	1

gen_edn_if_asserts[2].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181491217	181350117	0	0
T1	1679	1600	0	0
T2	1555	1497	0	0
T3	218919	218859	0	0
T4	480	332	0	0
T5	190062	190050	0	0
T10	3601	3507	0	0
T29	1195	1111	0	0
T32	996	923	0	0
T37	1888	1807	0	0
T49	1136	1066	0	0

gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181491217	114023	0	0
T4	480	202	0	0
T5	190062	0	0	0
T6	1843	37	0	0
T7	1011	268	0	0
T8	0	426	0	0
T9	0	377	0	0
T13	0	1154	0	0
T15	1783	0	0	0
T29	1195	0	0	0
T33	1521	0	0	0
T49	1136	0	0	0
T70	1458	0	0	0
T72	0	352	0	0
T73	0	362	0	0
T74	0	649	0	0
T75	0	642	0	0
T76	1223	0	0	0

gen_edn_if_asserts[3].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181491217	470168	0	0
T1	1679	72	0	0
T2	1555	23	0	0
T3	218919	68	0	0
T4	480	132	0	0
T5	190062	1275	0	0
T10	3601	414	0	0
T29	1195	17	0	0
T32	996	96	0	0
T37	1888	1079	0	0
T49	1136	77	0	0

gen_edn_if_asserts[3].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181491217	52010	0	91
T4	480	0	0	0
T5	190062	0	0	0
T6	1843	0	0	0
T15	1783	0	0	0
T29	1195	0	0	0
T32	996	3	0	0
T33	1521	3	0	1
T34	0	31	0	1
T35	0	3	0	1
T38	0	3	0	1
T39	0	3	0	1
T40	0	41	0	1
T43	0	0	0	1
T49	1136	0	0	0
T68	0	3	0	1
T70	1458	0	0	0
T76	1223	0	0	0
T78	0	3	0	1
T79	0	3	0	1

gen_edn_if_asserts[3].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181491217	181350117	0	0
T1	1679	1600	0	0
T2	1555	1497	0	0
T3	218919	218859	0	0
T4	480	332	0	0
T5	190062	190050	0	0
T10	3601	3507	0	0
T29	1195	1111	0	0
T32	996	923	0	0
T37	1888	1807	0	0
T49	1136	1066	0	0

gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181491217	114023	0	0
T4	480	202	0	0
T5	190062	0	0	0
T6	1843	37	0	0
T7	1011	268	0	0
T8	0	426	0	0
T9	0	377	0	0
T13	0	1154	0	0
T15	1783	0	0	0
T29	1195	0	0	0
T33	1521	0	0	0
T49	1136	0	0	0
T70	1458	0	0	0
T72	0	352	0	0
T73	0	362	0	0
T74	0	649	0	0
T75	0	642	0	0
T76	1223	0	0	0

gen_edn_if_asserts[4].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181491217	470168	0	0
T1	1679	72	0	0
T2	1555	23	0	0
T3	218919	68	0	0
T4	480	132	0	0
T5	190062	1275	0	0
T10	3601	414	0	0
T29	1195	17	0	0
T32	996	96	0	0
T37	1888	1079	0	0
T49	1136	77	0	0

gen_edn_if_asserts[4].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181491217	5755	0	75
T9	1139	0	0	0
T13	2082	0	0	0
T35	1649	4	0	1
T36	0	31	0	1
T42	0	3	0	0
T43	0	47	0	1
T44	0	32	0	1
T45	0	3	0	1
T46	1774	0	0	0
T47	0	0	0	1
T57	1870	0	0	0
T58	3721	0	0	0
T77	0	5	0	1
T80	0	3	0	0
T81	0	3	0	0
T82	0	4	0	1
T83	16389	0	0	0
T84	1767	0	0	0
T85	1213	0	0	0
T86	1031	0	0	0
T87	0	0	0	1
T88	0	0	0	1

gen_edn_if_asserts[4].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181491217	181350117	0	0
T1	1679	1600	0	0
T2	1555	1497	0	0
T3	218919	218859	0	0
T4	480	332	0	0
T5	190062	190050	0	0
T10	3601	3507	0	0
T29	1195	1111	0	0
T32	996	923	0	0
T37	1888	1807	0	0
T49	1136	1066	0	0

gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181491217	114023	0	0
T4	480	202	0	0
T5	190062	0	0	0
T6	1843	37	0	0
T7	1011	268	0	0
T8	0	426	0	0
T9	0	377	0	0
T13	0	1154	0	0
T15	1783	0	0	0
T29	1195	0	0	0
T33	1521	0	0	0
T49	1136	0	0	0
T70	1458	0	0	0
T72	0	352	0	0
T73	0	362	0	0
T74	0	649	0	0
T75	0	642	0	0
T76	1223	0	0	0

gen_edn_if_asserts[5].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181491217	470168	0	0
T1	1679	72	0	0
T2	1555	23	0	0
T3	218919	68	0	0
T4	480	132	0	0
T5	190062	1275	0	0
T10	3601	414	0	0
T29	1195	17	0	0
T32	996	96	0	0
T37	1888	1079	0	0
T49	1136	77	0	0

gen_edn_if_asserts[5].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181491217	2605	0	69
T4	480	0	0	0
T5	190062	0	0	0
T6	1843	0	0	0
T12	0	0	0	1
T15	1783	0	0	0
T29	1195	0	0	0
T32	996	0	0	0
T33	0	3	0	1
T34	0	3	0	1
T35	0	53	0	1
T37	1888	3	0	0
T38	0	3	0	1
T39	0	40	0	1
T43	0	7	0	1
T46	0	15	0	1
T49	1136	0	0	0
T57	0	3	0	0
T70	1458	0	0	0
T76	1223	0	0	0
T77	0	23	0	1
T87	0	0	0	1

gen_edn_if_asserts[5].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181491217	181350117	0	0
T1	1679	1600	0	0
T2	1555	1497	0	0
T3	218919	218859	0	0
T4	480	332	0	0
T5	190062	190050	0	0
T10	3601	3507	0	0
T29	1195	1111	0	0
T32	996	923	0	0
T37	1888	1807	0	0
T49	1136	1066	0	0

gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181491217	114023	0	0
T4	480	202	0	0
T5	190062	0	0	0
T6	1843	37	0	0
T7	1011	268	0	0
T8	0	426	0	0
T9	0	377	0	0
T13	0	1154	0	0
T15	1783	0	0	0
T29	1195	0	0	0
T33	1521	0	0	0
T49	1136	0	0	0
T70	1458	0	0	0
T72	0	352	0	0
T73	0	362	0	0
T74	0	649	0	0
T75	0	642	0	0
T76	1223	0	0	0

gen_edn_if_asserts[6].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181491217	470168	0	0
T1	1679	72	0	0
T2	1555	23	0	0
T3	218919	68	0	0
T4	480	132	0	0
T5	190062	1275	0	0
T10	3601	414	0	0
T29	1195	17	0	0
T32	996	96	0	0
T37	1888	1079	0	0
T49	1136	77	0	0

gen_edn_if_asserts[6].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181491217	2687	0	64
T9	1139	0	0	0
T12	0	23	0	1
T13	2082	0	0	0
T30	1909	23	0	1
T31	1511	0	0	0
T35	1649	3	0	1
T38	0	3	0	1
T46	1774	0	0	0
T47	0	15	0	1
T56	1520	0	0	0
T57	1870	0	0	0
T77	0	3	0	1
T83	16389	0	0	0
T84	1767	0	0	0
T89	0	3	0	1
T90	0	3	0	1
T91	0	3	0	1
T92	0	3	0	0
T93	0	0	0	1

gen_edn_if_asserts[6].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181491217	181350117	0	0
T1	1679	1600	0	0
T2	1555	1497	0	0
T3	218919	218859	0	0
T4	480	332	0	0
T5	190062	190050	0	0
T10	3601	3507	0	0
T29	1195	1111	0	0
T32	996	923	0	0
T37	1888	1807	0	0
T49	1136	1066	0	0

gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181491217	114023	0	0
T4	480	202	0	0
T5	190062	0	0	0
T6	1843	37	0	0
T7	1011	268	0	0
T8	0	426	0	0
T9	0	377	0	0
T13	0	1154	0	0
T15	1783	0	0	0
T29	1195	0	0	0
T33	1521	0	0	0
T49	1136	0	0	0
T70	1458	0	0	0
T72	0	352	0	0
T73	0	362	0	0
T74	0	649	0	0
T75	0	642	0	0
T76	1223	0	0	0