Unified Coverage Report :: Module :: edn_main_sm

Module : edn_main_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.86	100.00	100.00		86.67	97.62	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_edn_main_sm	96.86	100.00	100.00		86.67	97.62	100.00

---

Module Instance : tb.dut.u_edn_core.u_edn_main_sm

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.86	100.00	100.00		86.67	97.62	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	100.00	100.00		86.67	97.73	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.28	100.00	85.83			100.00		u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
TOTAL		116	116	100.00
ALWAYS	63	3	3	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	67	1	1	100.00
ALWAYS	71	111	111	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
63	3	3
65	1	1
67	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
77	1	1
78	1	1
79	1	1
80	1	1
81	1	1
82	1	1
83	1	1
84	1	1
85	1	1
86	1	1
87	1	1
89	1	1
90	1	1
91	1	1
92	1	1
93	1	1
94	1	1
95	1	1
			MISSING_ELSE
99	1	1
100	1	1
103	1	1
104	1	1
107	1	1
108	1	1
			MISSING_ELSE
112	1	1
113	1	1
116	1	1
117	1	1
118	1	1
			==> MISSING_ELSE
122	1	1
123	1	1
			MISSING_ELSE
127	1	1
128	1	1
131	1	1
132	1	1
			MISSING_ELSE
136	1	1
137	1	1
140	1	1
141	1	1
			MISSING_ELSE
146	1	1
147	1	1
148	1	1
149	1	1
150	1	1
			MISSING_ELSE
154	1	1
155	1	1
156	1	1
157	1	1
158	1	1
			MISSING_ELSE
162	1	1
163	1	1
164	1	1
			MISSING_ELSE
168	1	1
169	1	1
170	1	1
171	1	1
173	1	1
174	1	1
176	1	1
181	1	1
182	1	1
183	1	1
186	1	1
187	1	1
188	1	1
189	1	1
			MISSING_ELSE
193	1	1
194	1	1
195	1	1
198	1	1
199	1	1
200	1	1
201	1	1
			MISSING_ELSE
205	1	1
208	1	1
216	1	1
217	1	1
219	1	1
220	1	1
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
241	1	1
243	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
253	1	1
254	1	1
255	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_main_sm

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       67
 EXPRESSION ((state_q != Idle) && (state_q != BootPulse) && (state_q != SWPortMode))
             --------1--------    -----------2----------    -----------3-----------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T32,T4,T30
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T1,T3,T10

 LINE       67
 SUB-EXPRESSION (state_q != Idle)
                --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       67
 SUB-EXPRESSION (state_q != BootPulse)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       67
 SUB-EXPRESSION (state_q != SWPortMode)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       89
 EXPRESSION (boot_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T32,T4,T78
1	1	Covered	T32,T4,T30

 LINE       91
 EXPRESSION (auto_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T37,T7,T31
1	1	Covered	T1,T3,T10

 LINE       232
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_i)) && 
      2  (state_q inside {BootLoadIns, BootLoadGen, BootInsAckWait, BootCaptGenCnt, BootSendGenCmd, BootGenAckWait, BootPulse, BootDone, BootLoadUni, BootUniAckWait, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode}))

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T37,T32,T4

---

FSM Coverage for Module : edn_main_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	21	21	100.00	(Not included in score)
Transitions	60	52	86.67
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AutoAckWait	189	Covered	T17
AutoCaptGenCnt	176	Covered	T17
AutoCaptReseedCnt	174	Covered	T17
AutoDispatch	158	Covered	T17
AutoFirstAckWait	150	Covered	T17
AutoLoadIns	92	Covered	T17
AutoSendGenCmd	183	Covered	T17
AutoSendReseedCmd	195	Covered	T17
BootCaptGenCnt	108	Covered	T17
BootDone	128	Covered	T17
BootGenAckWait	118	Covered	T17
BootInsAckWait	104	Covered	T17
BootLoadGen	100	Covered	T17
BootLoadIns	90	Covered	T17
BootLoadUni	132	Covered	T17
BootPulse	123	Covered	T17
BootSendGenCmd	113	Covered	T17
BootUniAckWait	137	Covered	T17
Error	217	Covered	T17
Idle	141	Covered	T17
SWPortMode	95	Covered	T17

transitions	Line No.	Covered	Tests
AutoAckWait->AutoDispatch	164	Covered	T17
AutoAckWait->Error	217	Not Covered
AutoAckWait->Idle	241	Covered	T17
AutoCaptGenCnt->AutoSendGenCmd	183	Covered	T17
AutoCaptGenCnt->Error	217	Covered	T17
AutoCaptGenCnt->Idle	241	Covered	T17
AutoCaptReseedCnt->AutoSendReseedCmd	195	Covered	T17
AutoCaptReseedCnt->Error	217	Not Covered
AutoCaptReseedCnt->Idle	241	Covered	T17
AutoDispatch->AutoCaptGenCnt	176	Covered	T17
AutoDispatch->AutoCaptReseedCnt	174	Covered	T17
AutoDispatch->Error	217	Covered	T17
AutoDispatch->Idle	171	Covered	T17
AutoFirstAckWait->AutoDispatch	158	Covered	T17
AutoFirstAckWait->Error	217	Covered	T17
AutoFirstAckWait->Idle	241	Covered	T17
AutoLoadIns->AutoFirstAckWait	150	Covered	T17
AutoLoadIns->Error	217	Covered	T17
AutoLoadIns->Idle	241	Covered	T17
AutoSendGenCmd->AutoAckWait	189	Covered	T17
AutoSendGenCmd->Error	217	Covered	T17
AutoSendGenCmd->Idle	241	Covered	T17
AutoSendReseedCmd->AutoAckWait	201	Covered	T17
AutoSendReseedCmd->Error	217	Not Covered
AutoSendReseedCmd->Idle	241	Covered	T17
BootCaptGenCnt->BootSendGenCmd	113	Covered	T17
BootCaptGenCnt->Error	217	Covered	T17
BootCaptGenCnt->Idle	241	Covered	T17
BootDone->BootLoadUni	132	Covered	T17
BootDone->Error	217	Covered	T17
BootDone->Idle	241	Covered	T17
BootGenAckWait->BootPulse	123	Covered	T17
BootGenAckWait->Error	217	Covered	T17
BootGenAckWait->Idle	241	Covered	T17
BootInsAckWait->BootCaptGenCnt	108	Covered	T17
BootInsAckWait->Error	217	Covered	T17
BootInsAckWait->Idle	241	Covered	T17
BootLoadGen->BootInsAckWait	104	Covered	T17
BootLoadGen->Error	217	Covered	T17
BootLoadGen->Idle	241	Covered	T17
BootLoadIns->BootLoadGen	100	Covered	T17
BootLoadIns->Error	217	Covered	T17
BootLoadIns->Idle	241	Covered	T17
BootLoadUni->BootUniAckWait	137	Covered	T17
BootLoadUni->Error	217	Not Covered
BootLoadUni->Idle	241	Not Covered
BootPulse->BootDone	128	Covered	T17
BootPulse->Error	217	Not Covered
BootPulse->Idle	241	Covered	T17
BootSendGenCmd->BootGenAckWait	118	Covered	T17
BootSendGenCmd->Error	217	Not Covered
BootSendGenCmd->Idle	241	Covered	T17
BootUniAckWait->Error	217	Not Covered
BootUniAckWait->Idle	141	Covered	T17
Idle->AutoLoadIns	92	Covered	T17
Idle->BootLoadIns	90	Covered	T17
Idle->Error	217	Covered	T17
Idle->SWPortMode	95	Covered	T17
SWPortMode->Error	217	Covered	T17
SWPortMode->Idle	241	Covered	T17

---

Branch Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
Branches		42	41	97.62
IF	63	2	2	100.00
CASE	87	37	36	97.30
IF	216	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	63	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	87	case (state_q)
-2-:	89	if ((boot_req_mode_i && edn_enable_i))
-3-:	91	if ((auto_req_mode_i && edn_enable_i))
-4-:	93	if (edn_enable_i)
-5-:	107	if (csrng_cmd_ack_i)
-6-:	117	if (cmd_sent_i)
-7-:	122	if (csrng_cmd_ack_i)
-8-:	131	if ((!boot_req_mode_i))
-9-:	140	if (csrng_cmd_ack_i)
-10-:	149	if (sw_cmd_req_load_i)
-11-:	156	if (csrng_cmd_ack_i)
-12-:	163	if (csrng_cmd_ack_i)
-13-:	169	if ((!auto_req_mode_i))
-14-:	173	if (max_reqs_cnt_zero_i)
-15-:	188	if (cmd_sent_i)
-16-:	200	if (cmd_sent_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
Idle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T32,T4,T30
Idle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T10
Idle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
Idle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
BootLoadIns	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T32,T4,T30
BootLoadGen	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T32,T4,T30
BootInsAckWait	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T32,T4,T30
BootInsAckWait	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T32,T4,T30
BootCaptGenCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T32,T4,T30
BootSendGenCmd	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T32,T4,T30
BootSendGenCmd	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	Not Covered
BootGenAckWait	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	Covered	T32,T4,T30
BootGenAckWait	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	Covered	T32,T4,T30
BootPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T32,T4,T30
BootDone	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T30,T46,T45
BootDone	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T32,T78,T72
BootLoadUni	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T30,T46,T45
BootUniAckWait	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T30,T46,T45
BootUniAckWait	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T30,T46,T45
AutoLoadIns	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T1,T3,T10
AutoLoadIns	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T1,T3,T10
AutoFirstAckWait	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T1,T3,T10
AutoFirstAckWait	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T1,T3,T10
AutoAckWait	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T1,T3,T10
AutoAckWait	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T1,T3,T10
AutoDispatch	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T1,T3,T10
AutoDispatch	-	-	-	-	-	-	-	-	-	-	-	0	1	-	-	Covered	T1,T3,T10
AutoDispatch	-	-	-	-	-	-	-	-	-	-	-	0	0	-	-	Covered	T1,T3,T10
AutoCaptGenCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T10
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T1,T3,T10
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T1,T3,T10
AutoCaptReseedCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T10
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T3,T10
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T3,T10
SWPortMode	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
Error	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T7,T8
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T8,T72

	LineNo.	Expression
-1-:	216	if (local_escalate_i)
-2-:	232	if (((!edn_enable_i) && (state_q inside {BootLoadIns, BootLoadGen, BootInsAckWait, BootCaptGenCnt, BootSendGenCmd, BootGenAckWait, BootPulse, BootDone, BootLoadUni, BootUniAckWait, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T7,T8
0	1	Covered	T37,T32,T4
0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_main_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ErrorStStable_A	181491217	110049	0	0
FpvSecCmErrorStEscalate_A	181491217	110791	0	0
u_state_regs_A	181463555	181322455	0	0

ErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181491217	110049	0	0
T4	480	150	0	0
T5	190062	0	0	0
T6	1843	0	0	0
T7	1011	266	0	0
T8	0	374	0	0
T9	0	375	0	0
T13	0	1152	0	0
T15	1783	0	0	0
T29	1195	0	0	0
T33	1521	0	0	0
T49	1136	0	0	0
T70	1458	0	0	0
T72	0	300	0	0
T73	0	310	0	0
T74	0	597	0	0
T75	0	590	0	0
T76	1223	0	0	0
T94	0	270	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181491217	110791	0	0
T4	480	151	0	0
T5	190062	0	0	0
T6	1843	0	0	0
T7	1011	267	0	0
T8	0	375	0	0
T9	0	376	0	0
T13	0	1153	0	0
T15	1783	0	0	0
T29	1195	0	0	0
T33	1521	0	0	0
T49	1136	0	0	0
T70	1458	0	0	0
T72	0	301	0	0
T73	0	311	0	0
T74	0	598	0	0
T75	0	591	0	0
T76	1223	0	0	0
T94	0	271	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181463555	181322455	0	0
T1	1679	1600	0	0
T2	1555	1497	0	0
T3	218919	218859	0	0
T4	346	198	0	0
T5	190062	190050	0	0
T10	3601	3507	0	0
T29	1195	1111	0	0
T32	996	923	0	0
T37	1888	1807	0	0
T49	1136	1066	0	0