Unified Coverage Report :: Module :: edn_core

Module : edn_core

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.28	100.00	85.83			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_core.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core	95.28	100.00	85.83			100.00

---

Module Instance : tb.dut.u_edn_core

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.28	100.00	85.83			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.85	99.92	89.58	70.30	87.34	99.07	98.91

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44		83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_ep_blk[0].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
gen_ep_blk[0].u_prim_packer_fifo_ep	98.81	100.00	95.24			100.00	100.00
gen_ep_blk[1].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
gen_ep_blk[1].u_prim_packer_fifo_ep	98.81	100.00	95.24			100.00	100.00
gen_ep_blk[2].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
gen_ep_blk[2].u_prim_packer_fifo_ep	98.81	100.00	95.24			100.00	100.00
gen_ep_blk[3].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
gen_ep_blk[3].u_prim_packer_fifo_ep	98.81	100.00	95.24			100.00	100.00
gen_ep_blk[4].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
gen_ep_blk[4].u_prim_packer_fifo_ep	98.81	100.00	95.24			100.00	100.00
gen_ep_blk[5].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
gen_ep_blk[5].u_prim_packer_fifo_ep	98.81	100.00	95.24			100.00	100.00
gen_ep_blk[6].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
gen_ep_blk[6].u_prim_packer_fifo_ep	98.81	100.00	95.24			100.00	100.00
u_edn_main_sm	96.88	100.00	100.00		86.67	97.73	100.00
u_intr_hw_edn_cmd_req_done	100.00	100.00	100.00			100.00	100.00
u_intr_hw_edn_fatal_err	100.00	100.00	100.00			100.00	100.00
u_prim_arbiter_ppc_packer_arb	95.16	95.00	92.31			100.00	93.33
u_prim_count_max_reqs_cntr	70.30			70.30
u_prim_edge_detector_recov_alert	88.89	100.00	66.67			100.00
u_prim_fifo_sync_gencmd	97.12	100.00	88.46			100.00	100.00
u_prim_fifo_sync_output	91.06	100.00	69.23			95.00	100.00
u_prim_fifo_sync_rescmd	97.12	100.00	88.46			100.00	100.00
u_prim_mubi4_sync_auto_req_mode	100.00	100.00					100.00
u_prim_mubi4_sync_boot_req_mode	100.00	100.00					100.00
u_prim_mubi4_sync_cmd_fifo_rst	100.00	100.00					100.00
u_prim_mubi4_sync_edn_enable	100.00	100.00					100.00
u_prim_packer_fifo_cs	95.24	100.00	95.24			85.71	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : edn_core

	Line No.	Total	Covered	Percent
TOTAL		238	238	100.00
ALWAYS	226	29	29	100.00
CONT_ASSIGN	294	1	1	100.00
CONT_ASSIGN	299	1	1	100.00
CONT_ASSIGN	304	1	1	100.00
CONT_ASSIGN	311	1	1	100.00
CONT_ASSIGN	313	1	1	100.00
CONT_ASSIGN	315	1	1	100.00
CONT_ASSIGN	317	1	1	100.00
CONT_ASSIGN	319	1	1	100.00
CONT_ASSIGN	321	1	1	100.00
CONT_ASSIGN	324	1	1	100.00
CONT_ASSIGN	329	1	1	100.00
CONT_ASSIGN	334	1	1	100.00
CONT_ASSIGN	343	1	1	100.00
CONT_ASSIGN	346	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	352	1	1	100.00
CONT_ASSIGN	355	1	1	100.00
CONT_ASSIGN	358	1	1	100.00
CONT_ASSIGN	360	1	1	100.00
CONT_ASSIGN	361	1	1	100.00
CONT_ASSIGN	366	1	1	100.00
CONT_ASSIGN	369	1	1	100.00
CONT_ASSIGN	372	1	1	100.00
CONT_ASSIGN	377	1	1	100.00
CONT_ASSIGN	377	1	1	100.00
CONT_ASSIGN	377	1	1	100.00
CONT_ASSIGN	377	1	1	100.00
CONT_ASSIGN	377	1	1	100.00
CONT_ASSIGN	377	1	1	100.00
CONT_ASSIGN	377	1	1	100.00
CONT_ASSIGN	377	1	1	100.00
CONT_ASSIGN	377	1	1	100.00
CONT_ASSIGN	377	1	1	100.00
CONT_ASSIGN	377	1	1	100.00
CONT_ASSIGN	377	1	1	100.00
CONT_ASSIGN	377	1	1	100.00
CONT_ASSIGN	377	1	1	100.00
CONT_ASSIGN	377	1	1	100.00
CONT_ASSIGN	377	1	1	100.00
CONT_ASSIGN	377	1	1	100.00
CONT_ASSIGN	377	1	1	100.00
CONT_ASSIGN	377	1	1	100.00
CONT_ASSIGN	377	1	1	100.00
CONT_ASSIGN	377	1	1	100.00
CONT_ASSIGN	377	1	1	100.00
CONT_ASSIGN	377	1	1	100.00
CONT_ASSIGN	377	1	1	100.00
CONT_ASSIGN	377	1	1	100.00
CONT_ASSIGN	377	1	1	100.00
CONT_ASSIGN	377	1	1	100.00
CONT_ASSIGN	377	1	1	100.00
CONT_ASSIGN	377	1	1	100.00
CONT_ASSIGN	377	1	1	100.00
CONT_ASSIGN	377	1	1	100.00
CONT_ASSIGN	382	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	389	1	1	100.00
CONT_ASSIGN	398	1	1	100.00
CONT_ASSIGN	399	1	1	100.00
CONT_ASSIGN	400	1	1	100.00
CONT_ASSIGN	401	1	1	100.00
CONT_ASSIGN	404	1	1	100.00
CONT_ASSIGN	404	1	1	100.00
CONT_ASSIGN	404	1	1	100.00
CONT_ASSIGN	404	1	1	100.00
CONT_ASSIGN	404	1	1	100.00
CONT_ASSIGN	404	1	1	100.00
CONT_ASSIGN	404	1	1	100.00
CONT_ASSIGN	404	1	1	100.00
CONT_ASSIGN	404	1	1	100.00
CONT_ASSIGN	404	1	1	100.00
CONT_ASSIGN	404	1	1	100.00
CONT_ASSIGN	404	1	1	100.00
CONT_ASSIGN	404	1	1	100.00
CONT_ASSIGN	404	1	1	100.00
CONT_ASSIGN	404	1	1	100.00
CONT_ASSIGN	404	1	1	100.00
CONT_ASSIGN	404	1	1	100.00
CONT_ASSIGN	404	1	1	100.00
CONT_ASSIGN	404	1	1	100.00
CONT_ASSIGN	404	1	1	100.00
CONT_ASSIGN	404	1	1	100.00
CONT_ASSIGN	404	1	1	100.00
CONT_ASSIGN	419	1	1	100.00
CONT_ASSIGN	420	1	1	100.00
CONT_ASSIGN	421	1	1	100.00
CONT_ASSIGN	422	1	1	100.00
CONT_ASSIGN	425	1	1	100.00
CONT_ASSIGN	425	1	1	100.00
CONT_ASSIGN	425	1	1	100.00
CONT_ASSIGN	439	1	1	100.00
CONT_ASSIGN	446	1	1	100.00
CONT_ASSIGN	447	1	1	100.00
CONT_ASSIGN	448	1	1	100.00
CONT_ASSIGN	449	1	1	100.00
CONT_ASSIGN	450	1	1	100.00
CONT_ASSIGN	465	1	1	100.00
CONT_ASSIGN	466	1	1	100.00
CONT_ASSIGN	468	1	1	100.00
CONT_ASSIGN	469	1	1	100.00
CONT_ASSIGN	471	1	1	100.00
CONT_ASSIGN	472	1	1	100.00
CONT_ASSIGN	474	1	1	100.00
CONT_ASSIGN	475	1	1	100.00
CONT_ASSIGN	477	1	1	100.00
CONT_ASSIGN	484	1	1	100.00
CONT_ASSIGN	488	1	1	100.00
CONT_ASSIGN	494	1	1	100.00
CONT_ASSIGN	502	1	1	100.00
CONT_ASSIGN	503	1	1	100.00
CONT_ASSIGN	504	1	1	100.00
CONT_ASSIGN	512	1	1	100.00
CONT_ASSIGN	515	1	1	100.00
CONT_ASSIGN	516	1	1	100.00
CONT_ASSIGN	517	1	1	100.00
CONT_ASSIGN	518	1	1	100.00
CONT_ASSIGN	520	1	1	100.00
CONT_ASSIGN	548	1	1	100.00
CONT_ASSIGN	550	1	1	100.00
CONT_ASSIGN	554	1	1	100.00
CONT_ASSIGN	558	1	1	100.00
CONT_ASSIGN	560	1	1	100.00
CONT_ASSIGN	562	1	1	100.00
CONT_ASSIGN	588	1	1	100.00
CONT_ASSIGN	590	1	1	100.00
CONT_ASSIGN	595	1	1	100.00
CONT_ASSIGN	600	1	1	100.00
CONT_ASSIGN	602	1	1	100.00
CONT_ASSIGN	604	1	1	100.00
CONT_ASSIGN	630	1	1	100.00
CONT_ASSIGN	631	1	1	100.00
CONT_ASSIGN	633	1	1	100.00
CONT_ASSIGN	634	1	1	100.00
CONT_ASSIGN	635	1	1	100.00
CONT_ASSIGN	636	1	1	100.00
CONT_ASSIGN	638	1	1	100.00
CONT_ASSIGN	698	1	1	100.00
CONT_ASSIGN	702	1	1	100.00
CONT_ASSIGN	705	1	1	100.00
CONT_ASSIGN	713	1	1	100.00
CONT_ASSIGN	717	1	1	100.00
CONT_ASSIGN	718	1	1	100.00
CONT_ASSIGN	719	1	1	100.00
CONT_ASSIGN	720	1	1	100.00
CONT_ASSIGN	723	1	1	100.00
CONT_ASSIGN	759	1	1	100.00
CONT_ASSIGN	759	1	1	100.00
CONT_ASSIGN	759	1	1	100.00
CONT_ASSIGN	759	1	1	100.00
CONT_ASSIGN	759	1	1	100.00
CONT_ASSIGN	759	1	1	100.00
CONT_ASSIGN	759	1	1	100.00
CONT_ASSIGN	783	1	1	100.00
CONT_ASSIGN	784	1	1	100.00
CONT_ASSIGN	785	1	1	100.00
CONT_ASSIGN	786	1	1	100.00
CONT_ASSIGN	787	1	1	100.00
CONT_ASSIGN	788	1	1	100.00
CONT_ASSIGN	790	1	1	100.00
CONT_ASSIGN	805	1	1	100.00
CONT_ASSIGN	807	1	1	100.00
CONT_ASSIGN	809	1	1	100.00
CONT_ASSIGN	815	1	1	100.00
CONT_ASSIGN	833	1	1	100.00
CONT_ASSIGN	834	1	1	100.00
CONT_ASSIGN	858	1	1	100.00
CONT_ASSIGN	858	1	1	100.00
CONT_ASSIGN	858	1	1	100.00
CONT_ASSIGN	858	1	1	100.00
CONT_ASSIGN	858	1	1	100.00
CONT_ASSIGN	858	1	1	100.00
CONT_ASSIGN	858	1	1	100.00
CONT_ASSIGN	859	1	1	100.00
CONT_ASSIGN	859	1	1	100.00
CONT_ASSIGN	859	1	1	100.00
CONT_ASSIGN	859	1	1	100.00
CONT_ASSIGN	859	1	1	100.00
CONT_ASSIGN	859	1	1	100.00
CONT_ASSIGN	859	1	1	100.00
CONT_ASSIGN	862	1	1	100.00
CONT_ASSIGN	862	1	1	100.00
CONT_ASSIGN	862	1	1	100.00
CONT_ASSIGN	862	1	1	100.00
CONT_ASSIGN	862	1	1	100.00
CONT_ASSIGN	862	1	1	100.00
CONT_ASSIGN	862	1	1	100.00
CONT_ASSIGN	865	1	1	100.00
CONT_ASSIGN	865	1	1	100.00
CONT_ASSIGN	865	1	1	100.00
CONT_ASSIGN	865	1	1	100.00
CONT_ASSIGN	865	1	1	100.00
CONT_ASSIGN	865	1	1	100.00
CONT_ASSIGN	865	1	1	100.00
CONT_ASSIGN	868	1	1	100.00
CONT_ASSIGN	868	1	1	100.00
CONT_ASSIGN	868	1	1	100.00
CONT_ASSIGN	868	1	1	100.00
CONT_ASSIGN	868	1	1	100.00
CONT_ASSIGN	868	1	1	100.00
CONT_ASSIGN	868	1	1	100.00
CONT_ASSIGN	869	1	1	100.00
CONT_ASSIGN	869	1	1	100.00
CONT_ASSIGN	869	1	1	100.00
CONT_ASSIGN	869	1	1	100.00
CONT_ASSIGN	869	1	1	100.00
CONT_ASSIGN	869	1	1	100.00
CONT_ASSIGN	869	1	1	100.00
CONT_ASSIGN	889	1	1	100.00
CONT_ASSIGN	895	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_core.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_core.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
226	1	1
227	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
238	1	1
239	1	1
240	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
252	1	1
253	1	1
254	1	1
255	1	1
294	1	1
299	1	1
304	1	1
311	1	1
313	1	1
315	1	1
317	1	1
319	1	1
321	1	1
324	1	1
329	1	1
334	1	1
343	1	1
346	1	1
349	1	1
352	1	1
355	1	1
358	1	1
360	1	1
361	1	1
366	1	1
369	1	1
372	1	1
377	31	31
382	1	1
385	1	1
389	1	1
398	1	1
399	1	1
400	1	1
401	1	1
404	22	22
419	1	1
420	1	1
421	1	1
422	1	1
425	3	3
439	1	1
446	1	1
447	1	1
448	1	1
449	1	1
450	1	1
465	1	1
466	1	1
468	1	1
469	1	1
471	1	1
472	1	1
474	1	1
475	1	1
477	1	1
484	1	1
488	1	1
494	1	1
502	1	1
503	1	1
504	1	1
512	1	1
515	1	1
516	1	1
517	1	1
518	1	1
520	1	1
548	1	1
550	1	1
554	1	1
558	1	1
560	1	1
562	1	1
588	1	1
590	1	1
595	1	1
600	1	1
602	1	1
604	1	1
630	1	1
631	1	1
633	1	1
634	1	1
635	1	1
636	1	1
638	1	1
698	1	1
702	1	1
705	1	1
713	1	1
717	1	1
718	1	1
719	1	1
720	1	1
723	1	1
759	7	7
783	1	1
784	1	1
785	1	1
786	1	1
787	1	1
788	1	1
790	1	1
805	1	1
807	1	1
809	1	1
815	1	1
833	1	1
834	1	1
858	7	7
859	7	7
862	7	7
865	7	7
868	7	7
869	7	7
889	1	1
895	1	1

---

Cond Coverage for Module : edn_core

	Total	Covered	Percent
Conditions	501	430	85.83
Logical	501	430	85.83
Non-Logical	0	0
Event	0	0

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.

Line numbers	Percent
299-862	85.81
862-895	86.21

---

Branch Coverage for Module : edn_core

	Line No.	Total	Covered	Percent
Branches		72	72	100.00
TERNARY	477	5	5	100.00
TERNARY	484	2	2	100.00
TERNARY	488	4	4	100.00
TERNARY	494	3	3	100.00
TERNARY	504	6	6	100.00
TERNARY	520	5	5	100.00
TERNARY	550	2	2	100.00
TERNARY	554	2	2	100.00
TERNARY	590	3	3	100.00
TERNARY	595	3	3	100.00
TERNARY	705	6	6	100.00
TERNARY	790	3	3	100.00
TERNARY	807	2	2	100.00
TERNARY	809	3	3	100.00
TERNARY	862	3	3	100.00
TERNARY	862	3	3	100.00
TERNARY	862	3	3	100.00
TERNARY	862	3	3	100.00
TERNARY	862	3	3	100.00
TERNARY	862	3	3	100.00
TERNARY	862	3	3	100.00
IF	226	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_core.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_core.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	477	((!edn_enable_fo[CsrngCmdReq])) ? 
-2-:	477	(boot_wr_cmd_reg) ? 
-3-:	477	(sw_cmd_req_load) ? 
-4-:	477	(boot_wr_cmd_uni) ? 

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Covered	T32,T4,T30
0	0	1	-	Covered	T1,T2,T3
0	0	0	1	Covered	T30,T46,T45
0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	484	((!edn_enable_fo[CsrngCmdReqValid])) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	488	((!edn_enable_fo[CsrngCmdReqOut])) ? 
-2-:	488	(send_rescmd) ? 
-3-:	488	((send_gencmd || boot_send_gencmd)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T10
0	0	1	Covered	T1,T3,T10
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	494	((!edn_enable_fo[CsrngCmdReqValidOut])) ? 
-2-:	494	(((send_rescmd || send_gencmd) || (boot_send_gencmd && cmd_sent))) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T3,T10
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	504	((!edn_enable_q)) ? 
-2-:	504	(sw_cmd_req_load) ? 
-3-:	504	(auto_first_ack_wait) ? 
-4-:	504	(main_sm_busy) ? 
-5-:	504	(csrng_cmd_i.csrng_req_ready) ? 

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T1,T2,T3
0	0	1	-	-	Covered	T1,T3,T10
0	0	0	1	-	Covered	T1,T3,T10
0	0	0	0	1	Covered	T1,T2,T3
0	0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	520	((!edn_enable_fo[IntrStatus])) ? 
-2-:	520	(main_sm_done_pulse) ? 
-3-:	520	(auto_set_intr_gate) ? 
-4-:	520	(auto_clr_intr_gate) ? 

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Covered	T1,T2,T3
0	0	1	-	Covered	T1,T3,T10
0	0	0	1	Covered	T1,T3,T10
0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	550	((send_rescmd_q & edn_enable_fo[SendReseedCmd])) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	554	(auto_req_mode_busy) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	590	((boot_wr_cmd_genfifo & edn_enable_fo[SendGenCmd])) ? 
-2-:	590	((send_gencmd_q & edn_enable_fo[SendGenCmd])) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T32,T4,T30
0	1	Covered	T1,T3,T10
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	595	(boot_wr_cmd_genfifo) ? 
-2-:	595	(auto_req_mode_busy) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T32,T4,T30
0	1	Covered	T1,T3,T10
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	705	((!edn_enable_fo[CmdFifoCnt])) ? 
-2-:	705	((cmd_fifo_rst_fo[3] || main_sm_done_pulse)) ? 
-3-:	705	(capt_gencmd_fifo_cnt) ? 
-4-:	705	(capt_rescmd_fifo_cnt) ? 
-5-:	705	(((send_gencmd || boot_send_gencmd) || send_rescmd)) ? 

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T1,T2,T3
0	0	1	-	-	Covered	T1,T3,T10
0	0	0	1	-	Covered	T1,T3,T10
0	0	0	0	1	Covered	T1,T3,T10
0	0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	790	((!edn_enable_fo[CsrngFipsEn])) ? 
-2-:	790	((packer_cs_push && packer_cs_wready)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	807	(cs_rdata_capt_vld) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	809	((!edn_enable_fo[CsrngDataVld])) ? 
-2-:	809	(cs_rdata_capt_vld) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	862	(packer_ep_clr[0]) ? 
-2-:	862	((packer_ep_push[0] && packer_ep_wready[0])) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T3,T5
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	862	(packer_ep_clr[1]) ? 
-2-:	862	((packer_ep_push[1] && packer_ep_wready[1])) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T29,T34
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	862	(packer_ep_clr[2]) ? 
-2-:	862	((packer_ep_push[2] && packer_ep_wready[2])) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T10,T30,T31
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	862	(packer_ep_clr[3]) ? 
-2-:	862	((packer_ep_push[3] && packer_ep_wready[3])) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T32,T33,T34
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	862	(packer_ep_clr[4]) ? 
-2-:	862	((packer_ep_push[4] && packer_ep_wready[4])) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T35,T36,T45
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	862	(packer_ep_clr[5]) ? 
-2-:	862	((packer_ep_push[5] && packer_ep_wready[5])) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T37,T33,T34
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	862	(packer_ep_clr[6]) ? 
-2-:	862	((packer_ep_push[6] && packer_ep_wready[6])) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T30,T35,T38
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	226	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3