Unified Coverage Report :: Module :: edn_ack_sm

Module : edn_ack_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.28	100.00	85.83			100.00		u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.28	100.00	85.83			100.00		u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.28	100.00	85.83			100.00		u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.28	100.00	85.83			100.00		u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.28	100.00	85.83			100.00		u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.28	100.00	85.83			100.00		u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.28	100.00	85.83			100.00		u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_ack_sm

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T37,T32,T4

---

FSM Coverage for Module : edn_ack_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T17
DataWait	75	Covered	T17
Disabled	107	Covered	T17
EndPointClear	63	Covered	T17
Error	99	Covered	T17
Idle	68	Covered	T17

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T17
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T17
DataWait->AckPls	80	Covered	T17
DataWait->Disabled	107	Covered	T17
DataWait->Error	99	Covered	T17
Disabled->EndPointClear	63	Covered	T17
Disabled->Error	99	Covered	T17
EndPointClear->Disabled	107	Covered	T17
EndPointClear->Error	99	Covered	T17
EndPointClear->Idle	68	Covered	T17
Idle->DataWait	75	Covered	T17
Idle->Disabled	107	Covered	T17
Idle->Error	99	Covered	T17

---

Branch Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T1,T2,T3
Idle	-	1	0	-	Covered	T1,T2,T3
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T1,T2,T3
DataWait	-	-	-	0	Covered	T1,T2,T3
AckPls	-	-	-	-	Covered	T1,T2,T3
Error	-	-	-	-	Covered	T4,T7,T8
default	-	-	-	-	Covered	T9,T94,T14

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T7,T8
0	1	Covered	T37,T32,T4
0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_ack_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	1270438519	782943	0	0
FpvSecCmErrorStEscalate_A	1270438519	788137	0	0
u_state_regs_A	1270410857	1269423157	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1270438519	782943	0	0
T4	3360	1400	0	0
T5	1330434	0	0	0
T6	12901	0	0	0
T7	7077	1862	0	0
T8	0	2968	0	0
T9	0	2575	0	0
T13	0	8064	0	0
T15	12481	0	0	0
T29	8365	0	0	0
T33	10647	0	0	0
T49	7952	0	0	0
T70	10206	0	0	0
T72	0	2450	0	0
T73	0	2520	0	0
T74	0	4529	0	0
T75	0	4480	0	0
T76	8561	0	0	0
T94	0	1840	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1270438519	788137	0	0
T4	3360	1407	0	0
T5	1330434	0	0	0
T6	12901	0	0	0
T7	7077	1869	0	0
T8	0	2975	0	0
T9	0	2582	0	0
T13	0	8071	0	0
T15	12481	0	0	0
T29	8365	0	0	0
T33	10647	0	0	0
T49	7952	0	0	0
T70	10206	0	0	0
T72	0	2457	0	0
T73	0	2527	0	0
T74	0	4536	0	0
T75	0	4487	0	0
T76	8561	0	0	0
T94	0	1847	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1270410857	1269423157	0	0
T1	11753	11200	0	0
T2	10885	10479	0	0
T3	1532433	1532013	0	0
T4	3226	2190	0	0
T5	1330434	1330350	0	0
T10	25207	24549	0	0
T29	8365	7777	0	0
T32	6972	6461	0	0
T37	13216	12649	0	0
T49	7952	7462	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T37,T32,T4

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T17
DataWait	75	Covered	T17
Disabled	107	Covered	T17
EndPointClear	63	Covered	T17
Error	99	Covered	T17
Idle	68	Covered	T17

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T17
DataWait->AckPls	80	Covered	T17
DataWait->Disabled	107	Covered	T17
DataWait->Error	99	Covered	T17
Disabled->EndPointClear	63	Covered	T17
Disabled->Error	99	Covered	T17
EndPointClear->Disabled	107	Covered	T17
EndPointClear->Error	99	Covered	T17
EndPointClear->Idle	68	Covered	T17
Idle->DataWait	75	Covered	T17
Idle->Disabled	107	Covered	T17
Idle->Error	99	Covered	T17

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T2,T29,T34
Idle	-	1	0	-	Covered	T2,T4,T29
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T2,T29,T34
DataWait	-	-	-	0	Covered	T2,T4,T29
AckPls	-	-	-	-	Covered	T2,T29,T34
Error	-	-	-	-	Covered	T4,T7,T8
default	-	-	-	-	Covered	T14,T27,T28

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T7,T8
0	1	Covered	T37,T32,T4
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	181491217	112099	0	0
FpvSecCmErrorStEscalate_A	181491217	112841	0	0
u_state_regs_A	181491217	181350117	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181491217	112099	0	0
T4	480	200	0	0
T5	190062	0	0	0
T6	1843	0	0	0
T7	1011	266	0	0
T8	0	424	0	0
T9	0	375	0	0
T13	0	1152	0	0
T15	1783	0	0	0
T29	1195	0	0	0
T33	1521	0	0	0
T49	1136	0	0	0
T70	1458	0	0	0
T72	0	350	0	0
T73	0	360	0	0
T74	0	647	0	0
T75	0	640	0	0
T76	1223	0	0	0
T94	0	270	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181491217	112841	0	0
T4	480	201	0	0
T5	190062	0	0	0
T6	1843	0	0	0
T7	1011	267	0	0
T8	0	425	0	0
T9	0	376	0	0
T13	0	1153	0	0
T15	1783	0	0	0
T29	1195	0	0	0
T33	1521	0	0	0
T49	1136	0	0	0
T70	1458	0	0	0
T72	0	351	0	0
T73	0	361	0	0
T74	0	648	0	0
T75	0	641	0	0
T76	1223	0	0	0
T94	0	271	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181491217	181350117	0	0
T1	1679	1600	0	0
T2	1555	1497	0	0
T3	218919	218859	0	0
T4	480	332	0	0
T5	190062	190050	0	0
T10	3601	3507	0	0
T29	1195	1111	0	0
T32	996	923	0	0
T37	1888	1807	0	0
T49	1136	1066	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T37,T32,T4

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T17
DataWait	75	Covered	T17
Disabled	107	Covered	T17
EndPointClear	63	Covered	T17
Error	99	Covered	T17
Idle	68	Covered	T17

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T17
DataWait->AckPls	80	Covered	T17
DataWait->Disabled	107	Covered	T17
DataWait->Error	99	Covered	T17
Disabled->EndPointClear	63	Covered	T17
Disabled->Error	99	Covered	T17
EndPointClear->Disabled	107	Covered	T17
EndPointClear->Error	99	Covered	T17
EndPointClear->Idle	68	Covered	T17
Idle->DataWait	75	Covered	T17
Idle->Disabled	107	Covered	T17
Idle->Error	99	Covered	T17

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T10,T30,T31
Idle	-	1	0	-	Covered	T10,T30,T31
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T10,T30,T31
DataWait	-	-	-	0	Covered	T10,T30,T31
AckPls	-	-	-	-	Covered	T10,T30,T31
Error	-	-	-	-	Covered	T4,T7,T8
default	-	-	-	-	Covered	T14,T27,T28

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T7,T8
0	1	Covered	T37,T32,T4
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	181491217	112099	0	0
FpvSecCmErrorStEscalate_A	181491217	112841	0	0
u_state_regs_A	181491217	181350117	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181491217	112099	0	0
T4	480	200	0	0
T5	190062	0	0	0
T6	1843	0	0	0
T7	1011	266	0	0
T8	0	424	0	0
T9	0	375	0	0
T13	0	1152	0	0
T15	1783	0	0	0
T29	1195	0	0	0
T33	1521	0	0	0
T49	1136	0	0	0
T70	1458	0	0	0
T72	0	350	0	0
T73	0	360	0	0
T74	0	647	0	0
T75	0	640	0	0
T76	1223	0	0	0
T94	0	270	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181491217	112841	0	0
T4	480	201	0	0
T5	190062	0	0	0
T6	1843	0	0	0
T7	1011	267	0	0
T8	0	425	0	0
T9	0	376	0	0
T13	0	1153	0	0
T15	1783	0	0	0
T29	1195	0	0	0
T33	1521	0	0	0
T49	1136	0	0	0
T70	1458	0	0	0
T72	0	351	0	0
T73	0	361	0	0
T74	0	648	0	0
T75	0	641	0	0
T76	1223	0	0	0
T94	0	271	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181491217	181350117	0	0
T1	1679	1600	0	0
T2	1555	1497	0	0
T3	218919	218859	0	0
T4	480	332	0	0
T5	190062	190050	0	0
T10	3601	3507	0	0
T29	1195	1111	0	0
T32	996	923	0	0
T37	1888	1807	0	0
T49	1136	1066	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T37,T32,T4

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T17
DataWait	75	Covered	T17
Disabled	107	Covered	T17
EndPointClear	63	Covered	T17
Error	99	Covered	T17
Idle	68	Covered	T17

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T17
DataWait->AckPls	80	Covered	T17
DataWait->Disabled	107	Covered	T17
DataWait->Error	99	Covered	T17
Disabled->EndPointClear	63	Covered	T17
Disabled->Error	99	Covered	T17
EndPointClear->Disabled	107	Covered	T17
EndPointClear->Error	99	Covered	T17
EndPointClear->Idle	68	Covered	T17
Idle->DataWait	75	Covered	T17
Idle->Disabled	107	Covered	T17
Idle->Error	99	Covered	T17

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T35,T36,T45
Idle	-	1	0	-	Covered	T35,T9,T36
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T35,T36,T45
DataWait	-	-	-	0	Covered	T35,T9,T36
AckPls	-	-	-	-	Covered	T35,T36,T45
Error	-	-	-	-	Covered	T4,T7,T8
default	-	-	-	-	Covered	T14,T27,T28

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T7,T8
0	1	Covered	T37,T32,T4
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	181491217	112099	0	0
FpvSecCmErrorStEscalate_A	181491217	112841	0	0
u_state_regs_A	181491217	181350117	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181491217	112099	0	0
T4	480	200	0	0
T5	190062	0	0	0
T6	1843	0	0	0
T7	1011	266	0	0
T8	0	424	0	0
T9	0	375	0	0
T13	0	1152	0	0
T15	1783	0	0	0
T29	1195	0	0	0
T33	1521	0	0	0
T49	1136	0	0	0
T70	1458	0	0	0
T72	0	350	0	0
T73	0	360	0	0
T74	0	647	0	0
T75	0	640	0	0
T76	1223	0	0	0
T94	0	270	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181491217	112841	0	0
T4	480	201	0	0
T5	190062	0	0	0
T6	1843	0	0	0
T7	1011	267	0	0
T8	0	425	0	0
T9	0	376	0	0
T13	0	1153	0	0
T15	1783	0	0	0
T29	1195	0	0	0
T33	1521	0	0	0
T49	1136	0	0	0
T70	1458	0	0	0
T72	0	351	0	0
T73	0	361	0	0
T74	0	648	0	0
T75	0	641	0	0
T76	1223	0	0	0
T94	0	271	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181491217	181350117	0	0
T1	1679	1600	0	0
T2	1555	1497	0	0
T3	218919	218859	0	0
T4	480	332	0	0
T5	190062	190050	0	0
T10	3601	3507	0	0
T29	1195	1111	0	0
T32	996	923	0	0
T37	1888	1807	0	0
T49	1136	1066	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T37,T32,T4

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T17
DataWait	75	Covered	T17
Disabled	107	Covered	T17
EndPointClear	63	Covered	T17
Error	99	Covered	T17
Idle	68	Covered	T17

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T17
DataWait->AckPls	80	Covered	T17
DataWait->Disabled	107	Covered	T17
DataWait->Error	99	Covered	T17
Disabled->EndPointClear	63	Covered	T17
Disabled->Error	99	Covered	T17
EndPointClear->Disabled	107	Covered	T17
EndPointClear->Error	99	Covered	T17
EndPointClear->Idle	68	Covered	T17
Idle->DataWait	75	Covered	T17
Idle->Disabled	107	Covered	T17
Idle->Error	99	Covered	T17

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T37,T33,T34
Idle	-	1	0	-	Covered	T37,T33,T34
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T37,T33,T34
DataWait	-	-	-	0	Covered	T37,T33,T34
AckPls	-	-	-	-	Covered	T37,T33,T34
Error	-	-	-	-	Covered	T4,T7,T8
default	-	-	-	-	Covered	T14,T27,T28

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T7,T8
0	1	Covered	T37,T32,T4
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	181491217	112099	0	0
FpvSecCmErrorStEscalate_A	181491217	112841	0	0
u_state_regs_A	181491217	181350117	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181491217	112099	0	0
T4	480	200	0	0
T5	190062	0	0	0
T6	1843	0	0	0
T7	1011	266	0	0
T8	0	424	0	0
T9	0	375	0	0
T13	0	1152	0	0
T15	1783	0	0	0
T29	1195	0	0	0
T33	1521	0	0	0
T49	1136	0	0	0
T70	1458	0	0	0
T72	0	350	0	0
T73	0	360	0	0
T74	0	647	0	0
T75	0	640	0	0
T76	1223	0	0	0
T94	0	270	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181491217	112841	0	0
T4	480	201	0	0
T5	190062	0	0	0
T6	1843	0	0	0
T7	1011	267	0	0
T8	0	425	0	0
T9	0	376	0	0
T13	0	1153	0	0
T15	1783	0	0	0
T29	1195	0	0	0
T33	1521	0	0	0
T49	1136	0	0	0
T70	1458	0	0	0
T72	0	351	0	0
T73	0	361	0	0
T74	0	648	0	0
T75	0	641	0	0
T76	1223	0	0	0
T94	0	271	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181491217	181350117	0	0
T1	1679	1600	0	0
T2	1555	1497	0	0
T3	218919	218859	0	0
T4	480	332	0	0
T5	190062	190050	0	0
T10	3601	3507	0	0
T29	1195	1111	0	0
T32	996	923	0	0
T37	1888	1807	0	0
T49	1136	1066	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T37,T32,T4

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T17
DataWait	75	Covered	T17
Disabled	107	Covered	T17
EndPointClear	63	Covered	T17
Error	99	Covered	T17
Idle	68	Covered	T17

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T17
DataWait->AckPls	80	Covered	T17
DataWait->Disabled	107	Covered	T17
DataWait->Error	99	Covered	T17
Disabled->EndPointClear	63	Covered	T17
Disabled->Error	99	Covered	T17
EndPointClear->Disabled	107	Covered	T17
EndPointClear->Error	99	Covered	T17
EndPointClear->Idle	68	Covered	T17
Idle->DataWait	75	Covered	T17
Idle->Disabled	107	Covered	T17
Idle->Error	99	Covered	T17

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T30,T35,T38
Idle	-	1	0	-	Covered	T30,T35,T38
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T30,T35,T38
DataWait	-	-	-	0	Covered	T30,T35,T38
AckPls	-	-	-	-	Covered	T30,T35,T38
Error	-	-	-	-	Covered	T4,T7,T8
default	-	-	-	-	Covered	T14,T27,T28

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T7,T8
0	1	Covered	T37,T32,T4
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	181491217	112099	0	0
FpvSecCmErrorStEscalate_A	181491217	112841	0	0
u_state_regs_A	181491217	181350117	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181491217	112099	0	0
T4	480	200	0	0
T5	190062	0	0	0
T6	1843	0	0	0
T7	1011	266	0	0
T8	0	424	0	0
T9	0	375	0	0
T13	0	1152	0	0
T15	1783	0	0	0
T29	1195	0	0	0
T33	1521	0	0	0
T49	1136	0	0	0
T70	1458	0	0	0
T72	0	350	0	0
T73	0	360	0	0
T74	0	647	0	0
T75	0	640	0	0
T76	1223	0	0	0
T94	0	270	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181491217	112841	0	0
T4	480	201	0	0
T5	190062	0	0	0
T6	1843	0	0	0
T7	1011	267	0	0
T8	0	425	0	0
T9	0	376	0	0
T13	0	1153	0	0
T15	1783	0	0	0
T29	1195	0	0	0
T33	1521	0	0	0
T49	1136	0	0	0
T70	1458	0	0	0
T72	0	351	0	0
T73	0	361	0	0
T74	0	648	0	0
T75	0	641	0	0
T76	1223	0	0	0
T94	0	271	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181491217	181350117	0	0
T1	1679	1600	0	0
T2	1555	1497	0	0
T3	218919	218859	0	0
T4	480	332	0	0
T5	190062	190050	0	0
T10	3601	3507	0	0
T29	1195	1111	0	0
T32	996	923	0	0
T37	1888	1807	0	0
T49	1136	1066	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T37,T32,T4

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T17
DataWait	75	Covered	T17
Disabled	107	Covered	T17
EndPointClear	63	Covered	T17
Error	99	Covered	T17
Idle	68	Covered	T17

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T17
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T17
DataWait->AckPls	80	Covered	T17
DataWait->Disabled	107	Covered	T17
DataWait->Error	99	Covered	T17
Disabled->EndPointClear	63	Covered	T17
Disabled->Error	99	Covered	T17
EndPointClear->Disabled	107	Covered	T17
EndPointClear->Error	99	Covered	T17
EndPointClear->Idle	68	Covered	T17
Idle->DataWait	75	Covered	T17
Idle->Disabled	107	Covered	T17
Idle->Error	99	Covered	T17

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T1,T3,T5
Idle	-	1	0	-	Covered	T1,T3,T5
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T1,T3,T5
DataWait	-	-	-	0	Covered	T1,T3,T5
AckPls	-	-	-	-	Covered	T1,T3,T5
Error	-	-	-	-	Covered	T4,T7,T8
default	-	-	-	-	Covered	T9,T94,T14

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T7,T8
0	1	Covered	T37,T32,T4
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	181491217	110349	0	0
FpvSecCmErrorStEscalate_A	181491217	111091	0	0
u_state_regs_A	181463555	181322455	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181491217	110349	0	0
T4	480	200	0	0
T5	190062	0	0	0
T6	1843	0	0	0
T7	1011	266	0	0
T8	0	424	0	0
T9	0	325	0	0
T13	0	1152	0	0
T15	1783	0	0	0
T29	1195	0	0	0
T33	1521	0	0	0
T49	1136	0	0	0
T70	1458	0	0	0
T72	0	350	0	0
T73	0	360	0	0
T74	0	647	0	0
T75	0	640	0	0
T76	1223	0	0	0
T94	0	220	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181491217	111091	0	0
T4	480	201	0	0
T5	190062	0	0	0
T6	1843	0	0	0
T7	1011	267	0	0
T8	0	425	0	0
T9	0	326	0	0
T13	0	1153	0	0
T15	1783	0	0	0
T29	1195	0	0	0
T33	1521	0	0	0
T49	1136	0	0	0
T70	1458	0	0	0
T72	0	351	0	0
T73	0	361	0	0
T74	0	648	0	0
T75	0	641	0	0
T76	1223	0	0	0
T94	0	221	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181463555	181322455	0	0
T1	1679	1600	0	0
T2	1555	1497	0	0
T3	218919	218859	0	0
T4	346	198	0	0
T5	190062	190050	0	0
T10	3601	3507	0	0
T29	1195	1111	0	0
T32	996	923	0	0
T37	1888	1807	0	0
T49	1136	1066	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T37,T32,T4

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T17
DataWait	75	Covered	T17
Disabled	107	Covered	T17
EndPointClear	63	Covered	T17
Error	99	Covered	T17
Idle	68	Covered	T17

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T17
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T17
DataWait->AckPls	80	Covered	T17
DataWait->Disabled	107	Covered	T17
DataWait->Error	99	Covered	T17
Disabled->EndPointClear	63	Covered	T17
Disabled->Error	99	Covered	T17
EndPointClear->Disabled	107	Covered	T17
EndPointClear->Error	99	Covered	T17
EndPointClear->Idle	68	Covered	T17
Idle->DataWait	75	Covered	T17
Idle->Disabled	107	Covered	T17
Idle->Error	99	Covered	T17

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T1,T2,T3
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T1,T2,T3
Idle	-	1	1	-	Covered	T32,T33,T34
Idle	-	1	0	-	Covered	T32,T33,T34
Idle	-	0	-	-	Covered	T1,T2,T3
DataWait	-	-	-	1	Covered	T32,T33,T34
DataWait	-	-	-	0	Covered	T32,T33,T34
AckPls	-	-	-	-	Covered	T32,T33,T34
Error	-	-	-	-	Covered	T4,T7,T8
default	-	-	-	-	Covered	T14,T27,T28

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T7,T8
0	1	Covered	T37,T32,T4
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	181491217	112099	0	0
FpvSecCmErrorStEscalate_A	181491217	112841	0	0
u_state_regs_A	181491217	181350117	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181491217	112099	0	0
T4	480	200	0	0
T5	190062	0	0	0
T6	1843	0	0	0
T7	1011	266	0	0
T8	0	424	0	0
T9	0	375	0	0
T13	0	1152	0	0
T15	1783	0	0	0
T29	1195	0	0	0
T33	1521	0	0	0
T49	1136	0	0	0
T70	1458	0	0	0
T72	0	350	0	0
T73	0	360	0	0
T74	0	647	0	0
T75	0	640	0	0
T76	1223	0	0	0
T94	0	270	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181491217	112841	0	0
T4	480	201	0	0
T5	190062	0	0	0
T6	1843	0	0	0
T7	1011	267	0	0
T8	0	425	0	0
T9	0	376	0	0
T13	0	1153	0	0
T15	1783	0	0	0
T29	1195	0	0	0
T33	1521	0	0	0
T49	1136	0	0	0
T70	1458	0	0	0
T72	0	351	0	0
T73	0	361	0	0
T74	0	648	0	0
T75	0	641	0	0
T76	1223	0	0	0
T94	0	271	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	181491217	181350117	0	0
T1	1679	1600	0	0
T2	1555	1497	0	0
T3	218919	218859	0	0
T4	480	332	0	0
T5	190062	190050	0	0
T10	3601	3507	0	0
T29	1195	1111	0	0
T32	996	923	0	0
T37	1888	1807	0	0
T49	1136	1066	0	0