Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.59		83.33	100.00			67.44	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	197172624	9058307	0	0
boot_gen_cmd_rd_A	197172624	47960	0	0
boot_ins_cmd_rd_A	197172624	56861	0	0
ctrl_rd_A	197172624	50012	0	0
err_code_test_rd_A	197172624	49150	0	0
intr_enable_rd_A	197172624	56758	0	0
max_num_reqs_between_reseeds_rd_A	197172624	57078	0	0
regwen_rd_A	197172624	57949	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197172624	9058307	0	0
T26	2802	41	0	0
T27	1870	0	0	0
T28	863	0	0	0
T29	4204	8	0	0
T30	0	76	0	0
T49	855	0	0	0
T51	1203	0	0	0
T84	832	0	0	0
T85	1362	0	0	0
T86	2522	0	0	0
T145	0	617	0	0
T146	0	12	0	0
T147	0	4	0	0
T148	0	516	0	0
T149	0	136	0	0
T150	0	13	0	0
T151	0	11	0	0
T152	1271	0	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197172624	47960	0	0
T26	2802	7	0	0
T27	1870	0	0	0
T28	863	0	0	0
T29	4204	0	0	0
T30	0	9	0	0
T49	855	0	0	0
T51	1203	0	0	0
T84	832	0	0	0
T85	1362	0	0	0
T86	2522	35	0	0
T148	0	14	0	0
T151	0	9	0	0
T152	1271	0	0	0
T153	0	28	0	0
T154	0	21	0	0
T155	0	17	0	0
T156	0	19	0	0
T157	0	4	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197172624	56861	0	0
T26	2802	14	0	0
T27	1870	0	0	0
T28	863	0	0	0
T29	4204	0	0	0
T30	0	11	0	0
T49	855	0	0	0
T51	1203	0	0	0
T84	832	0	0	0
T85	1362	0	0	0
T86	2522	31	0	0
T148	0	18	0	0
T151	0	5	0	0
T152	1271	0	0	0
T153	0	4	0	0
T154	0	4	0	0
T155	0	7	0	0
T158	0	13	0	0
T159	0	2	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197172624	50012	0	0
T26	2802	12	0	0
T27	1870	0	0	0
T28	863	0	0	0
T29	4204	0	0	0
T30	0	16	0	0
T49	855	0	0	0
T51	1203	0	0	0
T84	832	0	0	0
T85	1362	0	0	0
T86	2522	29	0	0
T148	0	11	0	0
T151	0	4	0	0
T152	1271	0	0	0
T153	0	77	0	0
T154	0	22	0	0
T156	0	42	0	0
T157	0	14	0	0
T159	0	5	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197172624	49150	0	0
T26	2802	10	0	0
T27	1870	0	0	0
T28	863	0	0	0
T29	4204	0	0	0
T30	0	26	0	0
T49	855	0	0	0
T51	1203	0	0	0
T84	832	0	0	0
T85	1362	0	0	0
T86	2522	28	0	0
T146	0	5	0	0
T148	0	17	0	0
T151	0	7	0	0
T152	1271	0	0	0
T153	0	32	0	0
T154	0	12	0	0
T158	0	33	0	0
T159	0	4	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197172624	56758	0	0
T26	2802	15	0	0
T27	1870	0	0	0
T28	863	0	0	0
T29	4204	33	0	0
T30	0	32	0	0
T49	855	2	0	0
T50	0	13	0	0
T51	1203	0	0	0
T84	832	0	0	0
T85	1362	0	0	0
T86	2522	9	0	0
T146	0	118	0	0
T152	1271	6	0	0
T160	0	9	0	0
T161	0	7	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197172624	57078	0	0
T26	2802	17	0	0
T27	1870	0	0	0
T28	863	0	0	0
T29	4204	50	0	0
T30	0	26	0	0
T49	855	0	0	0
T51	1203	0	0	0
T84	832	0	0	0
T85	1362	0	0	0
T86	2522	23	0	0
T146	0	85	0	0
T148	0	4	0	0
T152	1271	8	0	0
T160	0	6	0	0
T162	0	350	0	0
T163	0	13	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	197172624	57949	0	0
T26	2802	18	0	0
T27	1870	0	0	0
T28	863	0	0	0
T29	4204	28	0	0
T30	0	18	0	0
T49	855	0	0	0
T51	1203	0	0	0
T84	832	0	0	0
T85	1362	0	0	0
T86	2522	2	0	0
T146	0	78	0	0
T148	0	13	0	0
T152	1271	11	0	0
T160	0	2	0	0
T162	0	330	0	0
T163	0	8	0	0