Unified Coverage Report :: Module :: edn_main_sm

Module : edn_main_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.52	100.00	100.00		90.00	97.62	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_edn_main_sm	97.52	100.00	100.00		90.00	97.62	100.00

---

Module Instance : tb.dut.u_edn_core.u_edn_main_sm

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.52	100.00	100.00		90.00	97.62	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.55	100.00	100.00		90.00	97.73	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.13	100.00	85.39			100.00		u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
TOTAL		109	109	100.00
ALWAYS	60	3	3	100.00
CONT_ASSIGN	62	1	1	100.00
ALWAYS	65	105	105	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	3	3
62	1	1
65	1	1
66	1	1
67	1	1
68	1	1
69	1	1
70	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
77	1	1
78	1	1
79	1	1
81	1	1
82	1	1
83	1	1
84	1	1
85	1	1
86	1	1
87	1	1
88	1	1
89	1	1
90	1	1
91	1	1
			MISSING_ELSE
95	1	1
96	1	1
99	1	1
100	1	1
103	1	1
104	1	1
			MISSING_ELSE
108	1	1
109	1	1
112	1	1
113	1	1
114	1	1
			==> MISSING_ELSE
118	1	1
119	1	1
			MISSING_ELSE
123	1	1
124	1	1
127	1	1
128	1	1
			MISSING_ELSE
132	1	1
133	1	1
136	1	1
137	1	1
			MISSING_ELSE
142	1	1
143	1	1
144	1	1
			MISSING_ELSE
148	1	1
149	1	1
150	1	1
			MISSING_ELSE
154	1	1
155	1	1
156	1	1
			MISSING_ELSE
160	1	1
161	1	1
162	1	1
163	1	1
165	1	1
166	1	1
168	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
180	1	1
181	1	1
			MISSING_ELSE
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
			MISSING_ELSE
197	1	1
200	1	1
208	1	1
209	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
221	1	1
222	1	1
231	1	1
233	1	1
234	1	1
235	1	1
236	1	1
237	1	1
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_main_sm

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (boot_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T108,T106,T36
1	1	Covered	T34,T108,T106

 LINE       83
 EXPRESSION (auto_req_mode_i && edn_enable_i)
             -------1-------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T10,T11,T48
1	1	Covered	T3,T10,T11

 LINE       222
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_i)) && 
      2  (state_q inside {BootLoadIns, BootLoadGen, BootInsAckWait, BootCaptGenCnt, BootSendGenCmd, BootGenAckWait, BootPulse, BootDone, BootLoadUni, BootUniAckWait, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode}))

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T10,T108,T11

---

FSM Coverage for Module : edn_main_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	21	21	100.00	(Not included in score)
Transitions	60	54	90.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AutoAckWait	181	Covered	T24
AutoCaptGenCnt	168	Covered	T24
AutoCaptReseedCnt	166	Covered	T24
AutoDispatch	150	Covered	T24
AutoFirstAckWait	144	Covered	T24
AutoLoadIns	86	Covered	T24
AutoSendGenCmd	175	Covered	T24
AutoSendReseedCmd	187	Covered	T24
BootCaptGenCnt	104	Covered	T24
BootDone	124	Covered	T24
BootGenAckWait	114	Covered	T24
BootInsAckWait	100	Covered	T24
BootLoadGen	96	Covered	T24
BootLoadIns	82	Covered	T24
BootLoadUni	128	Covered	T24
BootPulse	119	Covered	T24
BootSendGenCmd	109	Covered	T24
BootUniAckWait	133	Covered	T24
Error	209	Covered	T24
Idle	137	Covered	T24
SWPortMode	91	Covered	T24

transitions	Line No.	Covered	Tests
AutoAckWait->AutoDispatch	156	Covered	T24
AutoAckWait->Error	209	Not Covered
AutoAckWait->Idle	231	Covered	T24
AutoCaptGenCnt->AutoSendGenCmd	175	Covered	T24
AutoCaptGenCnt->Error	209	Covered	T24
AutoCaptGenCnt->Idle	231	Covered	T24
AutoCaptReseedCnt->AutoSendReseedCmd	187	Covered	T24
AutoCaptReseedCnt->Error	209	Not Covered
AutoCaptReseedCnt->Idle	231	Covered	T24
AutoDispatch->AutoCaptGenCnt	168	Covered	T24
AutoDispatch->AutoCaptReseedCnt	166	Covered	T24
AutoDispatch->Error	209	Covered	T24
AutoDispatch->Idle	163	Covered	T24
AutoFirstAckWait->AutoDispatch	150	Covered	T24
AutoFirstAckWait->Error	209	Covered	T24
AutoFirstAckWait->Idle	231	Covered	T24
AutoLoadIns->AutoFirstAckWait	144	Covered	T24
AutoLoadIns->Error	209	Covered	T24
AutoLoadIns->Idle	231	Covered	T24
AutoSendGenCmd->AutoAckWait	181	Covered	T24
AutoSendGenCmd->Error	209	Covered	T24
AutoSendGenCmd->Idle	231	Covered	T24
AutoSendReseedCmd->AutoAckWait	193	Covered	T24
AutoSendReseedCmd->Error	209	Not Covered
AutoSendReseedCmd->Idle	231	Covered	T24
BootCaptGenCnt->BootSendGenCmd	109	Covered	T24
BootCaptGenCnt->Error	209	Covered	T24
BootCaptGenCnt->Idle	231	Covered	T24
BootDone->BootLoadUni	128	Covered	T24
BootDone->Error	209	Covered	T24
BootDone->Idle	231	Covered	T24
BootGenAckWait->BootPulse	119	Covered	T24
BootGenAckWait->Error	209	Covered	T24
BootGenAckWait->Idle	231	Covered	T24
BootInsAckWait->BootCaptGenCnt	104	Covered	T24
BootInsAckWait->Error	209	Covered	T24
BootInsAckWait->Idle	231	Covered	T24
BootLoadGen->BootInsAckWait	100	Covered	T24
BootLoadGen->Error	209	Covered	T24
BootLoadGen->Idle	231	Covered	T24
BootLoadIns->BootLoadGen	96	Covered	T24
BootLoadIns->Error	209	Covered	T24
BootLoadIns->Idle	231	Covered	T24
BootLoadUni->BootUniAckWait	133	Covered	T24
BootLoadUni->Error	209	Not Covered
BootLoadUni->Idle	231	Not Covered
BootPulse->BootDone	124	Covered	T24
BootPulse->Error	209	Covered	T24
BootPulse->Idle	231	Covered	T24
BootSendGenCmd->BootGenAckWait	114	Covered	T24
BootSendGenCmd->Error	209	Covered	T24
BootSendGenCmd->Idle	231	Covered	T24
BootUniAckWait->Error	209	Not Covered
BootUniAckWait->Idle	137	Covered	T24
Idle->AutoLoadIns	86	Covered	T24
Idle->BootLoadIns	82	Covered	T24
Idle->Error	209	Covered	T24
Idle->SWPortMode	91	Covered	T24
SWPortMode->Error	209	Covered	T24
SWPortMode->Idle	231	Covered	T24

---

Branch Coverage for Module : edn_main_sm

	Line No.	Total	Covered	Percent
Branches		42	41	97.62
IF	60	2	2	100.00
CASE	79	37	36	97.30
IF	208	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_main_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	79	case (state_q)
-2-:	81	if ((boot_req_mode_i && edn_enable_i))
-3-:	83	if ((auto_req_mode_i && edn_enable_i))
-4-:	87	if (edn_enable_i)
-5-:	103	if (csrng_cmd_ack_i)
-6-:	113	if (cmd_sent_i)
-7-:	118	if (csrng_cmd_ack_i)
-8-:	127	if ((!boot_req_mode_i))
-9-:	136	if (csrng_cmd_ack_i)
-10-:	143	if (sw_cmd_req_load_i)
-11-:	149	if (csrng_cmd_ack_i)
-12-:	155	if (csrng_cmd_ack_i)
-13-:	161	if ((!auto_req_mode_i))
-14-:	165	if (max_reqs_cnt_zero_i)
-15-:	180	if (cmd_sent_i)
-16-:	192	if (cmd_sent_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
Idle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T34,T108,T106
Idle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T10,T11
Idle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T6
Idle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
BootLoadIns	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T34,T108,T106
BootLoadGen	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T34,T108,T106
BootInsAckWait	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T34,T108,T106
BootInsAckWait	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T34,T108,T106
BootCaptGenCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T34,T108,T106
BootSendGenCmd	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T34,T108,T106
BootSendGenCmd	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	Not Covered
BootGenAckWait	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	Covered	T34,T108,T106
BootGenAckWait	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	Covered	T34,T108,T106
BootPulse	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T34,T108,T106
BootDone	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T34,T39,T115
BootDone	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Covered	T108,T106,T36
BootLoadUni	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T34,T39,T115
BootUniAckWait	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T34,T39,T115
BootUniAckWait	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T34,T39,T115
AutoLoadIns	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T3,T10,T11
AutoLoadIns	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T3,T10,T11
AutoFirstAckWait	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T3,T10,T11
AutoFirstAckWait	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T3,T10,T11
AutoAckWait	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T3,T10,T11
AutoAckWait	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T3,T10,T11
AutoDispatch	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	Covered	T3,T114,T41
AutoDispatch	-	-	-	-	-	-	-	-	-	-	-	0	1	-	-	Covered	T3,T10,T11
AutoDispatch	-	-	-	-	-	-	-	-	-	-	-	0	0	-	-	Covered	T3,T10,T11
AutoCaptGenCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T10,T11
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	Covered	T3,T10,T11
AutoSendGenCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	Covered	T3,T10,T11
AutoCaptReseedCnt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T10,T11
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T3,T10,T11
AutoSendReseedCmd	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T3,T10,T11
SWPortMode	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T6
Error	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T75,T8
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T75,T76,T77

	LineNo.	Expression
-1-:	208	if (local_escalate_i)
-2-:	222	if (((!edn_enable_i) && (state_q inside {BootLoadIns, BootLoadGen, BootInsAckWait, BootCaptGenCnt, BootSendGenCmd, BootGenAckWait, BootPulse, BootDone, BootLoadUni, BootUniAckWait, AutoLoadIns, AutoFirstAckWait, AutoAckWait, AutoDispatch, AutoCaptGenCnt, AutoSendGenCmd, AutoCaptReseedCnt, AutoSendReseedCmd, SWPortMode})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T7,T75,T8
0	1	Covered	T10,T108,T11
0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_main_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
ErrorStStable_A	196715697	117747	0	0
FpvSecCmErrorStEscalate_A	196715697	118584	0	0
u_state_regs_A	196686508	196534154	0	0

ErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196715697	117747	0	0
T7	2258	602	0	0
T8	0	372	0	0
T9	0	333	0	0
T15	0	1177	0	0
T23	856	0	0	0
T42	5646	0	0	0
T59	1195	0	0	0
T60	1703	0	0	0
T61	964	0	0	0
T62	3049	0	0	0
T63	1572	0	0	0
T64	15862	0	0	0
T65	1404	0	0	0
T75	0	459	0	0
T76	0	193	0	0
T77	0	1060	0	0
T78	0	388	0	0
T79	0	398	0	0
T121	0	600	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196715697	118584	0	0
T7	2258	603	0	0
T8	0	373	0	0
T9	0	334	0	0
T15	0	1178	0	0
T23	856	0	0	0
T42	5646	0	0	0
T59	1195	0	0	0
T60	1703	0	0	0
T61	964	0	0	0
T62	3049	0	0	0
T63	1572	0	0	0
T64	15862	0	0	0
T65	1404	0	0	0
T75	0	460	0	0
T76	0	194	0	0
T77	0	1061	0	0
T78	0	389	0	0
T79	0	399	0	0
T121	0	601	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196686508	196534154	0	0
T1	1313	1222	0	0
T2	15243	14737	0	0
T3	6616	6524	0	0
T4	470499	470486	0	0
T6	1628	1577	0	0
T17	1397	1343	0	0
T31	1049	961	0	0
T32	1557	1493	0	0
T33	2391	2300	0	0
T52	1367	1315	0	0