Unified Coverage Report :: Module :: edn_ack_sm

Module : edn_ack_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.13	100.00	85.39			100.00		u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.13	100.00	85.39			100.00		u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.13	100.00	85.39			100.00		u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.13	100.00	85.39			100.00		u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.13	100.00	85.39			100.00		u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.13	100.00	85.39			100.00		u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.13	100.00	85.39			100.00		u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_ack_sm

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T10,T108,T11

---

FSM Coverage for Module : edn_ack_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T24
DataWait	75	Covered	T24
Disabled	107	Covered	T24
EndPointClear	63	Covered	T24
Error	99	Covered	T24
Idle	68	Covered	T24

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T24
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T24
DataWait->AckPls	80	Covered	T24
DataWait->Disabled	107	Covered	T24
DataWait->Error	99	Covered	T24
Disabled->EndPointClear	63	Covered	T24
Disabled->Error	99	Covered	T24
EndPointClear->Disabled	107	Covered	T24
EndPointClear->Error	99	Covered	T24
EndPointClear->Idle	68	Covered	T24
Idle->DataWait	75	Covered	T24
Idle->Disabled	107	Covered	T24
Idle->Error	99	Covered	T24

---

Branch Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T2,T3,T6
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T2,T3,T6
Idle	-	1	1	-	Covered	T2,T3,T6
Idle	-	1	0	-	Covered	T2,T3,T6
Idle	-	0	-	-	Covered	T2,T3,T6
DataWait	-	-	-	1	Covered	T2,T3,T6
DataWait	-	-	-	0	Covered	T2,T3,T6
AckPls	-	-	-	-	Covered	T2,T3,T6
Error	-	-	-	-	Covered	T7,T75,T8
default	-	-	-	-	Covered	T8,T78,T79

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T7,T75,T8
0	1	Covered	T10,T108,T11
0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_ack_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	1377009879	836829	0	0
FpvSecCmErrorStEscalate_A	1377009879	842688	0	0
u_state_regs_A	1376980690	1375914212	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1377009879	836829	0	0
T7	15806	4214	0	0
T8	0	2554	0	0
T9	0	2681	0	0
T15	0	8239	0	0
T23	5992	0	0	0
T42	39522	0	0	0
T59	8365	0	0	0
T60	11921	0	0	0
T61	6748	0	0	0
T62	21343	0	0	0
T63	11004	0	0	0
T64	111034	0	0	0
T65	9828	0	0	0
T75	0	3563	0	0
T76	0	1701	0	0
T77	0	7770	0	0
T78	0	2666	0	0
T79	0	2736	0	0
T121	0	4150	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1377009879	842688	0	0
T7	15806	4221	0	0
T8	0	2561	0	0
T9	0	2688	0	0
T15	0	8246	0	0
T23	5992	0	0	0
T42	39522	0	0	0
T59	8365	0	0	0
T60	11921	0	0	0
T61	6748	0	0	0
T62	21343	0	0	0
T63	11004	0	0	0
T64	111034	0	0	0
T65	9828	0	0	0
T75	0	3570	0	0
T76	0	1708	0	0
T77	0	7777	0	0
T78	0	2673	0	0
T79	0	2743	0	0
T121	0	4157	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1376980690	1375914212	0	0
T1	9191	8554	0	0
T2	106701	103159	0	0
T3	46312	45668	0	0
T4	3293493	3293402	0	0
T6	11396	11039	0	0
T17	9779	9401	0	0
T31	7343	6727	0	0
T32	10899	10451	0	0
T33	16737	16100	0	0
T52	9569	9205	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T10,T108,T11

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T24
DataWait	75	Covered	T24
Disabled	107	Covered	T24
EndPointClear	63	Covered	T24
Error	99	Covered	T24
Idle	68	Covered	T24

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T24
DataWait->AckPls	80	Covered	T24
DataWait->Disabled	107	Covered	T24
DataWait->Error	99	Covered	T24
Disabled->EndPointClear	63	Covered	T24
Disabled->Error	99	Covered	T24
EndPointClear->Disabled	107	Covered	T24
EndPointClear->Error	99	Covered	T24
EndPointClear->Idle	68	Covered	T24
Idle->DataWait	75	Covered	T24
Idle->Disabled	107	Covered	T24
Idle->Error	99	Covered	T24

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T2,T3,T6
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T2,T3,T6
Idle	-	1	1	-	Covered	T6,T32,T33
Idle	-	1	0	-	Covered	T6,T32,T33
Idle	-	0	-	-	Covered	T2,T3,T6
DataWait	-	-	-	1	Covered	T6,T32,T33
DataWait	-	-	-	0	Covered	T6,T32,T33
AckPls	-	-	-	-	Covered	T6,T32,T33
Error	-	-	-	-	Covered	T7,T75,T8
default	-	-	-	-	Covered	T20,T21,T22

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T7,T75,T8
0	1	Covered	T10,T108,T11
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	196715697	119797	0	0
FpvSecCmErrorStEscalate_A	196715697	120634	0	0
u_state_regs_A	196715697	196563343	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196715697	119797	0	0
T7	2258	602	0	0
T8	0	372	0	0
T9	0	383	0	0
T15	0	1177	0	0
T23	856	0	0	0
T42	5646	0	0	0
T59	1195	0	0	0
T60	1703	0	0	0
T61	964	0	0	0
T62	3049	0	0	0
T63	1572	0	0	0
T64	15862	0	0	0
T65	1404	0	0	0
T75	0	509	0	0
T76	0	243	0	0
T77	0	1110	0	0
T78	0	388	0	0
T79	0	398	0	0
T121	0	600	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196715697	120634	0	0
T7	2258	603	0	0
T8	0	373	0	0
T9	0	384	0	0
T15	0	1178	0	0
T23	856	0	0	0
T42	5646	0	0	0
T59	1195	0	0	0
T60	1703	0	0	0
T61	964	0	0	0
T62	3049	0	0	0
T63	1572	0	0	0
T64	15862	0	0	0
T65	1404	0	0	0
T75	0	510	0	0
T76	0	244	0	0
T77	0	1111	0	0
T78	0	389	0	0
T79	0	399	0	0
T121	0	601	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196715697	196563343	0	0
T1	1313	1222	0	0
T2	15243	14737	0	0
T3	6616	6524	0	0
T4	470499	470486	0	0
T6	1628	1577	0	0
T17	1397	1343	0	0
T31	1049	961	0	0
T32	1557	1493	0	0
T33	2391	2300	0	0
T52	1367	1315	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T10,T108,T11

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T24
DataWait	75	Covered	T24
Disabled	107	Covered	T24
EndPointClear	63	Covered	T24
Error	99	Covered	T24
Idle	68	Covered	T24

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T24
DataWait->AckPls	80	Covered	T24
DataWait->Disabled	107	Covered	T24
DataWait->Error	99	Covered	T24
Disabled->EndPointClear	63	Covered	T24
Disabled->Error	99	Covered	T24
EndPointClear->Disabled	107	Covered	T24
EndPointClear->Error	99	Covered	T24
EndPointClear->Idle	68	Covered	T24
Idle->DataWait	75	Covered	T24
Idle->Disabled	107	Covered	T24
Idle->Error	99	Covered	T24

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T2,T3,T6
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T2,T3,T6
Idle	-	1	1	-	Covered	T17,T32,T34
Idle	-	1	0	-	Covered	T17,T32,T34
Idle	-	0	-	-	Covered	T2,T3,T6
DataWait	-	-	-	1	Covered	T17,T32,T34
DataWait	-	-	-	0	Covered	T17,T32,T34
AckPls	-	-	-	-	Covered	T17,T32,T34
Error	-	-	-	-	Covered	T7,T75,T8
default	-	-	-	-	Covered	T20,T21,T22

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T7,T75,T8
0	1	Covered	T10,T108,T11
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	196715697	119797	0	0
FpvSecCmErrorStEscalate_A	196715697	120634	0	0
u_state_regs_A	196715697	196563343	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196715697	119797	0	0
T7	2258	602	0	0
T8	0	372	0	0
T9	0	383	0	0
T15	0	1177	0	0
T23	856	0	0	0
T42	5646	0	0	0
T59	1195	0	0	0
T60	1703	0	0	0
T61	964	0	0	0
T62	3049	0	0	0
T63	1572	0	0	0
T64	15862	0	0	0
T65	1404	0	0	0
T75	0	509	0	0
T76	0	243	0	0
T77	0	1110	0	0
T78	0	388	0	0
T79	0	398	0	0
T121	0	600	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196715697	120634	0	0
T7	2258	603	0	0
T8	0	373	0	0
T9	0	384	0	0
T15	0	1178	0	0
T23	856	0	0	0
T42	5646	0	0	0
T59	1195	0	0	0
T60	1703	0	0	0
T61	964	0	0	0
T62	3049	0	0	0
T63	1572	0	0	0
T64	15862	0	0	0
T65	1404	0	0	0
T75	0	510	0	0
T76	0	244	0	0
T77	0	1111	0	0
T78	0	389	0	0
T79	0	399	0	0
T121	0	601	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196715697	196563343	0	0
T1	1313	1222	0	0
T2	15243	14737	0	0
T3	6616	6524	0	0
T4	470499	470486	0	0
T6	1628	1577	0	0
T17	1397	1343	0	0
T31	1049	961	0	0
T32	1557	1493	0	0
T33	2391	2300	0	0
T52	1367	1315	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T10,T108,T11

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T24
DataWait	75	Covered	T24
Disabled	107	Covered	T24
EndPointClear	63	Covered	T24
Error	99	Covered	T24
Idle	68	Covered	T24

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T24
DataWait->AckPls	80	Covered	T24
DataWait->Disabled	107	Covered	T24
DataWait->Error	99	Covered	T24
Disabled->EndPointClear	63	Covered	T24
Disabled->Error	99	Covered	T24
EndPointClear->Disabled	107	Covered	T24
EndPointClear->Error	99	Covered	T24
EndPointClear->Idle	68	Covered	T24
Idle->DataWait	75	Covered	T24
Idle->Disabled	107	Covered	T24
Idle->Error	99	Covered	T24

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T2,T3,T6
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T2,T3,T6
Idle	-	1	1	-	Covered	T33,T34,T35
Idle	-	1	0	-	Covered	T33,T34,T35
Idle	-	0	-	-	Covered	T2,T3,T6
DataWait	-	-	-	1	Covered	T33,T34,T35
DataWait	-	-	-	0	Covered	T33,T34,T35
AckPls	-	-	-	-	Covered	T33,T34,T35
Error	-	-	-	-	Covered	T7,T75,T8
default	-	-	-	-	Covered	T20,T21,T22

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T7,T75,T8
0	1	Covered	T10,T108,T11
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	196715697	119797	0	0
FpvSecCmErrorStEscalate_A	196715697	120634	0	0
u_state_regs_A	196715697	196563343	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196715697	119797	0	0
T7	2258	602	0	0
T8	0	372	0	0
T9	0	383	0	0
T15	0	1177	0	0
T23	856	0	0	0
T42	5646	0	0	0
T59	1195	0	0	0
T60	1703	0	0	0
T61	964	0	0	0
T62	3049	0	0	0
T63	1572	0	0	0
T64	15862	0	0	0
T65	1404	0	0	0
T75	0	509	0	0
T76	0	243	0	0
T77	0	1110	0	0
T78	0	388	0	0
T79	0	398	0	0
T121	0	600	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196715697	120634	0	0
T7	2258	603	0	0
T8	0	373	0	0
T9	0	384	0	0
T15	0	1178	0	0
T23	856	0	0	0
T42	5646	0	0	0
T59	1195	0	0	0
T60	1703	0	0	0
T61	964	0	0	0
T62	3049	0	0	0
T63	1572	0	0	0
T64	15862	0	0	0
T65	1404	0	0	0
T75	0	510	0	0
T76	0	244	0	0
T77	0	1111	0	0
T78	0	389	0	0
T79	0	399	0	0
T121	0	601	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196715697	196563343	0	0
T1	1313	1222	0	0
T2	15243	14737	0	0
T3	6616	6524	0	0
T4	470499	470486	0	0
T6	1628	1577	0	0
T17	1397	1343	0	0
T31	1049	961	0	0
T32	1557	1493	0	0
T33	2391	2300	0	0
T52	1367	1315	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T10,T108,T11

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T24
DataWait	75	Covered	T24
Disabled	107	Covered	T24
EndPointClear	63	Covered	T24
Error	99	Covered	T24
Idle	68	Covered	T24

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T24
DataWait->AckPls	80	Covered	T24
DataWait->Disabled	107	Covered	T24
DataWait->Error	99	Covered	T24
Disabled->EndPointClear	63	Covered	T24
Disabled->Error	99	Covered	T24
EndPointClear->Disabled	107	Covered	T24
EndPointClear->Error	99	Covered	T24
EndPointClear->Idle	68	Covered	T24
Idle->DataWait	75	Covered	T24
Idle->Disabled	107	Covered	T24
Idle->Error	99	Covered	T24

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T2,T3,T6
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T2,T3,T6
Idle	-	1	1	-	Covered	T18,T5,T36
Idle	-	1	0	-	Covered	T18,T5,T36
Idle	-	0	-	-	Covered	T2,T3,T6
DataWait	-	-	-	1	Covered	T18,T5,T36
DataWait	-	-	-	0	Covered	T18,T36,T42
AckPls	-	-	-	-	Covered	T18,T5,T36
Error	-	-	-	-	Covered	T7,T75,T8
default	-	-	-	-	Covered	T20,T21,T22

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T7,T75,T8
0	1	Covered	T10,T108,T11
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	196715697	119797	0	0
FpvSecCmErrorStEscalate_A	196715697	120634	0	0
u_state_regs_A	196715697	196563343	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196715697	119797	0	0
T7	2258	602	0	0
T8	0	372	0	0
T9	0	383	0	0
T15	0	1177	0	0
T23	856	0	0	0
T42	5646	0	0	0
T59	1195	0	0	0
T60	1703	0	0	0
T61	964	0	0	0
T62	3049	0	0	0
T63	1572	0	0	0
T64	15862	0	0	0
T65	1404	0	0	0
T75	0	509	0	0
T76	0	243	0	0
T77	0	1110	0	0
T78	0	388	0	0
T79	0	398	0	0
T121	0	600	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196715697	120634	0	0
T7	2258	603	0	0
T8	0	373	0	0
T9	0	384	0	0
T15	0	1178	0	0
T23	856	0	0	0
T42	5646	0	0	0
T59	1195	0	0	0
T60	1703	0	0	0
T61	964	0	0	0
T62	3049	0	0	0
T63	1572	0	0	0
T64	15862	0	0	0
T65	1404	0	0	0
T75	0	510	0	0
T76	0	244	0	0
T77	0	1111	0	0
T78	0	389	0	0
T79	0	399	0	0
T121	0	601	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196715697	196563343	0	0
T1	1313	1222	0	0
T2	15243	14737	0	0
T3	6616	6524	0	0
T4	470499	470486	0	0
T6	1628	1577	0	0
T17	1397	1343	0	0
T31	1049	961	0	0
T32	1557	1493	0	0
T33	2391	2300	0	0
T52	1367	1315	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T10,T108,T11

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T24
DataWait	75	Covered	T24
Disabled	107	Covered	T24
EndPointClear	63	Covered	T24
Error	99	Covered	T24
Idle	68	Covered	T24

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T24
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T24
DataWait->AckPls	80	Covered	T24
DataWait->Disabled	107	Covered	T24
DataWait->Error	99	Covered	T24
Disabled->EndPointClear	63	Covered	T24
Disabled->Error	99	Covered	T24
EndPointClear->Disabled	107	Covered	T24
EndPointClear->Error	99	Covered	T24
EndPointClear->Idle	68	Covered	T24
Idle->DataWait	75	Covered	T24
Idle->Disabled	107	Covered	T24
Idle->Error	99	Covered	T24

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T2,T3,T6
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T2,T3,T6
Idle	-	1	1	-	Covered	T2,T3,T31
Idle	-	1	0	-	Covered	T2,T3,T31
Idle	-	0	-	-	Covered	T2,T3,T6
DataWait	-	-	-	1	Covered	T2,T3,T31
DataWait	-	-	-	0	Covered	T2,T3,T31
AckPls	-	-	-	-	Covered	T2,T3,T31
Error	-	-	-	-	Covered	T7,T75,T8
default	-	-	-	-	Covered	T8,T78,T79

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T7,T75,T8
0	1	Covered	T10,T108,T11
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	196715697	118047	0	0
FpvSecCmErrorStEscalate_A	196715697	118884	0	0
u_state_regs_A	196686508	196534154	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196715697	118047	0	0
T7	2258	602	0	0
T8	0	322	0	0
T9	0	383	0	0
T15	0	1177	0	0
T23	856	0	0	0
T42	5646	0	0	0
T59	1195	0	0	0
T60	1703	0	0	0
T61	964	0	0	0
T62	3049	0	0	0
T63	1572	0	0	0
T64	15862	0	0	0
T65	1404	0	0	0
T75	0	509	0	0
T76	0	243	0	0
T77	0	1110	0	0
T78	0	338	0	0
T79	0	348	0	0
T121	0	550	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196715697	118884	0	0
T7	2258	603	0	0
T8	0	323	0	0
T9	0	384	0	0
T15	0	1178	0	0
T23	856	0	0	0
T42	5646	0	0	0
T59	1195	0	0	0
T60	1703	0	0	0
T61	964	0	0	0
T62	3049	0	0	0
T63	1572	0	0	0
T64	15862	0	0	0
T65	1404	0	0	0
T75	0	510	0	0
T76	0	244	0	0
T77	0	1111	0	0
T78	0	339	0	0
T79	0	349	0	0
T121	0	551	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196686508	196534154	0	0
T1	1313	1222	0	0
T2	15243	14737	0	0
T3	6616	6524	0	0
T4	470499	470486	0	0
T6	1628	1577	0	0
T17	1397	1343	0	0
T31	1049	961	0	0
T32	1557	1493	0	0
T33	2391	2300	0	0
T52	1367	1315	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T10,T108,T11

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T24
DataWait	75	Covered	T24
Disabled	107	Covered	T24
EndPointClear	63	Covered	T24
Error	99	Covered	T24
Idle	68	Covered	T24

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T24
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T24
DataWait->AckPls	80	Covered	T24
DataWait->Disabled	107	Covered	T24
DataWait->Error	99	Covered	T24
Disabled->EndPointClear	63	Covered	T24
Disabled->Error	99	Covered	T24
EndPointClear->Disabled	107	Covered	T24
EndPointClear->Error	99	Covered	T24
EndPointClear->Idle	68	Covered	T24
Idle->DataWait	75	Covered	T24
Idle->Disabled	107	Covered	T24
Idle->Error	99	Covered	T24

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T2,T3,T6
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T2,T3,T6
Idle	-	1	1	-	Covered	T33,T37,T35
Idle	-	1	0	-	Covered	T33,T37,T35
Idle	-	0	-	-	Covered	T2,T3,T6
DataWait	-	-	-	1	Covered	T33,T37,T35
DataWait	-	-	-	0	Covered	T33,T37,T35
AckPls	-	-	-	-	Covered	T33,T37,T35
Error	-	-	-	-	Covered	T7,T75,T8
default	-	-	-	-	Covered	T20,T21,T22

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T7,T75,T8
0	1	Covered	T10,T108,T11
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	196715697	119797	0	0
FpvSecCmErrorStEscalate_A	196715697	120634	0	0
u_state_regs_A	196715697	196563343	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196715697	119797	0	0
T7	2258	602	0	0
T8	0	372	0	0
T9	0	383	0	0
T15	0	1177	0	0
T23	856	0	0	0
T42	5646	0	0	0
T59	1195	0	0	0
T60	1703	0	0	0
T61	964	0	0	0
T62	3049	0	0	0
T63	1572	0	0	0
T64	15862	0	0	0
T65	1404	0	0	0
T75	0	509	0	0
T76	0	243	0	0
T77	0	1110	0	0
T78	0	388	0	0
T79	0	398	0	0
T121	0	600	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196715697	120634	0	0
T7	2258	603	0	0
T8	0	373	0	0
T9	0	384	0	0
T15	0	1178	0	0
T23	856	0	0	0
T42	5646	0	0	0
T59	1195	0	0	0
T60	1703	0	0	0
T61	964	0	0	0
T62	3049	0	0	0
T63	1572	0	0	0
T64	15862	0	0	0
T65	1404	0	0	0
T75	0	510	0	0
T76	0	244	0	0
T77	0	1111	0	0
T78	0	389	0	0
T79	0	399	0	0
T121	0	601	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196715697	196563343	0	0
T1	1313	1222	0	0
T2	15243	14737	0	0
T3	6616	6524	0	0
T4	470499	470486	0	0
T6	1628	1577	0	0
T17	1397	1343	0	0
T31	1049	961	0	0
T32	1557	1493	0	0
T33	2391	2300	0	0
T52	1367	1315	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T10,T108,T11

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T24
DataWait	75	Covered	T24
Disabled	107	Covered	T24
EndPointClear	63	Covered	T24
Error	99	Covered	T24
Idle	68	Covered	T24

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T24
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T24
DataWait->AckPls	80	Covered	T24
DataWait->Disabled	107	Covered	T24
DataWait->Error	99	Covered	T24
Disabled->EndPointClear	63	Covered	T24
Disabled->Error	99	Covered	T24
EndPointClear->Disabled	107	Covered	T24
EndPointClear->Error	99	Covered	T24
EndPointClear->Idle	68	Covered	T24
Idle->DataWait	75	Covered	T24
Idle->Disabled	107	Covered	T24
Idle->Error	99	Covered	T24

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T2,T3,T6
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T2,T3,T6
Idle	-	1	1	-	Covered	T33,T37,T38
Idle	-	1	0	-	Covered	T33,T37,T38
Idle	-	0	-	-	Covered	T2,T3,T6
DataWait	-	-	-	1	Covered	T33,T37,T38
DataWait	-	-	-	0	Covered	T33,T37,T38
AckPls	-	-	-	-	Covered	T33,T37,T38
Error	-	-	-	-	Covered	T7,T75,T8
default	-	-	-	-	Covered	T20,T21,T22

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T7,T75,T8
0	1	Covered	T10,T108,T11
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	196715697	119797	0	0
FpvSecCmErrorStEscalate_A	196715697	120634	0	0
u_state_regs_A	196715697	196563343	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196715697	119797	0	0
T7	2258	602	0	0
T8	0	372	0	0
T9	0	383	0	0
T15	0	1177	0	0
T23	856	0	0	0
T42	5646	0	0	0
T59	1195	0	0	0
T60	1703	0	0	0
T61	964	0	0	0
T62	3049	0	0	0
T63	1572	0	0	0
T64	15862	0	0	0
T65	1404	0	0	0
T75	0	509	0	0
T76	0	243	0	0
T77	0	1110	0	0
T78	0	388	0	0
T79	0	398	0	0
T121	0	600	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196715697	120634	0	0
T7	2258	603	0	0
T8	0	373	0	0
T9	0	384	0	0
T15	0	1178	0	0
T23	856	0	0	0
T42	5646	0	0	0
T59	1195	0	0	0
T60	1703	0	0	0
T61	964	0	0	0
T62	3049	0	0	0
T63	1572	0	0	0
T64	15862	0	0	0
T65	1404	0	0	0
T75	0	510	0	0
T76	0	244	0	0
T77	0	1111	0	0
T78	0	389	0	0
T79	0	399	0	0
T121	0	601	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196715697	196563343	0	0
T1	1313	1222	0	0
T2	15243	14737	0	0
T3	6616	6524	0	0
T4	470499	470486	0	0
T6	1628	1577	0	0
T17	1397	1343	0	0
T31	1049	961	0	0
T32	1557	1493	0	0
T33	2391	2300	0	0
T52	1367	1315	0	0