Unified Coverage Report :: Module :: edn_reg_top

Module : edn_reg_top

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_reg_top.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.81	96.00	98.29	100.00		94.76	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.59		83.33	100.00			67.44	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_alert_test_fatal_alert	100.00	100.00
u_alert_test_recov_alert	100.00	100.00
u_boot_gen_cmd	100.00	100.00	100.00			100.00
u_boot_ins_cmd	100.00	100.00	100.00			100.00
u_chk	100.00	100.00		100.00			100.00
u_ctrl_auto_req_mode	100.00	100.00	100.00			100.00
u_ctrl_boot_req_mode	100.00	100.00	100.00			100.00
u_ctrl_cmd_fifo_rst	100.00	100.00	100.00			100.00
u_ctrl_edn_enable	100.00	100.00	100.00			100.00
u_err_code_edn_ack_sm_err	96.30	88.89	100.00			100.00
u_err_code_edn_cntr_err	96.30	88.89	100.00			100.00
u_err_code_edn_main_sm_err	96.30	88.89	100.00			100.00
u_err_code_fifo_read_err	96.30	88.89	100.00			100.00
u_err_code_fifo_state_err	96.30	88.89	100.00			100.00
u_err_code_fifo_write_err	96.30	88.89	100.00			100.00
u_err_code_sfifo_gencmd_err	96.30	88.89	100.00			100.00
u_err_code_sfifo_output_err	62.59	77.78	50.00			60.00
u_err_code_sfifo_rescmd_err	96.30	88.89	100.00			100.00
u_err_code_test	100.00	100.00	100.00			100.00
u_err_code_test0_qe	100.00	100.00				100.00
u_generate_cmd	100.00	100.00
u_intr_enable_edn_cmd_req_done	100.00	100.00	100.00			100.00
u_intr_enable_edn_fatal_err	100.00	100.00	100.00			100.00
u_intr_state_edn_cmd_req_done	100.00	100.00	100.00			100.00
u_intr_state_edn_fatal_err	100.00	100.00	100.00			100.00
u_intr_test_edn_cmd_req_done	100.00	100.00
u_intr_test_edn_fatal_err	100.00	100.00
u_main_sm_state	62.59	77.78	50.00			60.00
u_max_num_reqs_between_reseeds	100.00	100.00	100.00			100.00
u_max_num_reqs_between_reseeds0_qe	100.00	100.00				100.00
u_prim_reg_we_check	100.00	100.00		100.00
u_recov_alert_sts_auto_req_mode_field_alert	100.00	100.00	100.00			100.00
u_recov_alert_sts_boot_req_mode_field_alert	100.00	100.00	100.00			100.00
u_recov_alert_sts_cmd_fifo_rst_field_alert	100.00	100.00	100.00			100.00
u_recov_alert_sts_edn_bus_cmp_alert	100.00	100.00	100.00			100.00
u_recov_alert_sts_edn_enable_field_alert	100.00	100.00	100.00			100.00
u_reg_if	98.67	97.14	97.53			100.00	100.00
u_regwen	100.00	100.00	100.00			100.00
u_reseed_cmd	100.00	100.00
u_rsp_intg_gen	100.00	100.00					100.00
u_sw_cmd_req	100.00	100.00
u_sw_cmd_sts_cmd_ack	62.59	77.78	50.00			60.00
u_sw_cmd_sts_cmd_rdy	62.59	77.78	50.00			60.00
u_sw_cmd_sts_cmd_reg_rdy	62.59	77.78	50.00			60.00
u_sw_cmd_sts_cmd_sts	62.59	77.78	50.00			60.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : edn_reg_top

	Line No.	Total	Covered	Percent
TOTAL		144	144	100.00
ALWAYS	68	4	4	100.00
CONT_ASSIGN	77	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	119	1	1	100.00
CONT_ASSIGN	312	1	1	100.00
CONT_ASSIGN	327	1	1	100.00
CONT_ASSIGN	343	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	364	1	1	100.00
CONT_ASSIGN	380	1	1	100.00
CONT_ASSIGN	414	1	1	100.00
CONT_ASSIGN	583	1	1	100.00
CONT_ASSIGN	597	1	1	100.00
CONT_ASSIGN	713	1	1	100.00
CONT_ASSIGN	727	1	1	100.00
CONT_ASSIGN	733	1	1	100.00
CONT_ASSIGN	747	1	1	100.00
CONT_ASSIGN	787	1	1	100.00
CONT_ASSIGN	1209	1	1	100.00
ALWAYS	1243	18	18	100.00
CONT_ASSIGN	1263	1	1	100.00
ALWAYS	1267	1	1	100.00
CONT_ASSIGN	1288	1	1	100.00
CONT_ASSIGN	1290	1	1	100.00
CONT_ASSIGN	1292	1	1	100.00
CONT_ASSIGN	1293	1	1	100.00
CONT_ASSIGN	1295	1	1	100.00
CONT_ASSIGN	1297	1	1	100.00
CONT_ASSIGN	1298	1	1	100.00
CONT_ASSIGN	1300	1	1	100.00
CONT_ASSIGN	1302	1	1	100.00
CONT_ASSIGN	1303	1	1	100.00
CONT_ASSIGN	1305	1	1	100.00
CONT_ASSIGN	1307	1	1	100.00
CONT_ASSIGN	1308	1	1	100.00
CONT_ASSIGN	1310	1	1	100.00
CONT_ASSIGN	1311	1	1	100.00
CONT_ASSIGN	1313	1	1	100.00
CONT_ASSIGN	1315	1	1	100.00
CONT_ASSIGN	1317	1	1	100.00
CONT_ASSIGN	1319	1	1	100.00
CONT_ASSIGN	1320	1	1	100.00
CONT_ASSIGN	1322	1	1	100.00
CONT_ASSIGN	1323	1	1	100.00
CONT_ASSIGN	1325	1	1	100.00
CONT_ASSIGN	1326	1	1	100.00
CONT_ASSIGN	1328	1	1	100.00
CONT_ASSIGN	1329	1	1	100.00
CONT_ASSIGN	1331	1	1	100.00
CONT_ASSIGN	1332	1	1	100.00
CONT_ASSIGN	1334	1	1	100.00
CONT_ASSIGN	1335	1	1	100.00
CONT_ASSIGN	1337	1	1	100.00
CONT_ASSIGN	1338	1	1	100.00
CONT_ASSIGN	1340	1	1	100.00
CONT_ASSIGN	1342	1	1	100.00
CONT_ASSIGN	1344	1	1	100.00
CONT_ASSIGN	1346	1	1	100.00
CONT_ASSIGN	1348	1	1	100.00
CONT_ASSIGN	1349	1	1	100.00
CONT_ASSIGN	1351	1	1	100.00
ALWAYS	1355	18	18	100.00
ALWAYS	1377	41	41	100.00
CONT_ASSIGN	1480	0	0
CONT_ASSIGN	1488	1	1	100.00
CONT_ASSIGN	1489	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_reg_top.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_reg_top.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
69	1	1
70	1	1
71	1	1
			MISSING_ELSE
77	1	1
89	1	1
90	1	1
118	1	1
119	1	1
312	1	1
327	1	1
343	1	1
349	1	1
364	1	1
380	1	1
414	1	1
583	1	1
597	1	1
713	1	1
727	1	1
733	1	1
747	1	1
787	1	1
1209	1	1
1243	1	1
1244	1	1
1245	1	1
1246	1	1
1247	1	1
1248	1	1
1249	1	1
1250	1	1
1251	1	1
1252	1	1
1253	1	1
1254	1	1
1255	1	1
1256	1	1
1257	1	1
1258	1	1
1259	1	1
1260	1	1
1263	1	1
1267	1	1
1288	1	1
1290	1	1
1292	1	1
1293	1	1
1295	1	1
1297	1	1
1298	1	1
1300	1	1
1302	1	1
1303	1	1
1305	1	1
1307	1	1
1308	1	1
1310	1	1
1311	1	1
1313	1	1
1315	1	1
1317	1	1
1319	1	1
1320	1	1
1322	1	1
1323	1	1
1325	1	1
1326	1	1
1328	1	1
1329	1	1
1331	1	1
1332	1	1
1334	1	1
1335	1	1
1337	1	1
1338	1	1
1340	1	1
1342	1	1
1344	1	1
1346	1	1
1348	1	1
1349	1	1
1351	1	1
1355	1	1
1356	1	1
1357	1	1
1358	1	1
1359	1	1
1360	1	1
1361	1	1
1362	1	1
1363	1	1
1364	1	1
1365	1	1
1366	1	1
1367	1	1
1368	1	1
1369	1	1
1370	1	1
1371	1	1
1372	1	1
1377	1	1
1378	1	1
1380	1	1
1381	1	1
1385	1	1
1386	1	1
1390	1	1
1391	1	1
1395	1	1
1396	1	1
1400	1	1
1404	1	1
1405	1	1
1406	1	1
1407	1	1
1411	1	1
1415	1	1
1419	1	1
1423	1	1
1424	1	1
1425	1	1
1426	1	1
1430	1	1
1434	1	1
1438	1	1
1442	1	1
1443	1	1
1444	1	1
1445	1	1
1446	1	1
1450	1	1
1451	1	1
1452	1	1
1453	1	1
1454	1	1
1455	1	1
1456	1	1
1457	1	1
1458	1	1
1462	1	1
1466	1	1
1480		unreachable
1488	1	1
1489	1	1

---

Cond Coverage for Module : edn_reg_top

	Total	Covered	Percent
Conditions	184	184	100.00
Logical	184	184	100.00
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (reg_we && ((!addrmiss)))
             ---1--    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T24,T25,T26
1	0	Covered	T29,T145,T146
1	1	Covered	T24,T25,T26

 LINE       70
 EXPRESSION (intg_err || reg_we_err)
             ----1---    -----2----

-1-	-2-	Status	Tests
0	0	Covered	T24,T25,T26
0	1	Covered	T20,T21,T22
1	0	Covered	T29,T146,T147

 LINE       77
 EXPRESSION (err_q | intg_err | reg_we_err)
             --1--   ----2---   -----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T24,T25,T26
0	0	1	Covered	T20,T21,T22
0	1	0	Covered	T29,T146,T147
1	0	0	Covered	T29,T146,T147

 LINE       119
 EXPRESSION (addrmiss | wr_err | intg_err)
             ----1---   ---2--   ----3---

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T24,T25,T26
0	0	1	Covered	T29,T146,T147
0	1	0	Covered	T145,T148,T165
1	0	0	Covered	T145,T148,T165

 LINE       414
 EXPRESSION (ctrl_we & regwen_qs)
             ---1---   ----2----

-1-	-2-	Status	Tests
0	1	Covered	T24,T25,T26
1	0	Covered	T207,T208,T73
1	1	Covered	T2,T3,T6

 LINE       1244
 EXPRESSION (reg_addr == edn_reg_pkg::EDN_INTR_STATE_OFFSET)
            ------------------------1-----------------------

-1-	Status	Tests
0	Covered	T24,T25,T26
1	Covered	T24,T25,T26

 LINE       1245
 EXPRESSION (reg_addr == edn_reg_pkg::EDN_INTR_ENABLE_OFFSET)
            ------------------------1------------------------

-1-	Status	Tests
0	Covered	T24,T25,T26
1	Covered	T24,T25,T26

 LINE       1246
 EXPRESSION (reg_addr == edn_reg_pkg::EDN_INTR_TEST_OFFSET)
            -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T24,T25,T26
1	Covered	T24,T25,T26

 LINE       1247
 EXPRESSION (reg_addr == edn_reg_pkg::EDN_ALERT_TEST_OFFSET)
            ------------------------1-----------------------

-1-	Status	Tests
0	Covered	T24,T25,T26
1	Covered	T24,T26,T27

 LINE       1248
 EXPRESSION (reg_addr == edn_reg_pkg::EDN_REGWEN_OFFSET)
            ----------------------1---------------------

-1-	Status	Tests
0	Covered	T24,T25,T26
1	Covered	T24,T26,T27

 LINE       1249
 EXPRESSION (reg_addr == edn_reg_pkg::EDN_CTRL_OFFSET)
            ---------------------1--------------------

-1-	Status	Tests
0	Covered	T24,T25,T26
1	Covered	T24,T26,T27

 LINE       1250
 EXPRESSION (reg_addr == edn_reg_pkg::EDN_BOOT_INS_CMD_OFFSET)
            -------------------------1------------------------

-1-	Status	Tests
0	Covered	T24,T25,T26
1	Covered	T24,T26,T27

 LINE       1251
 EXPRESSION (reg_addr == edn_reg_pkg::EDN_BOOT_GEN_CMD_OFFSET)
            -------------------------1------------------------

-1-	Status	Tests
0	Covered	T24,T25,T26
1	Covered	T24,T26,T27

 LINE       1252
 EXPRESSION (reg_addr == edn_reg_pkg::EDN_SW_CMD_REQ_OFFSET)
            ------------------------1-----------------------

-1-	Status	Tests
0	Covered	T24,T25,T26
1	Covered	T24,T26,T27

 LINE       1253
 EXPRESSION (reg_addr == edn_reg_pkg::EDN_SW_CMD_STS_OFFSET)
            ------------------------1-----------------------

-1-	Status	Tests
0	Covered	T24,T25,T26
1	Covered	T24,T26,T27

 LINE       1254
 EXPRESSION (reg_addr == edn_reg_pkg::EDN_RESEED_CMD_OFFSET)
            ------------------------1-----------------------

-1-	Status	Tests
0	Covered	T24,T25,T26
1	Covered	T24,T26,T27

 LINE       1255
 EXPRESSION (reg_addr == edn_reg_pkg::EDN_GENERATE_CMD_OFFSET)
            -------------------------1------------------------

-1-	Status	Tests
0	Covered	T24,T25,T26
1	Covered	T24,T26,T27

 LINE       1256
 EXPRESSION (reg_addr == edn_reg_pkg::EDN_MAX_NUM_REQS_BETWEEN_RESEEDS_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T24,T25,T26
1	Covered	T24,T26,T27

 LINE       1257
 EXPRESSION (reg_addr == edn_reg_pkg::EDN_RECOV_ALERT_STS_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T24,T25,T26
1	Covered	T24,T26,T27

 LINE       1258
 EXPRESSION (reg_addr == edn_reg_pkg::EDN_ERR_CODE_OFFSET)
            -----------------------1----------------------

-1-	Status	Tests
0	Covered	T24,T25,T26
1	Covered	T24,T26,T27

 LINE       1259
 EXPRESSION (reg_addr == edn_reg_pkg::EDN_ERR_CODE_TEST_OFFSET)
            -------------------------1-------------------------

-1-	Status	Tests
0	Covered	T24,T25,T26
1	Covered	T24,T26,T27

 LINE       1260
 EXPRESSION (reg_addr == edn_reg_pkg::EDN_MAIN_SM_STATE_OFFSET)
            -------------------------1-------------------------

-1-	Status	Tests
0	Covered	T24,T25,T26
1	Covered	T24,T26,T27

 LINE       1263
 EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
             ---------1--------

-1-	Status	Tests
0	Covered	T24,T25,T26
1	Covered	T24,T25,T26

 LINE       1263
 SUB-EXPRESSION (reg_re || reg_we)
                 ---1--    ---2--

-1-	-2-	Status	Tests
0	0	Covered	T24,T25,T26
0	1	Covered	T24,T25,T26
1	0	Covered	T24,T25,T26

 LINE       1267
 EXPRESSION 
 Number  Term
      1  reg_we & 
      2  ((addr_hit[0] & ((|(4'b1 & (~reg_be))))) | (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | (addr_hit[5] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[6] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[7] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[8] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[9] & ((|(4'b1 & (~reg_be))))) | (addr_hit[10] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[11] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[12] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[13] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[14] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[15] & ((|(4'b1 & (~reg_be))))) | (addr_hit[16] & ((|(4'b0011 & (~reg_be)))))))

-1-	-2-	Status	Tests
0	1	Covered	T24,T25,T26
1	0	Covered	T24,T25,T26
1	1	Covered	T29,T145,T148

 LINE       1267
 SUB-EXPRESSION 
 Number  Term
      1  (addr_hit[0] & ((|(4'b1 & (~reg_be))))) | 
      2  (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | 
      3  (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | 
      4  (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | 
      5  (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | 
      6  (addr_hit[5] & ((|(4'b0011 & (~reg_be))))) | 
      7  (addr_hit[6] & ((|(4'b1111 & (~reg_be))))) | 
      8  (addr_hit[7] & ((|(4'b1111 & (~reg_be))))) | 
      9  (addr_hit[8] & ((|(4'b1111 & (~reg_be))))) | 
     10  (addr_hit[9] & ((|(4'b1 & (~reg_be))))) | 
     11  (addr_hit[10] & ((|(4'b1111 & (~reg_be))))) | 
     12  (addr_hit[11] & ((|(4'b1111 & (~reg_be))))) | 
     13  (addr_hit[12] & ((|(4'b1111 & (~reg_be))))) | 
     14  (addr_hit[13] & ((|(4'b0011 & (~reg_be))))) | 
     15  (addr_hit[14] & ((|(4'b1111 & (~reg_be))))) | 
     16  (addr_hit[15] & ((|(4'b1 & (~reg_be))))) | 
     17  (addr_hit[16] & ((|(4'b0011 & (~reg_be))))))

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	-17-	Status	Tests
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	Covered	T24,T25,T26
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	Covered	T24,T26,T27
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	Covered	T24,T26,T27
0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	Covered	T24,T26,T27
0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	Covered	T24,T28,T84
0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	0	Covered	T24,T26,T28
0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	Covered	T24,T26,T27
0	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	Covered	T24,T26,T29
0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	Covered	T27,T84,T85
0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	Covered	T24,T26,T27
0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	Covered	T24,T26,T27
0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	Covered	T24,T26,T27
0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	0	Covered	T24,T27,T84
0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	Covered	T24,T27,T28
0	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	Covered	T24,T26,T28
0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	Covered	T24,T25,T26
0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	Covered	T24,T25,T27
1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	Covered	T25,T27,T28

 LINE       1267
 SUB-EXPRESSION (addr_hit[0] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T24,T25,T26
1	0	Covered	T24,T25,T26
1	1	Covered	T25,T27,T28

 LINE       1267
 SUB-EXPRESSION (addr_hit[1] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T24,T25,T26
1	0	Covered	T24,T25,T26
1	1	Covered	T24,T25,T27

 LINE       1267
 SUB-EXPRESSION (addr_hit[2] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T24,T25,T26
1	0	Covered	T24,T25,T26
1	1	Covered	T24,T25,T26

 LINE       1267
 SUB-EXPRESSION (addr_hit[3] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T24,T25,T26
1	0	Covered	T24,T26,T27
1	1	Covered	T24,T26,T28

 LINE       1267
 SUB-EXPRESSION (addr_hit[4] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T24,T25,T26
1	0	Covered	T24,T26,T27
1	1	Covered	T24,T27,T28

 LINE       1267
 SUB-EXPRESSION (addr_hit[5] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T24,T25,T26
1	0	Covered	T24,T26,T27
1	1	Covered	T24,T27,T84

 LINE       1267
 SUB-EXPRESSION (addr_hit[6] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T24,T25,T26
1	0	Covered	T24,T26,T85
1	1	Covered	T24,T26,T27

 LINE       1267
 SUB-EXPRESSION (addr_hit[7] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T24,T25,T26
1	0	Covered	T26,T27,T85
1	1	Covered	T24,T26,T27

 LINE       1267
 SUB-EXPRESSION (addr_hit[8] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T24,T25,T26
1	0	Covered	T24,T26,T27
1	1	Covered	T24,T26,T27

 LINE       1267
 SUB-EXPRESSION (addr_hit[9] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T24,T25,T26
1	0	Covered	T24,T26,T27
1	1	Covered	T27,T84,T85

 LINE       1267
 SUB-EXPRESSION (addr_hit[10] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T24,T25,T26
1	0	Covered	T24,T26,T27
1	1	Covered	T24,T26,T29

 LINE       1267
 SUB-EXPRESSION (addr_hit[11] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T24,T25,T26
1	0	Covered	T24,T26,T27
1	1	Covered	T24,T26,T27

 LINE       1267
 SUB-EXPRESSION (addr_hit[12] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T24,T25,T26
1	0	Covered	T24,T26,T27
1	1	Covered	T24,T26,T28

 LINE       1267
 SUB-EXPRESSION (addr_hit[13] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T24,T25,T26
1	0	Covered	T24,T26,T27
1	1	Covered	T24,T28,T84

 LINE       1267
 SUB-EXPRESSION (addr_hit[14] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T24,T25,T26
1	0	Covered	T24,T26,T27
1	1	Covered	T24,T26,T27

 LINE       1267
 SUB-EXPRESSION (addr_hit[15] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T24,T25,T26
1	0	Covered	T24,T26,T84
1	1	Covered	T24,T26,T27

 LINE       1267
 SUB-EXPRESSION (addr_hit[16] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T24,T25,T26
1	0	Covered	T24,T26,T27
1	1	Covered	T24,T26,T27

 LINE       1288
 EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T24,T25,T26
1	0	1	Covered	T24,T25,T26
1	1	0	Covered	T165,T209,T210
1	1	1	Covered	T25,T28,T51

 LINE       1293
 EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T24,T25,T26
1	0	1	Covered	T24,T25,T26
1	1	0	Covered	T175,T165,T158
1	1	1	Covered	T24,T25,T26

 LINE       1298
 EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T24,T25,T26
1	0	1	Covered	T24,T25,T26
1	1	0	Covered	T165,T166,T155
1	1	1	Covered	T24,T25,T27

 LINE       1303
 EXPRESSION (addr_hit[3] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T24,T25,T26
1	0	1	Covered	T24,T26,T27
1	1	0	Covered	T155,T211,T212
1	1	1	Covered	T24,T26,T27

 LINE       1308
 EXPRESSION (addr_hit[4] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T24,T25,T26
1	0	1	Covered	T24,T26,T27
1	1	0	Covered	T158,T166,T155
1	1	1	Covered	T24,T26,T27

 LINE       1311
 EXPRESSION (addr_hit[5] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T24,T25,T26
1	0	1	Covered	T24,T26,T27
1	1	0	Covered	T166,T155,T167
1	1	1	Covered	T2,T3,T6

 LINE       1320
 EXPRESSION (addr_hit[6] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T24,T25,T26
1	0	1	Covered	T24,T26,T27
1	1	0	Covered	T165,T158,T166
1	1	1	Covered	T34,T108,T106

 LINE       1323
 EXPRESSION (addr_hit[7] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T24,T25,T26
1	0	1	Covered	T24,T26,T27
1	1	0	Covered	T148,T165,T155
1	1	1	Covered	T34,T108,T106

 LINE       1326
 EXPRESSION (addr_hit[8] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T24,T25,T26
1	0	1	Covered	T24,T26,T27
1	1	0	Covered	T145,T165,T158
1	1	1	Covered	T24,T26,T27

 LINE       1329
 EXPRESSION (addr_hit[10] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T24,T25,T26
1	0	1	Covered	T24,T26,T27
1	1	0	Covered	T146,T148,T147
1	1	1	Covered	T24,T26,T27

 LINE       1332
 EXPRESSION (addr_hit[11] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T24,T25,T26
1	0	1	Covered	T24,T26,T27
1	1	0	Covered	T29,T145,T165
1	1	1	Covered	T24,T26,T27

 LINE       1335
 EXPRESSION (addr_hit[12] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T24,T25,T26
1	0	1	Covered	T24,T26,T27
1	1	0	Covered	T145,T148,T176
1	1	1	Covered	T24,T26,T27

 LINE       1338
 EXPRESSION (addr_hit[13] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T24,T25,T26
1	0	1	Covered	T24,T26,T27
1	1	0	Covered	T145,T148,T165
1	1	1	Covered	T24,T26,T27

 LINE       1349
 EXPRESSION (addr_hit[15] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T24,T25,T26
1	0	1	Covered	T24,T26,T27
1	1	0	Covered	T165,T166,T155
1	1	1	Covered	T2,T31,T17

---

Branch Coverage for Module : edn_reg_top

	Line No.	Total	Covered	Percent
Branches		23	23	100.00
TERNARY	1263	2	2	100.00
IF	68	3	3	100.00
CASE	1378	18	18	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_reg_top.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	1263	((reg_re || reg_we)) ? 

Branches:

-1-	Status	Tests
1	Covered	T24,T25,T26
0	Covered	T24,T25,T26

	LineNo.	Expression
-1-:	68	if ((!rst_ni))
-2-:	70	if ((intg_err || reg_we_err))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T24,T25,T26
0	1	Covered	T29,T146,T147
0	0	Covered	T24,T25,T26

	LineNo.	Expression
-1-:	1378	case (1'b1)

Branches:

-1-	Status	Tests
addr_hit[0]	Covered	T24,T25,T26
addr_hit[1]	Covered	T24,T25,T26
addr_hit[2]	Covered	T24,T25,T26
addr_hit[3]	Covered	T24,T25,T26
addr_hit[4]	Covered	T24,T25,T26
addr_hit[5]	Covered	T24,T25,T26
addr_hit[6]	Covered	T24,T25,T26
addr_hit[7]	Covered	T24,T25,T26
addr_hit[8]	Covered	T24,T25,T26
addr_hit[9]	Covered	T24,T25,T26
addr_hit[10]	Covered	T24,T25,T26
addr_hit[11]	Covered	T24,T25,T26
addr_hit[12]	Covered	T24,T25,T26
addr_hit[13]	Covered	T24,T25,T26
addr_hit[14]	Covered	T24,T25,T26
addr_hit[15]	Covered	T24,T25,T26
addr_hit[16]	Covered	T24,T25,T26
default	Covered	T24,T25,T26

---

Assert Coverage for Module : edn_reg_top

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
en2addrHit	197172624	680024	0	0
reAfterRv	197172624	680022	0	0
rePulse	197172624	268632	0	0
wePulse	197172624	411390	0	0

en2addrHit

Name	Attempts	Real Successes	Failures	Incomplete
Total	197172624	680024	0	0
T24	1389	55	0	0
T25	709	20	0	0
T26	2802	76	0	0
T27	1870	54	0	0
T28	863	38	0	0
T29	4204	236	0	0
T51	1203	22	0	0
T84	832	31	0	0
T85	1362	140	0	0
T86	2522	137	0	0

reAfterRv

Name	Attempts	Real Successes	Failures	Incomplete
Total	197172624	680022	0	0
T24	1389	55	0	0
T25	709	20	0	0
T26	2802	76	0	0
T27	1870	54	0	0
T28	863	38	0	0
T29	4204	236	0	0
T51	1203	22	0	0
T84	832	31	0	0
T85	1362	140	0	0
T86	2522	137	0	0

rePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	197172624	268632	0	0
T24	1389	31	0	0
T25	709	10	0	0
T26	2802	55	0	0
T27	1870	30	0	0
T28	863	19	0	0
T29	4204	124	0	0
T51	1203	11	0	0
T84	832	20	0	0
T85	1362	81	0	0
T86	2522	87	0	0

wePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	197172624	411390	0	0
T24	1389	24	0	0
T25	709	10	0	0
T26	2802	21	0	0
T27	1870	24	0	0
T28	863	19	0	0
T29	4204	112	0	0
T51	1203	11	0	0
T84	832	11	0	0
T85	1362	59	0	0
T86	2522	50	0	0