Group : tb.dut.u_edn_cov_if::edn_cfg_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tb.dut.u_edn_cov_if::edn_cfg_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
96.97 96.97 1 100 1 1 64 64


Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_edn_cov_0/edn_cov_if.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
edn_cfg_cg 96.97 1 100 1 64 64




Group Instance : edn_cfg_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
96.97 1 100 1 64 64




Summary for Group Instance edn_cfg_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 12 0 12 100.00
Crosses 21 1 20 95.24


Variables for Group Instance edn_cfg_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mode 3 0 3 100.00 100 1 1 0
cp_num_boot_reqs 2 0 2 100.00 100 1 1 0
cp_num_endpoints 7 0 7 100.00 100 1 1 8


Crosses for Group Instance edn_cfg_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_num_endpoints_mode 21 1 20 95.24 100 1 1 0


Summary for Variable cp_mode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_mode

Excluded/Illegal bins
NAMECOUNTSTATUS
both 0 Illegal


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
boot_req_mode 133 1 T28 1 T37 1 T31 1
auto_req_mode 129 1 T7 1 T8 1 T29 1
sw_mode 3182 1 T1 1 T32 40 T30 1



Summary for Variable cp_num_boot_reqs

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_num_boot_reqs

Excluded/Illegal bins
NAMECOUNTSTATUS
zero 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
multiple 294 1 T1 1 T28 1 T8 1
single 94 1 T7 1 T37 1 T33 1



Summary for Variable cp_num_endpoints

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 7 0 7 100.00


Automatically Generated Bins for cp_num_endpoints

Excluded/Illegal bins
NAMECOUNTSTATUS
zero 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 1310 1 T7 1 T8 1 T37 1
auto[2] 135 1 T31 1 T170 1 T171 1
auto[3] 145 1 T9 1 T172 1 T173 1
auto[4] 113 1 T174 1 T175 92 T176 1
auto[5] 209 1 T38 1 T32 40 T89 1
auto[6] 187 1 T41 1 T177 1 T178 1
auto[7] 1345 1 T1 1 T28 1 T29 1



Summary for Cross cr_num_endpoints_mode

Samples crossed: cp_num_endpoints cp_mode
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 21 1 20 95.24 1


Automatically Generated Cross Bins for cr_num_endpoints_mode

Uncovered bins
cp_num_endpointscp_modeCOUNTAT LEASTNUMBERSTATUS
[auto[4]] [boot_req_mode] 0 1 1


Excluded/Illegal bins
cp_num_endpointscp_modeCOUNTSTATUS
[auto[0]] [boot_req_mode , auto_req_mode , sw_mode] -- Excluded (3 bins)


Covered bins
cp_num_endpointscp_modeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] boot_req_mode 84 1 T37 1 T56 1 T78 1
auto[1] auto_req_mode 70 1 T7 1 T8 1 T33 1
auto[1] sw_mode 1156 1 T105 1 T88 1 T179 1
auto[2] boot_req_mode 3 1 T31 1 T170 1 T171 1
auto[2] auto_req_mode 3 1 T180 1 T181 1 T182 1
auto[2] sw_mode 129 1 T183 1 T184 77 T185 1
auto[3] boot_req_mode 3 1 T186 1 T187 1 T188 1
auto[3] auto_req_mode 6 1 T9 1 T173 1 T189 1
auto[3] sw_mode 136 1 T172 1 T190 1 T191 41
auto[4] auto_req_mode 3 1 T192 1 T193 1 T194 1
auto[4] sw_mode 110 1 T174 1 T175 92 T176 1
auto[5] boot_req_mode 1 1 T195 1 - - - -
auto[5] auto_req_mode 6 1 T38 1 T196 1 T197 1
auto[5] sw_mode 202 1 T32 40 T89 1 T82 28
auto[6] boot_req_mode 3 1 T198 1 T199 1 T200 1
auto[6] auto_req_mode 2 1 T41 1 T178 1 - -
auto[6] sw_mode 182 1 T177 1 T201 6 T202 61
auto[7] boot_req_mode 39 1 T28 1 T42 1 T120 1
auto[7] auto_req_mode 39 1 T29 1 T80 1 T203 1
auto[7] sw_mode 1267 1 T1 1 T30 1 T57 1

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